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91. 发明专利

JPH0969610A INTEGRATED SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JPH0969610A
公开(公告)日：1997-03-11
申请号：JP22341295
申请日：1995-08-31
申请人： HITACHI LTD
发明人： HISAMOTO MASARU , SHIBA TAKEO
IPC分类号： H01L27/08 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To simplify the formation of SOI-MOSFET in which there is no possibility of occurring of substrate floating by forming NMOSFET and PMOSFET in an active area of an SOI film and assigning a diffusion layer of the PMOSFET so as to be electrically connected to a channel of the NMOSFET. SOLUTION: An Si oxide film 110 and a monocrystal Si film are formed on an Si substrate 120 for forming a SOI substrate. Then, with the use of the Si oxide film and an Si nitride film, an exposed part of the monacrystal Si film is oxidized for forming a thick oxide film 900 for element isolation, and then the Si nitride film and the oxide film are removed. Then, after a gate oxide film 910 is formed, a gate electrode 500 is formed. An N-type diffusion layer 300 of low resistance is formed with the gate electrode 500 and a specified mask pattern as masks, and a P-type diffusion layer 400 of low resistance is formed with the gate electrode 500 and another mask pattern as masks, and a wiring 700 connected to the N-type diffusion layer 300 and the P-type diffusion layer 400 is formed.

92. 发明专利

JPH0945916A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH0945916A
公开(公告)日：1997-02-14
申请号：JP19726995
申请日：1995-08-02
申请人： HITACHI LTD
发明人： MIYAUCHI AKIHIRO , KIYOTA YUKIHIRO , KOBAYASHI NOBUYOSHI , NAKAMURA YOSHITAKA , ANDO TOSHIO , SHIBA TAKEO , SUZUKI TAKAYA
IPC分类号： H01L29/78
摘要： PROBLEM TO BE SOLVED: To reduce the facet generated at a part where the insulator spacer next to a gate electrode and a selective silicon film contact by setting the main surface on a semiconductor substrate to (100) face and setting a gate direction to a specific angle or less to (100) face. SOLUTION: A separation insulation film is formed around an element region on one surface of a substrate 100 consisting of silicon wafer which is a p type and whose crystal orientation is a (100) plane. A thermal oxidation film 102 which is 5nm thick is formed by the wet oxidation method at 850 deg.C, ion is implanted for adjusting a threshold voltage, a polycrystalline silicon film is 200nm thick is formed on an entire surface, and a gate 103 with a gate width of 0.3μm is formed by the photolithography method. Then, by making the gate 103 parallel with a direction which is equivalent to crystal axis, a facet generated at a part where the insulator spacer of the side wall of the gate contacts the silicon epitaxial film selectively grown on a source and drain regions is reduced.

93. 发明专利

JPH08227997A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH08227997A
公开(公告)日：1996-09-03
申请号：JP3042195
申请日：1995-02-20
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： SHIBA TAKEO , KIYOTA YUKIHIRO , MIYAUCHI AKIHIRO , ONISHI KAZUHIRO , SHIMAMOTO HIROMI , UCHINO TAKASHI
IPC分类号： H01L27/088 , H01L21/336 , H01L21/8234 , H01L29/78
摘要： PURPOSE: To evade the punchthrough between the source and the drain of a MOSFET, to raise the drain current and the mutual conductance, and to lower the parasitic capacitances and the parasitic resistances of the source and the drain. CONSTITUTION: A MOSFET semiconductor device is composed of a heavily doped first conductivity type source diffusion layer 5 provided in a semiconductor substrate on an insulating film substrate 1, a single crystalline silicon semiconductor layer 9 deposited on it, a heavily doped first conductivity type sourve diffusion layer 23, a heavily doped first conductivity type drain diffusion layer 22, a metal gate electrode 16, and drain and source electrodes 17, 18 made of metal. Consequently, it becomes possible to speed up a semiconductor integrated circuit, and to speed up a system which uses this semiconductor integrated circuit.

94. 发明专利

JPH07176537A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH07176537A
公开(公告)日：1995-07-14
申请号：JP31940293
申请日：1993-12-20
申请人： HITACHI LTD
发明人： SHIBA TAKEO , TAMAOKI YOICHI , KONDO MASAO , UCHINO TAKASHI , ONISHI KAZUHIRO , MIYAUCHI AKIHIRO
IPC分类号： H01L29/73 , H01L21/331 , H01L29/732
摘要： PURPOSE:To enable a semiconductor device provided with a bipolar transistor small in parasitic junction capacitance, high in operation speed, and low in power consumption to be manufactured high in controllability. CONSTITUTION:An element isolating region 113, an outer base upper opening, and an insulating layer 131 located between an emitter electrode 134 and a base lead-out electrode 24 are formed in a self-aligned manner to a protrudent laminated insulating film formed in a region of the surface of a semiconductor substrate 100 where a collector 104 and a base 130 are to be formed.

95. 发明专利

JPH07130756A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH07130756A
公开(公告)日：1995-05-19
申请号：JP27648093
申请日：1993-11-05
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： USAMI MITSUO , SHIBA TAKEO , SHIMAMOTO HIROMI
IPC分类号： H01L29/73 , H01L21/02 , H01L21/331 , H01L21/338 , H01L21/76 , H01L27/12 , H01L29/732 , H01L29/812
摘要： PURPOSE:To obtain a technology with which bipolar transistors and resistance elements are integrated with a high density so as to have high performances by a method wherein a first trench which separates adjacent transistors electrically from each other and a second trench which separates the collector electrodes of the adjacent transistors electrically from each other and is deeper than the first trench are provided. CONSTITUTION:A semiconductor integrated circuit device has a plurality of vertical bipolar transistors(BT's) whose collectors 3 and 4 are directly connected to metal collector electrodes 5. In a semiconductor integrated circuit device like this, a first trench which separates the adjacent BT's electrically from each other and a second trench 64 which separates the collector electrodes 5 of the adjacent BT's electrically from each other and is deeper than the first trench are provided. For instance, an opening is selectively formed in the inner silicon oxide layer 13 of an SOI wafer to form the rear collector electrodes 5. Further, surface base electrodes 7 and surface emitter electrodes 6 are flattened by an insulator layer 11 and a support substrate 9 is attached to the flat surface with adhesive.

96. 发明专利

JPH0722431A MANUFACTURE OF BIPOLAR TRANSISTOR 失效
公开(公告)号：JPH0722431A
公开(公告)日：1995-01-24
申请号：JP16354093
申请日：1993-07-01
申请人： HITACHI LTD
发明人： UCHINO TAKASHI , SHIBA TAKEO , KIKUCHI TOSHIYUKI , KONNO AKIHIKO
IPC分类号： H01L29/73 , H01L21/331 , H01L29/732
摘要： PURPOSE:To lower the temperature of a bipolar transistor manufacturing process, and to form thin base layers. CONSTITUTION:When an emitter region 8 is formed after the formation of a base region 7, a thin second insulating film 12 and amorphous silicon 15 containing impurities of a conductivity type the same as that of the collector are laminated on the sidewall of an opening 7a, and the amorphous silicon 15 in the opening is removed and opened by dry etching and the insulating film 12 is exposed. Furthermore, the insulating film is removed and opened with an etching solution, and the base region 8 is exposed. Finally, an emitter electrode 11 is formed with polycrystalline silicon along with the formation of the emitter region 8 by the injection of impurities of a conductivity type the same as that of the collector. Consequently, high speed operation of the device becomes feasible since it becomes possible to thin the base layer. Besides, it becomes possible to reduce the emitter resistance approximately to 70% of the former value. Furthermore, it becomes possible to prevent the emitter and the collector from being short-circuited electrically, since the emitter electrode on the opening hem is removed in a contact-hole-forming process.

97. 发明专利

JPH03101236A HETERO JUNCTION SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH03101236A
公开(公告)日：1991-04-26
申请号：JP23703589
申请日：1989-09-14
申请人： HITACHI LTD
发明人： SHIBA TAKEO , KONDO MASAO , YAMAGUCHI KUNIHIKO , HONMA NORIYUKI , NAKAMURA TORU
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8222 , H01L21/8229 , H01L27/06 , H01L27/102 , H01L29/161 , H01L29/165 , H01L29/737
摘要： PURPOSE:To reduce the accumulated charge at the time of saturation of a transistor so as to shorten the writing time by putting the collector and base junction of a vertical bipolar transistor in hetero junction, using the uppermost layer of this transistor where a memory cell is formed as a collector. CONSTITUTION:An n-type buried diffusion layer 2 to become an emitter, a p-type base diffusion layer 7, and an n-type collector diffusion layer 9 are formed in an Si substrate 1, and thereon a fine crystal Si11, which has wider band gap than the base diffusion layer 7 and to which n-type impurities are added, is accumulated. Moreover, the SBD is a shielded type SBD shielded from the Si substrate 1 by a p-type diffusion layer 8, and there an n-type buried diffusion layer 3, a p-type diffusion layer 8 to shield the SBD, and an n-type diffusion layer 10 to become the cathode of SBD are formed, and thereon a metallic electrode 15 is accumulated to form SBD. These, the collector regions 9 and 11 of a transistor and the cathode region 10 of SBD, are connected by a polycrystalline Si film 12 where n-type impurities are diffused. Hereby, the charges accumulated in the regions 9 and 11 at the time of saturation of a transistor can be reduced, and the writing operation to invert a flip flop circuit can be quickened.

98. 发明专利

JPS61256759A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS61256759A
公开(公告)日：1986-11-14
申请号：JP9776685
申请日：1985-05-10
申请人： HITACHI LTD
发明人： NISHIOKA TAIJO , SHIBA TAKEO , JINRIKI HIROSHI , MUKAI KIICHIRO
IPC分类号： H01L27/082 , G11C11/34 , G11C11/411 , H01L21/8222 , H01L21/8229 , H01L27/06 , H01L27/10 , H01L27/102
摘要： PURPOSE:To reduce the area of a memory cell, by inserting a Schottky barrier diode or a capacitor in region beneath a digit line, which is not used before, so that the diode or capacitor is insulated from the digit line. CONSTITUTION:In an FF type memory cell, an SBD is newly formed in a region 5 beneath a digit line 2. A wired section 6 is an anode and connected to a word line 3 through a via hole 17. The anode 6 is insulated from the digit line. An Si substrate B is insulated and isolated 9 and islands are formed. Transistors, a load resistor RMC and an SBD are formed on each island. An N layer 10 is a low resistor RL. A layer 11 is a high resistance load. Layers 12-14 are a base layer, an emitter layer and a collector layer. A PtSi2 layer 15 is Schottdy-contacted with an N layer 16. T-W alloy 17 is made to be an upper electrode. The electrode 17 and a digit line 19 are insulated by PSG 18. The electrode 17 is connected to the word line 3 through the via hole 7. When the thickness of the PSG 18 is made to be 2,000 Angstrom or more, signal delay due to the capacity between the digit line and the electrode 17 can be neglected.

99. 发明专利

JPS60164356A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60164356A
公开(公告)日：1985-08-27
申请号：JP1833784
申请日：1984-02-06
申请人： HITACHI LTD
发明人： NANBA MITSUO , SHIBA TAKEO
IPC分类号： H01L29/417 , H01L21/331 , H01L29/72 , H01L29/73 , H01L29/732
摘要： PURPOSE:To assure the excellent stability of electric characteristics by a method wherein an isolation oxide mask structure is composed of three layers comprising Si3N4/poly-Si/SiO2 assuming the sidewall oxide length of poly-Si to be BC region while a poly-Si layer formed along the periphery of an Si island to be a seed crystal for selective growing process. CONSTITUTION:Within a transistor made of an Si substrate 1 to be an N type collector region, a P type base region (true base region) 3, base leading parts 6 from external base regions (base-control regions) are connected to an emitter leading part 8 through the intermediary of insulating films 7 with thickness isotropic to an emitter regions 5. Besides, the emitter 5 is formed into a square region omnidistant from the edges of an isolation oxide film 2. 9 is an emitter region and 10 is a base electrode. Through these procedures, base-contact (gamma) and emitters 5, 12 may be doubly and selfmatchingly formed conforming to the processes such as poly-Si sidewall oxidation and selective poly-Si growing process subject to excellent controllability to assure the excellent stability of electric characteristics.

100. 发明专利

JPS5958838A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS5958838A
公开(公告)日：1984-04-04
申请号：JP16835582
申请日：1982-09-29
申请人： Hitachi Ltd
发明人： TAMAOKI YOUICHI , SHIBA TAKEO , SAGARA KAZUHIKO , KAWAMURA MASAO
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/331 , H01L21/76 , H01L21/762 , H01L21/763 , H01L29/73
CPC分类号： H01L21/76224 , H01L21/76 , H01L21/763
摘要： PURPOSE: To reduce wiring capacitance through a simple method by forming a shallow groove, an upper section thereof is coated with an insulating film, between deep narrow grooves for isolating an element, the surfaces thereof are coated with dielectrics.
CONSTITUTION: A buried collector layer 2 and an active layer 3 are superposed on the (100) face of an Si substrate 1, an Si
3 N
4 mask 5 is executed to the SiO
2 film 4 of the surface and windows 6, 8 are bored, and window width is made narrower than depth. The vertical grooves 9 are formed through reactive sputtering etching, SiO
2 4 is removed selectively, and the groove 10 shallower than the layer 2 and grooves 11 deeper than that are formed through second etching. The surface is coated with SiO
2 12, the film 5 is removed, and poly Si 14 is deposited through novel Si
3 N
4 13 to fill the grooves. The layer 14 is removed through isotropic etching, Si
3 N
4 13 is exposed, and SiO
2 15 is formed to the surface of the poly Si 14 and coated with Si
3 N
4 16. A transistor is manufactured through a predetermined method. In a bipolar device by the constitution, wiring capacitance is reduced because there are thick oxide films 12, 15 in an isolation region, and a circuit is accelerated by approximately 50%.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：为了通过简单的方法通过形成浅沟槽来减少布线电容，其上部分覆盖有用于隔离元件的深窄沟槽之间的绝缘膜，其表面被电介质涂覆。构成：将掩埋集电极层2和有源层3重叠在Si衬底1的（100）面上，对表面的SiO 2膜4施加Si 3 N 4掩模5，并且窗口6,8被钻孔，并且窗口宽度比深度更窄。通过反应性溅射蚀刻形成垂直槽9，选择性地除去SiO 2，并且比第二蚀刻浅的槽10和比第二蚀刻形成的槽11更深的沟槽10。表面涂有SiO 2 12，除去膜5，通过新颖的Si 3 N 4 13沉积多晶硅14以填充凹槽。通过各向同性蚀刻去除层14，暴露Si 3 N 4 13，并且在多晶Si 14的表面上形成SiO 15并涂覆有Si 3 N 4 16.通过预定方法制造晶体管。在通过该结构的双极型器件中，由于在隔离区域中存在厚的氧化物膜12,15，并且电路加速了大约50％，所以布线电容减小。

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