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91. 发明专利

JPS6038898B2 失效
公开(公告)号：JPS6038898B2
公开(公告)日：1985-09-03
申请号：JP14651776
申请日：1976-12-08
申请人： HITACHI LTD
发明人： ETO YOSHIZUMI
IPC分类号： H03C1/60 , H03D1/24 , H03H15/00 , H03H17/02 , H04L27/02 , H04L27/04 , H04N5/38

92. 发明专利

JPS5184515A 失效
公开(公告)号：JPS5184515A
公开(公告)日：1976-07-23
申请号：JP876775
申请日：1975-01-22
申请人： HITACHI LTD
发明人： ETO YOSHIZUMI
IPC分类号： H04N5/20 , H03G11/00

93. 发明专利

JP2590155B2 失效
公开(公告)号：JP2590155B2
公开(公告)日：1997-03-12
申请号：JP31193587
申请日：1987-12-11
申请人： HITACHI LTD
发明人： IZUMIDA MORIJI , MITA SEIICHI , DOI NOBUKAZU , ISHII HIROTAKE , ETO YOSHIZUMI , HARA FUMIO
IPC分类号： G11B7/09 , G11B21/10

94. 发明专利

JP2510658B2 失效
公开(公告)号：JP2510658B2
公开(公告)日：1996-06-26
申请号：JP5255988
申请日：1988-03-08
申请人： HITACHI LTD
发明人： OKIGUCHI KOTARO , TAKESHITA KAZUYUKI , ETO YOSHIZUMI
IPC分类号： G11B20/10 , H04N5/91 , H04N5/92

95. 发明专利

JPH05227043A METHOD AND CIRCUIT FOR IDENTIFYING DIGITAL SIGNAL 失效
公开(公告)号：JPH05227043A
公开(公告)日：1993-09-03
申请号：JP2510192
申请日：1992-02-12
申请人： HITACHI LTD
发明人： UMEMOTO MASUO , ETO YOSHIZUMI , ISHII HIROTAKE , SAWAMURA HIDEHIKO
IPC分类号： G11B20/14 , G11B20/18 , H03M13/23 , H04L1/00 , H04L25/49 , H04N5/92
摘要： PURPOSE:To more accurately identify a digital signal by a compact circuit. CONSTITUTION:A magnetic tape records modulated binary digital signals. A digital A/D converter 4 finds out a digital decoding value of a reproducing signal read out from the magnetic tape through a head 1 and a reproducing equalizing circuit 3 and its probability in accordance with its signal level and outputs the obtained result as a temporary identification(ID) value. If a decoded value dropped at its probability and not satisfied with a modulation rule exists in a temporary ID value string, a temporary ID correcting circuit 5 corrects the decoded value. Consequently ID considering the reliability of the modulation rule and a reproducing bit value can be executed by the compact circuit.

96. 发明专利

JPH04143904A DIGITAL PICTURE RECORDING DEVICE 失效
公开(公告)号：JPH04143904A
公开(公告)日：1992-05-18
申请号：JP26643290
申请日：1990-10-05
申请人： HITACHI LTD
发明人： UMEMOTO MASUO , ISHII HIROTAKE , SAWAMURA HIDEHIKO , ETO YOSHIZUMI
IPC分类号： G11B5/09 , G11B20/10 , G11B20/14
摘要： PURPOSE:To miniaturize the device by providing a code converter and a time base compressing device, and recording a code word subjected to time base compression in a recording medium to narrow a winding angle without shortening the recording wavelength. CONSTITUTION:In a recording processing part of an image signal to be recorded, digital data, and a code word of (n) bits are converted to (m) bits in which '1' and '0' are continued by (d) bits or more by a code converter 10. Before recording this code word of (m) bits, it is converted to a code word of (m) bits (m>n) in which '1' and '0' are continued by (d) bits or more by a time base compressing device 11. Compressibility alpha in this case satisfies m/nd

97. 发明专利

JPH02207637A PICTURE STUFF CONTROL CIRCUIT 失效
公开(公告)号：JPH02207637A
公开(公告)日：1990-08-17
申请号：JP2741689
申请日：1989-02-08
申请人： HITACHI LTD
发明人： NAKABASHI TOMOKO , KINOSHITA TAIZO , ETO YOSHIZUMI
IPC分类号： H04L29/08 , H04L13/08
摘要： PURPOSE:To realize the stuffing by plural bits with the unit of arbitrary bit by monitoring a write address at the timing of a read address of a memory for stuffing being digital quantity, and generating a stuff control signal from the digital arithmetic result of the address value. CONSTITUTION:An input picture signal is stored to a memory 1 for stuff by a writing clock and converted to a transmission rate by being read according to a reading clock. The address control of the memory 1 for stuff is executed by an address arithmetic circuit 3. A write address counter 32 counts the write address in the internal part of the memory for stuff and a read address counter 33 counts the read address. Both pieces of address information are sent to an address computing element 31 and as the result of the arithmetic, a stuff position is detected. Then, a control signal is sent to a stuff information marking circuit 4. Thus, the signal processing of a stuff control circuit is digitally executed and the stuff can be controlled by the plural bits with the unit of arbitrary bit.

98. 发明专利

JPH0232688A ADAPTIVE CONVERSION ENCODER 失效
公开(公告)号：JPH0232688A
公开(公告)日：1990-02-02
申请号：JP18190188
申请日：1988-07-22
申请人： HITACHI LTD
发明人： HANIYU HIROYUKI , DOI NOBUKAZU , MITA SEIICHI , IZUMIDA MORIJI , ETO YOSHIZUMI
IPC分类号： G06T9/00 , H03M7/30 , H03M7/38 , H04N1/41 , H04N5/926 , H04N19/00 , H04N19/115 , H04N19/126 , H04N19/134 , H04N19/136 , H04N19/14 , H04N19/176 , H04N19/186 , H04N19/189 , H04N19/196 , H04N19/46 , H04N19/59 , H04N19/60 , H04N19/625 , H04N19/70 , H04N19/85
摘要： PURPOSE:To heighten compressibility and to keep the required number of bits i.e., a recording rate constant by changing bit allocation required at every block based on a pattern. CONSTITUTION:When an encoding block is of a high class bit (c), an excessive bit 26 is allocated to the null area 18 of low bit class (a) in a monitoring block area so as to be the number of reference bits, and when a decoding block is of the high bit class (c), a part of bits allocated to the low bit class (a) is returned to an original position, then, decoded. In such a way, the compressibility can be heightened, and also, the data rate of recording can be kept constant. Therefore, it is possible to realize adaptive conversion encoding suitable for a DVTR.

99. 发明专利

JPH0223790A METHOD AND CIRCUIT FOR REGISTRATION CORRECTION 失效
公开(公告)号：JPH0223790A
公开(公告)日：1990-01-25
申请号：JP17270988
申请日：1988-07-13
申请人： HITACHI LTD
发明人： MIMURA ITARU , AKIYAMA TOSHIYUKI , ETO YOSHIZUMI , OZAWA NAOKI , TAKAHASHI KENJI
IPC分类号： H04N9/093
摘要： PURPOSE:To obtain a video signal free from a color slip and in addition, of high resolution even in a color camera using a solidstate image pickup element by controlling the factor of a two-dimensional filter according to a registration error. CONSTITUTION:A lens parameter detection circuit 1 detects parameters such as the zoom ratio Z of a lens, a stop value F, subject distance L, etc., in a photographing state, and outputs them to an aberration operation circuit 2. The operation circuit 2 operates the aberration quantity of the lens from the supplied lens parameters, and outputs it to a factor operation circuit 3. The factor operation circuit 3 determines the factor of the lens from the supplied aberration quantity of the lens, and outputs it to a registration correction circuit (two-dimensional filter) 4. The correction circuit 4 multiplies an input signal by the factor, and corrects registration.

100. 发明专利

JPH01227269A RECORDING AND REPRODUCING DEVICE 失效
公开(公告)号：JPH01227269A
公开(公告)日：1989-09-11
申请号：JP5255988
申请日：1988-03-08
申请人： HITACHI LTD
发明人： OKIGUCHI KOTARO , TAKESHITA KAZUYUKI , ETO YOSHIZUMI
IPC分类号： G11B20/10 , H04N5/91 , H04N5/92
摘要： PURPOSE:To prevent the degradation of picture quality due to dubbing by providing a dubbing interface circuit. CONSTITUTION:At the time of dubbing recording, a dubbing interface circuit is switched to (b) side. A regenerating digital signal is inputted from an input terminal 10, passes through the circuit 2, through a recording signal processing circuit 5 and recorded in a medium. At the time of dubbing reproducing, a dubbing interface circuit 11 is switched to (i) side, the regenerating digital signal processed by a regenerating signal processing circuit 6 passes through the circuit 11 and supplied to another recording and reproducing device from an output terminal 12. Since the regenerating digital signal does not pass through either a pre-filter 3 or an interposed filter 7 like this, the degradation of a frequency characteristic can be prevented.

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