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91. 发明授权

US08871588B2 Reverse construction integrated circuit 有权
标题翻译：反向施工集成电路
公开(公告)号：US08871588B2
公开(公告)日：2014-10-28
申请号：US13475716
申请日：2012-05-18
申请人： David H. Wells , H. Montgomery Manning
发明人： David H. Wells , H. Montgomery Manning
IPC分类号： H01L21/8242 , H01L21/762 , H01L21/84 , H01L27/108
CPC分类号： H01L27/10885 , H01L21/76254 , H01L21/84 , H01L27/10876 , H01L27/10882
摘要： A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate.
摘要翻译：制造存储单元的方法包括在载体衬底上形成多个掺杂半导体层。该方法还包括形成由绝缘材料隔开的多个数字线。数字线排列在掺杂半导体层之上。该方法还包括将多个沟槽蚀刻到掺杂半导体层中。该方法还包括将绝缘材料沉积到多个沟槽中以形成多个电隔离的晶体管柱。该方法还包括将形成在载体衬底上的结构的至少一部分结合到主体衬底。该方法还包括从载体衬底分离载体衬底。

92. 发明申请

US20120168903A1 Semiconductor Constructions Containing Tubular Capacitor Storage Nodes, And Retaining Structures Along Portions Of The Tubular Capacitor Storage Nodes 有权
标题翻译：包含管状电容器存储节点和保留结构的半导体结构沿管状电容器存储节点的一部分
公开(公告)号：US20120168903A1
公开(公告)日：2012-07-05
申请号：US13413552
申请日：2012-03-06
申请人： H. Montgomery Manning , Thomas M. Graettinger
发明人： H. Montgomery Manning , Thomas M. Graettinger
IPC分类号： H01L29/02
CPC分类号： H01L27/10894 , H01L27/10817 , H01L27/10852 , H01L28/91 , H01L29/945 , Y10S257/906
摘要： The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.
摘要翻译：本发明包括半导体结构，并且还包括形成多个电容器器件的方法。本发明的示例性方法包括在绝缘材料的开口内形成导电储存节点材料以形成导电容器。形成与至少一些容器物理接触的保持结构格子，随后去除绝缘材料以露出容器的外表面。保持结构可以减轻容器结构的结构完整性的倒塌或其它损失。导电容器对应于第一电容器电极。在容器的外侧壁暴露之后，电介质材料形成在容器内并沿外露的外侧壁。随后，在电介质材料上形成第二电容器电极。第一和第二电容器电极与电介质材料一起形成多个电容器器件。

93. 发明授权

US08207564B2 Memory cell, pair of memory cells, and memory array 有权
标题翻译：存储单元，存储单元对和存储器阵列
公开(公告)号：US08207564B2
公开(公告)日：2012-06-26
申请号：US12844045
申请日：2010-07-27
申请人： H. Montgomery Manning , David H. Wells
发明人： H. Montgomery Manning , David H. Wells
IPC分类号： H01L27/108 , H01L21/70
CPC分类号： H01L27/10885 , H01L27/0207 , H01L27/10823
摘要： A memory cell, device, and system include a memory cell having a shared digitline, a storage capacitor, and a plurality of access transistors configured to selectively electrically couple the storage capacitor with the shared digitline. The shared digitline couples with adjacent memory cells, and the plurality of access transistors selects which adjacent memory cell is coupled to the shared digitline. A method of forming the memory cell includes forming a buried digitline in a substrate and a vertical pillar in the substrate immediately adjacent to the buried digitline. A dual gate transistor is formed on the vertical pillar with a first end electrically coupled to the buried digitline and a second end coupled to a storage capacitor formed thereto.
摘要翻译：存储器单元，器件和系统包括具有共享数字线的存储单元，存储电容器和被配置为选择性地将存储电容器与共享数字线电耦合的多个存取晶体管。共享数字线耦合到相邻存储器单元，并且多个存取晶体管选择哪个相邻存储器单元耦合到共享数字线。形成存储单元的方法包括在衬底中形成掩埋数字线，并且在与衬底数字线相邻的衬底中形成垂直柱。双栅晶体管形成在垂直柱上，第一端电耦合到掩埋数字线，第二端耦合到形成于其上的存储电容器。

94. 发明授权

US08154064B2 Semiconductor constructions 有权
标题翻译：半导体结构
公开(公告)号：US08154064B2
公开(公告)日：2012-04-10
申请号：US12853948
申请日：2010-08-10
申请人： H. Montgomery Manning , Thomas M. Graettinger
发明人： H. Montgomery Manning , Thomas M. Graettinger
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/10894 , H01L27/10817 , H01L27/10852 , H01L28/91 , H01L29/945 , Y10S257/906
摘要： The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.
摘要翻译：本发明包括半导体结构，并且还包括形成多个电容器器件的方法。本发明的示例性方法包括在绝缘材料的开口内形成导电储存节点材料以形成导电容器。形成与至少一些容器物理接触的保持结构格子，随后去除绝缘材料以露出容器的外表面。保持结构可以减轻容器结构的结构完整性的倒塌或其它损失。导电容器对应于第一电容器电极。在容器的外侧壁暴露之后，电介质材料形成在容器内并沿外露的外侧壁。随后，在电介质材料上形成第二电容器电极。第一和第二电容器电极与电介质材料一起形成多个电容器器件。

95. 发明申请

US20120009779A1 CONTACT FORMATION 有权
标题翻译：联系方式
公开(公告)号：US20120009779A1
公开(公告)日：2012-01-12
申请号：US13237126
申请日：2011-09-20
申请人： James Mathew , H. Montgomery Manning
发明人： James Mathew , H. Montgomery Manning
IPC分类号： H01L21/768
CPC分类号： H01L21/76804 , H01L21/76801 , H01L21/76831 , H01L27/0207 , H01L27/10855 , H01L27/10888
摘要： The present disclosure includes various methods of contact embodiments. One such method embodiment includes forming a trench in an insulator stack material of a particular thickness. This method includes forming a filler material in the trench and removing the filler material to a particular depth that is less than the particular thickness of the insulator stack material. This method also includes forming a spacer material on at least one side surface of the trench to the particular depth of the filler material and forming a conductive material in the trench over the filler material.
摘要翻译：本公开包括各种接触实施方式。一种这样的方法实施例包括在特定厚度的绝缘体堆叠材料中形成沟槽。该方法包括在沟槽中形成填充材料，并将填料材料移除到小于绝缘体堆叠材料的特定厚度的特定深度。该方法还包括在沟槽的至少一个侧表面上形成隔离材料至填充材料的特定深度，并在填充材料上的沟槽中形成导电材料。

96. 发明授权

US08084142B2 Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects 有权
标题翻译：向源极/漏极区形成导电接触的方法以及形成局部互连的方法
公开(公告)号：US08084142B2
公开(公告)日：2011-12-27
申请号：US11525762
申请日：2006-09-21
申请人： Cem Basceri , Gurtej S. Sandhu , H. Montgomery Manning
发明人： Cem Basceri , Gurtej S. Sandhu , H. Montgomery Manning
IPC分类号： H01L21/44 , H01L21/4763 , H01L29/40
CPC分类号： H01L21/76823 , H01L21/28512 , H01L21/76895 , Y10T428/12542
摘要： The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.
摘要翻译：本发明包括形成对场效应晶体管的源极/漏极区的导电接触的方法，以及形成局部互连的方法。在一个实施方案中，形成到场效应晶体管的源/漏区的导电接触的方法包括在晶体管栅极和场效应晶体管的沟道区之间提供栅介质材料。至少一些栅极电介质材料延伸以在场效应晶体管的至少一个源极/漏极区域上接收。接收在一个源极/漏极区域上的栅极电介质材料暴露于有效地将其从电绝缘转变为导电并与一个源极/漏极区域导电接触的条件。考虑了其他方面和实现。

97. 发明授权

US08012674B2 Efficient pitch multiplication process 有权
标题翻译：高效的音调乘法过程
公开(公告)号：US08012674B2
公开(公告)日：2011-09-06
申请号：US12687005
申请日：2010-01-13
申请人： Mark Fischer , Stephen Russell , H. Montgomery Manning
发明人： Mark Fischer , Stephen Russell , H. Montgomery Manning
IPC分类号： G03F7/26
CPC分类号： H01L29/06 , H01L21/0338 , H01L21/3088
摘要： Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which an underlying substrate is etched.
摘要翻译：通过通过掩模处理衬底来形成集成电路的间距倍增和非间距倍数特征，例如集成电路的阵列，接口和外围区域中的特征。通过图案化光刻胶层来形成掩模，该光致抗蚀剂层同时限定对应于集成电路的阵列，界面和外围区域中的特征的掩模元件。将图案转移到无定形碳层。侧壁间隔物形成在图案化无定形碳层的侧壁上。沉积一层保护材料，然后将其图案化以暴露阵列区域中的掩模元件和界面或外围区域的选定部分。除去阵列区域或其它暴露部分中的无定形碳，从而在阵列区域中留下包括独立的，间距倍增的间隔物的图案。去除保护材料，在阵列区域中留下间距倍数间隔物的图案，并在界面和外围区域留下非间距倍增的掩模元件。将图案转移到硬掩模层，通过该硬掩模层蚀刻下面的基底。

98. 发明授权

US07923308B2 Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects 有权
公开(公告)号：US07923308B2
公开(公告)日：2011-04-12
申请号：US11478715
申请日：2006-06-30
申请人： Cem Basceri , Gurtej S. Sandhu , H. Montgomery Manning
发明人： Cem Basceri , Gurtej S. Sandhu , H. Montgomery Manning
IPC分类号： H01L21/332 , H01L21/336 , H01L21/4763
CPC分类号： H01L21/76823 , H01L21/28512 , H01L21/76895 , Y10T428/12542
摘要： The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.

99. 发明申请

US20100233875A1 CONTACT FORMATION 有权
标题翻译：联系方式
公开(公告)号：US20100233875A1
公开(公告)日：2010-09-16
申请号：US12787684
申请日：2010-05-26
申请人： James Mathew , H. Montgomery Manning
发明人： James Mathew , H. Montgomery Manning
IPC分类号： H01L21/768
CPC分类号： H01L21/76804 , H01L21/76801 , H01L21/76831 , H01L27/0207 , H01L27/10855 , H01L27/10888
摘要： The present disclosure includes various method of contact embodiments. One such method embodiment includes creating a trench in an insulator stack material of a particular thickness and having a portion of the trench positioned between two of a number of gates. This method includes depositing a filler material in the trench and etching the filler material to a particular depth that is less than the particular thickness of the insulator stack material. This method also includes depositing a spacer material to at least one side surface of the trench to the particular depth of the filler material and depositing a conductive material into the trench over the filler material.
摘要翻译：本公开包括各种接触实施方式。一种这样的方法实施例包括在特定厚度的绝缘体堆叠材料中产生沟槽，并且具有位于多个栅极之间的沟槽的一部分。该方法包括在沟槽中沉积填充材料并将填充材料蚀刻到小于绝缘体堆叠材料的特定厚度的特定深度。该方法还包括将间隔物材料沉积到沟槽的至少一个侧表面至填充材料的特定深度，并将导电材料沉积在填料材料上的沟槽中。

100. 发明授权

US07666578B2 Efficient pitch multiplication process 有权
标题翻译：高效的音调乘法过程
公开(公告)号：US07666578B2
公开(公告)日：2010-02-23
申请号：US11521851
申请日：2006-09-14
申请人： Mark Fischer , Stephen Russell , H. Montgomery Manning
发明人： Mark Fischer , Stephen Russell , H. Montgomery Manning
IPC分类号： G03F7/26 , G03F7/00
CPC分类号： H01L29/06 , H01L21/0338 , H01L21/3088
摘要： Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which an underlying substrate is etched.
摘要翻译：通过通过掩模处理衬底来形成集成电路的间距倍增和非间距倍数特征，例如集成电路的阵列，接口和外围区域中的特征。通过图案化光刻胶层来形成掩模，该光致抗蚀剂层同时限定对应于集成电路的阵列，界面和外围区域中的特征的掩模元件。将图案转移到无定形碳层。侧壁间隔物形成在图案化无定形碳层的侧壁上。沉积一层保护材料，然后将其图案化以暴露阵列区域中的掩模元件和界面或外围区域的选定部分。除去阵列区域或其它暴露部分中的无定形碳，从而在阵列区域中留下包括独立的，间距倍增的间隔物的图案。去除保护材料，在阵列区域中留下间距倍数间隔物的图案，并在界面和外围区域留下非间距倍增的掩模元件。将图案转移到硬掩模层，通过该硬掩模层蚀刻下面的基底。

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