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91. 发明授权

US07422635B2 Methods and apparatus for processing microfeature workpieces, e.g., for depositing materials on microfeature workpieces 失效
标题翻译：用于加工微型工件的方法和装置，例如用于在微型工件上沉积材料
公开(公告)号：US07422635B2
公开(公告)日：2008-09-09
申请号：US10652461
申请日：2003-08-28
申请人： Lingyi A. Zheng , Trung T. Doan , Lyle D. Breiner , Er-Xuan Ping , Kevin L. Beaman , Ronald A. Weimer , David J. Kubista , Cem Basceri
发明人： Lingyi A. Zheng , Trung T. Doan , Lyle D. Breiner , Er-Xuan Ping , Kevin L. Beaman , Ronald A. Weimer , David J. Kubista , Cem Basceri
IPC分类号： C23C16/00 , C23C16/455 , H01L21/306
CPC分类号： C23C16/45546 , C23C16/45578 , C23C16/4583
摘要： The present disclosure suggests several systems and methods for batch processing of microfeature workpieces, e.g., semiconductor wafers or the like. One exemplary implementation provides a method of depositing a reaction product on each of a batch of workpieces positioned in a process chamber in a spaced-apart relationship. A first gas may be delivered to an elongate first delivery conduit that includes a plurality of outlets spaced along a length of the conduit. A first gas flow may be directed by the outlets to flow into at least one of the process spaces between adjacent workpieces along a first vector that is transverse to the direction in which the workpieces are spaced. A second gas may be delivered to an elongate second delivery conduit that also has outlets spaced along its length. A second gas flow of the second gas may be directed by the outlets to flow into the process spaces along a second vector that is transverse to the first direction.
摘要翻译：本公开提出了用于批量处理微特征工件（例如半导体晶片等）的几种系统和方法。一个示例性实施方案提供了一种在间隔开的关系中将反应产物沉积在处理室中的一批工件的每一个上的方法。第一气体可以被输送到细长的第一输送管道，该第一输送管道包括沿管道的长度间隔开的多个出口。第一气流可以由出口引导，沿着横向于工件间隔开的方向的第一向量流入相邻工件之间的至少一个工艺空间。第二气体可以被输送到细长的第二输送管道，该第二输送管道也具有沿其长度间隔开的出口。第二气体的第二气流可以由出口引导，沿着横向于第一方向的第二向量流入处理空间。

92. 发明授权

US07323230B2 Coating for aluminum component 有权
标题翻译：铝组件涂层
公开(公告)号：US07323230B2
公开(公告)日：2008-01-29
申请号：US10910096
申请日：2004-08-02
申请人： Trung T. Doan , Kenny King-Tai Ngan
发明人： Trung T. Doan , Kenny King-Tai Ngan
IPC分类号： H05H1/24 , H05H1/30 , C23C14/00
CPC分类号： C23C16/20 , C23C16/0227 , C23C16/0272 , C23C16/56
摘要： A coated aluminum component for a substrate processing chamber comprises an aluminum component having a surface; a first aluminum oxide layer formed on the surface of the aluminum component, the aluminum oxide layer having a surface comprising penetrating surface features; and a second aluminum oxide layer on the first aluminum oxide layer, the second aluminum oxide layer substantially completely filling the penetrating surface features of the first aluminum oxide layer. A method of forming the coated aluminum component is also described.
摘要翻译：用于基板处理室的涂覆铝部件包括具有表面的铝部件; 形成在铝部件的表面上的第一氧化铝层，所述氧化铝层具有包括穿透表面特征的表面; 和在第一氧化铝层上的第二氧化铝层，第二氧化铝层基本上完全填充第一氧化铝层的穿透表面特征。还描述了形成涂覆的铝组分的方法。

93. 发明授权

US07279398B2 Microfeature workpiece processing apparatus and methods for controlling deposition of materials on microfeature workpieces 有权
标题翻译：微型工件加工设备及控制材料沉积在微型工件上的方法
公开(公告)号：US07279398B2
公开(公告)日：2007-10-09
申请号：US11327794
申请日：2006-01-06
申请人： Cem Basceri , Trung T. Doan , Ronald A. Weimer , Kevin L. Beaman , Lyle D. Breiner , Lingyi A. Zheng , Er-Xuan Ping , Demetrius Sarigiannis , David J. Kubista
发明人： Cem Basceri , Trung T. Doan , Ronald A. Weimer , Kevin L. Beaman , Lyle D. Breiner , Lingyi A. Zheng , Er-Xuan Ping , Demetrius Sarigiannis , David J. Kubista
IPC分类号： H01L21/20 , H01L21/36 , H01L21/302 , H01L21/461 , H01L21/469
CPC分类号： C23C16/45527 , C23C16/34 , C23C16/45546
摘要： The present disclosure provides methods and apparatus useful in depositing materials on batches of microfeature workpieces. One implementation provides a method in which a quantity of a first precursor gas is introduced to an enclosure at a first enclosure pressure. The pressure within the enclosure is reduced to a second enclosure pressure while introducing a purge gas at a first flow rate. The second enclosure pressure may approach or be equal to a steady-state base pressure of the processing system at the first flow rate. After reducing the pressure, the purge gas flow may be increased to a second flow rate and the enclosure pressure may be increased to a third enclosure pressure. Thereafter, a flow of a second precursor gas may be introduced with a pressure within the enclosure at a fourth enclosure pressure; the third enclosure pressure is desirably within about 10 percent of the fourth enclosure pressure.
摘要翻译：本公开提供了用于在批次的微特征工件上沉积材料中有用的方法和装置。一个实施方案提供了一种方法，其中一定量的第一前体气体以第一封壳压力被引入外壳。当以第一流速引入吹扫气体时，外壳内的压力降低到第二封闭压力。第二外壳压力可接近或等于处理系统在第一流量下的稳态基础压力。在降低压力之后，吹扫气体流量可以增加到第二流量，并且外壳压力可以增加到第三外壳压力。此后，第二前体气体的流动可以在第四封闭压力下以外壳内的压力引入; 第三外壳压力理想地在第四外壳压力的约10％内。

94. 发明授权

US07160785B1 Container capacitor structure and method of formation thereof 失效
标题翻译：集装箱电容器结构及其形成方法
公开(公告)号：US07160785B1
公开(公告)日：2007-01-09
申请号：US09652999
申请日：2000-08-31
申请人： D. Mark Durcan , Trung T. Doan , Roger R. Lee , Fernando Gonzalez
发明人： D. Mark Durcan , Trung T. Doan , Roger R. Lee , Fernando Gonzalez
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L27/10811 , H01L27/10817 , H01L27/10852 , H01L27/10888 , H01L28/65 , Y10S257/905
摘要： Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.
摘要翻译：公开了一种容器电容器结构及其构造方法。蚀刻掩模和蚀刻用于暴露容器电容器结构的电极（“底部电极”）的外部表面的部分。蚀刻在容器电容器结构的近端对之间提供凹槽，该凹槽可用于形成额外的电容。因此，电容器电介质和顶电极分别形成在第一电极的外表面的内表面和部分上并相邻。有利地，仅使用内表面增加了第一电极和第二电极两者共同的表面积，这提供了额外的电容，而不会减小用于清除电容器电介质部分和第二电极远离接触孔位置的间隔。此外，与在接触通孔的底部位置处的清除相反，电容器电介质和第二电极部分的这种清除可以在衬底组件的上部位置进行。

95. 发明授权

US06956210B2 Methods for preparing samples for atom probe analysis 失效
标题翻译：原子探针分析样品的制备方法
公开(公告)号：US06956210B2
公开(公告)日：2005-10-18
申请号：US10687111
申请日：2003-10-15
申请人： Trung T. Doan
发明人： Trung T. Doan
IPC分类号： B23K26/36 , G01N1/04 , G01N1/32 , G01Q30/04 , G01Q60/00 , H01J49/16 , G01N1/28
CPC分类号： H01J49/164 , B23K26/364 , G01N1/32 , G01N2001/045
摘要： The present disclosure provides methods for preparing samples for atom probe analysis and methods for analyzing such samples. In one exemplary implementation, a surface of the sample may be positioned with respect to a laser source and laser energy may be directed from the laser source toward the sample surface, removing material from the sample to define an annulus about a sample column. The sample column may be provided with a reduced-diameter apex at its outward end, e.g., by etching. This apex may be juxtaposed with an electrode of an atom probe and material may be selectively removed from the apex for analysis by controlling energy delivered to the apex, e.g., by the electrode.
摘要翻译：本公开提供了用于制备原子探针分析的样品的方法和用于分析这些样品的方法。在一个示例性实施方案中，样品的表面可以相对于激光源定位，并且激光能量可以从激光源朝向样品表面引导，从样品中去除材料以限定围绕样品柱的环带。样品柱可以在其外端例如通过蚀刻设置有直径较小的顶点。该顶点可以与原子探针的电极并置，并且可以通过例如通过电极控制递送到顶点的能量来选择性地从顶点移除材料用于分析。

96. 发明授权

US06881974B2 Probe card for testing microelectronic components 有权
标题翻译：用于测试微电子元件的探针卡
公开(公告)号：US06881974B2
公开(公告)日：2005-04-19
申请号：US10730548
申请日：2003-12-08
申请人： Alan G. Wood , Trung T. Doan , David R. Hembree
发明人： Alan G. Wood , Trung T. Doan , David R. Hembree
IPC分类号： G01R3/00 , G01R31/28 , H05K3/00 , H05K3/40 , H05K3/42 , H01L23/58 , G01R31/02
CPC分类号： G01R3/00 , G01R31/2886 , H01L2224/05001 , H01L2224/05009 , H01L2224/0557 , H01L2224/13 , H05K3/002 , H05K3/4007 , H05K3/423 , H05K2201/0367 , H05K2201/09563 , H05K2203/025 , Y10T29/49004 , Y10T29/49153 , Y10T29/49165 , H01L2224/05624 , H01L2924/00014 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05155 , H01L2224/05171
摘要： Various aspects of the invention provide methods of manufacturing probe cards and test systems which may test microelectronic components using such probe cards. In one specific example, a probe card may be manufactured by forming a plurality of blind holes in a substrate, with each hole having a closed bottom spaced from a back of the substrate by a back thickness. An electrically conductive metal may be deposited on the substrate to fill the holes and define an overburden on the substrate. The metal in each hole may define a conductor. At least a portion of the overburden may be removed to electrically isolate each of the conductors from one another. A portion of the substrate including the back thickness is removed to define an array of pins extending outwardly from a remaining thickness of the substrate, with each pin being an exposed length of one of the conductors.
摘要翻译：本发明的各个方面提供了制造探针卡和测试系统的方法，该测试系统可以使用这种探针卡测试微电子部件。在一个具体示例中，可以通过在基板中形成多个盲孔来制造探针卡，每个孔具有与基板的背面间隔开的背部厚度的封闭底部。可以在衬底上沉积导电金属以填充孔并且在衬底上限定覆盖层。每个孔中的金属可以限定导体。可以去除覆盖层的至少一部分以将每个导体彼此电隔离。去除包括背部厚度的基板的一部分以限定从基板的剩余厚度向外延伸的销的阵列，其中每个销是导体之一的暴露长度。

97. 发明授权

US06825107B2 Method for fabricating a memory chip 失效
标题翻译：存储芯片的制造方法
公开(公告)号：US06825107B2
公开(公告)日：2004-11-30
申请号：US09963842
申请日：2001-09-25
申请人： Trung T. Doan , D. Mark Durcan , Brent D. Gilgen
发明人： Trung T. Doan , D. Mark Durcan , Brent D. Gilgen
IPC分类号： H01L2144
CPC分类号： H01L45/06 , G11C2213/52 , H01L27/2463 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.
摘要翻译：具有硫族化物存储器的电极之间的接触面积减小的超声相变半导体存储器件及其形成方法。这样的存储器件通过形成从下电极元件的下表面突出的尖端而形成。在下电极上施加绝缘材料，使得尖端的上表面露出。硫族化物材料和上电极都形成在尖端顶部，或者尖端被蚀刻到绝缘材料中，并且硫族化物材料和上电极沉积在凹部内。这允许使存储器单元变得更小并且允许最小化存储器单元的总体功率需求。

98. 发明授权

US06773938B2 Probe card, e.g., for testing microelectronic components, and methods for making same 失效
标题翻译：探针卡，例如用于测试微电子部件，以及制造它们的方法
公开(公告)号：US06773938B2
公开(公告)日：2004-08-10
申请号：US10230653
申请日：2002-08-29
申请人： Alan G. Wood , Trung T. Doan , David R. Hembree
发明人： Alan G. Wood , Trung T. Doan , David R. Hembree
IPC分类号： H01L2166
CPC分类号： G01R3/00 , G01R31/2886 , H01L2224/05001 , H01L2224/05009 , H01L2224/0557 , H01L2224/13 , H05K3/002 , H05K3/4007 , H05K3/423 , H05K2201/0367 , H05K2201/09563 , H05K2203/025 , Y10T29/49004 , Y10T29/49153 , Y10T29/49165 , H01L2224/05624 , H01L2924/00014 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05155 , H01L2224/05171
摘要： Various aspects of the invention provide methods of manufacturing probe cards and test systems which may test microelectronic components using such probe cards. In one specific example, a probe card may be manufactured by forming a plurality of blind holes in a substrate, with each hole having a closed bottom spaced from a back of the substrate by a back thickness. An electrically conductive metal may be deposited on the substrate to fill the holes and define an overburden on the substrate. The metal in each hole may define a conductor. At least a portion of the overburden may be removed to electrically isolate each of the conductors from one another. A portion of the substrate including the back thickness is removed to define an array of pins extending outwardly from a remaining thickness of the substrate, with each pin being an exposed length of one of the conductors.
摘要翻译：本发明的各个方面提供了制造探针卡和测试系统的方法，该测试系统可以使用这种探针卡测试微电子部件。在一个具体示例中，可以通过在基板中形成多个盲孔来制造探针卡，每个孔具有与基板的背面间隔开的背部厚度的封闭底部。可以在衬底上沉积导电金属以填充孔并且在衬底上限定覆盖层。每个孔中的金属可以限定导体。可以去除覆盖层的至少一部分以将每个导体彼此电隔离。去除包括背部厚度的基板的一部分以限定从基板的剩余厚度向外延伸的销的阵列，其中每个销是导体之一的暴露长度。

99. 发明授权

US06765250B2 Self-aligned, trenchless mangetoresitive random-access memory (MRAM) structure with sidewall containment of MRAM structure 有权
标题翻译：自对准，无沟槽随机存取存储器（MRAM）结构，侧壁容纳MRAM结构
公开(公告)号：US06765250B2
公开(公告)日：2004-07-20
申请号：US10409145
申请日：2003-04-09
申请人： Trung T. Doan , Roger Lee , Dennis Keller , Gurtej Sandhu , Ren Earl
发明人： Trung T. Doan , Roger Lee , Dennis Keller , Gurtej Sandhu , Ren Earl
IPC分类号： H01L31119
CPC分类号： H01L43/12 , B82Y10/00 , H01L27/222
摘要： This invention pertains to a method of fabricating a trenchless MRAM structure and to the resultant MRAM structure. The MRAM structure of the invention has a pinned layer formed within protective sidewalls formed over a substrate. The protective sidewalls facilitate formation of the MRAM structure by a self-aligning process.
摘要翻译：本发明涉及一种制造无沟槽MRAM结构的方法以及由此产生的MRAM结构。本发明的MRAM结构具有形成在衬底上形成的保护侧壁内的钉扎层。保护侧壁有利于通过自对准工艺形成MRAM结构。

100. 发明授权

US06743724B2 Planarization process for semiconductor substrates 失效
标题翻译：半导体衬底的平面化工艺
公开(公告)号：US06743724B2
公开(公告)日：2004-06-01
申请号：US09832560
申请日：2001-04-11
申请人： Trung T. Doan , Guy T. Blalock , Mark Durcan , Scott G. Meikle
发明人： Trung T. Doan , Guy T. Blalock , Mark Durcan , Scott G. Meikle
IPC分类号： H01L21302
CPC分类号： H01L21/31053
摘要： A method of manufacturing semiconductor devices using an improved chemical mechanical planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved chemical mechanical planarization process includes the formation of a flat planar surface from a deformable coating on the surface of the wafer filling in between the surface irregularities prior to the planarization of the surface through a chemical mechanical planarization process.
摘要翻译：使用改进的化学机械平面化工艺制造半导体器件的方法，用于对其上形成半导体器件的晶片的表面进行平坦化。改进的化学机械平面化处理包括从晶片表面上的可变形涂层形成平坦的平坦表面，其填充在通过化学机械平面化工艺在表面平坦化之前的表面凹凸之间。

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