专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US07010642B2 System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices 失效
标题翻译：具有控制器装置和存储模块的系统包括集成电路缓冲装置和多个集成电路存储装置
公开(公告)号：US07010642B2
公开(公告)日：2006-03-07
申请号：US10952667
申请日：2004-09-28
申请人： Richard E. Perego , Stefanos Sidiropoulos , Ely Tsern
发明人： Richard E. Perego , Stefanos Sidiropoulos , Ely Tsern
IPC分类号： G06F12/00
CPC分类号： G11C29/028 , G06F13/1673 , G06F13/1684 , G11C5/04 , G11C7/10 , G11C29/02 , G11C29/50012
摘要： A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point links and corresponding memory subsystems. The master communicates to the plurality of memory devices in each memory subsystem through the respective buffer device via each point-to-point link
摘要翻译：存储器系统架构/互连拓扑，其包括主机和至少一个存储器子系统之间的至少一个点对点链路。存储器子系统包括耦合到多个存储器件的缓冲器件。可以通过专用点对点链路和对应的存储器子系统升级存储器系统。主设备经由每个点到点链路通过相应的缓冲设备与每个存储器子系统中的多个存储器件进行通信

92. 发明申请

US20140047306A1 CONFIGURABLE, ERROR-TOLERANT MEMORY CONTROL 有权
标题翻译：可配置，容错的内存控制
公开(公告)号：US20140047306A1
公开(公告)日：2014-02-13
申请号：US14112935
申请日：2012-03-10
申请人： Richard E. Perego
发明人： Richard E. Perego
IPC分类号： G06F11/16
CPC分类号： H03M13/356 , G06F11/10 , G06F11/1666
摘要： Configurable, error-tolerant communication of memory control information between components of a memory system. A controller component and memory component each have a variable-width command/address (CA) interface that operates in conjunction with an error detection/correction (EDC) channel to enable a variable level of error detection and correction with respect to command/address information conveyed between the two components as the widths of the CA interfaces are adjusted.
摘要翻译：存储器系统的组件之间的可配置的，容错的通信存储器控制信息。控制器组件和存储器组件各自具有与错误检测/校正（EDC）通道一起操作的可变宽度命令/地址（CA）接口，以实现关于命令/地址信息的可变级别的错误检测和校正由于CA接口的宽度被调整，在两个部件之间传送。

93. 发明授权

US07200710B2 Buffer device and method of operation in a buffer device 失效
标题翻译：缓冲装置和缓冲装置中的操作方法
公开(公告)号：US07200710B2
公开(公告)日：2007-04-03
申请号：US11130734
申请日：2005-05-17
申请人： Richard E. Perego , Stefanos Sidiropoulos , Ely Tsern
发明人： Richard E. Perego , Stefanos Sidiropoulos , Ely Tsern
IPC分类号： G06F12/00
CPC分类号： G11C29/028 , G06F13/1673 , G06F13/1684 , G11C5/04 , G11C7/10 , G11C29/02 , G11C29/50012
摘要： An integrated circuit buffer device comprising a receiver circuit to receive control information and address information. A first interface portion provides at least a first control signal that specifies a write operation to a first memory device. The first control signal corresponds to the control information. A second interface portion provides a first address to the first memory device. The first address corresponds to the address information. The first address specifies a memory location for the write operation to the first memory device. A third interface portion provides a first signal to the first memory device. The first signal synchronizes communication of the first control signal from the integrated circuit buffer device to the first memory device. A fourth interface portion provides at least a second control signal that specifies a write operation to a second memory device. The second control signal corresponds to the control information. A fifth interface portion provides a second address to the second memory device. The second address corresponds to the address information. The second address specifies a memory location for the write operation to the second memory device. A sixth interface portion provides a second signal to the second memory device. The second signal synchronizes communication of the second control signal from the integrated circuit buffer device to the second memory device.
摘要翻译：一种集成电路缓冲器件，包括用于接收控制信息和地址信息的接收器电路。第一接口部分至少提供指定对第一存储器件的写入操作的第一控制信号。第一控制信号对应于控制信息。第二接口部分向第一存储器件提供第一地址。第一个地址对应于地址信息。第一个地址指定用于对第一个存储设备的写入操作的存储器位置。第三接口部分向第一存储器件提供第一信号。第一信号使来自集成电路缓冲器的第一控制信号与第一存储器件的通信同步。第四接口部分至少提供指定对第二存储器件的写入操作的第二控制信号。第二控制信号对应于控制信息。第五接口部分向第二存储器件提供第二地址。第二个地址对应于地址信息。第二地址指定用于对第二存储设备的写操作的存储器位置。第六接口部分向第二存储器件提供第二信号。第二信号使来自集成电路缓冲器的第二控制信号与第二存储器件的通信同步。

94. 发明授权

US06864896B2 Scalable unified memory architecture 有权
标题翻译：可扩展的统一内存架构
公开(公告)号：US06864896B2
公开(公告)日：2005-03-08
申请号：US09858836
申请日：2001-05-15
申请人： Richard E. Perego
发明人： Richard E. Perego
IPC分类号： G06T1/60 , G09G5/36 , G09G5/393 , G06F15/167
CPC分类号： G09G5/363 , G06T1/60 , G09G5/393 , G09G2352/00 , G09G2360/125
摘要： A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides instructions to the computing engine. An interconnect on each module allows multiple modules to be coupled to the memory controller.
摘要翻译：存储器架构包括耦合到多个模块的存储器控制器。每个模块包括耦合到共享存储器的计算引擎。每个计算引擎能够从存储器控制器接收指令并处理接收到的指令。共享内存配置为存储主内存数据和图形数据。某些计算引擎能够处理图形数据。存储器控制器可以包括向计算引擎提供指令的图形控制器。每个模块上的互连允许多个模块耦合到存储器控制器。

95. 发明授权

US06359625B1 Video refresh compression 有权
标题翻译：视频刷新压缩
公开(公告)号：US06359625B1
公开(公告)日：2002-03-19
申请号：US09130509
申请日：1998-08-06
申请人： Richard E. Perego
发明人： Richard E. Perego
IPC分类号： G09G500
CPC分类号： G09G5/393 , G09G5/399 , G09G2340/02 , G09G2360/12 , G09G2360/125
摘要： A data compression apparatus and method of displaying graphics in a computer system employs a full frame buffer and compressed frame buffer wherein pixel data is sent to a display device and concurrently compressed and captured in parallel so that subsequent unchanged frames are regenerated directly from the compressed frame buffer.
摘要翻译：在计算机系统中显示图形的数据压缩装置和方法采用全帧缓冲器和压缩帧缓冲器，其中像素数据被发送到显示装置并且并行压缩和捕获，使得后续不变的帧直接从压缩帧重新生成缓冲。

96. 发明授权

US08352772B2 Reference clock and command word alignment 有权
标题翻译：参考时钟和命令字对齐
公开(公告)号：US08352772B2
公开(公告)日：2013-01-08
申请号：US12598068
申请日：2008-05-08
申请人： Jade M. Kizer , Richard E. Perego
发明人： Jade M. Kizer , Richard E. Perego
IPC分类号： G06F1/04 , G06F1/14 , G06F11/00
CPC分类号： G11C7/22 , G11C7/222 , H03L7/0891 , H03L7/18
摘要： A memory system includes a memory controller that issues command signals and a reference-clock signal to a memory device. The edge rate of the reference-clock signal is lower than the bit rate of the command signals, so the memory device multiplies the reference clock signal to develop a command-recovery clock signal with which to sample the incoming command signals. The memory controller issues the command signals as a series of multi-bit command words aligned with edges of the reference-clock signal so that the memory device can use edges of the reference clock signal for command-word alignment.
摘要翻译：存储器系统包括向存储器件发出命令信号和参考时钟信号的存储器控制器。参考时钟信号的边沿速率低于命令信号的比特率，因此存储器件将参考时钟信号相乘以产生用于对输入的命令信号进行采样的命令恢复时钟信号。存储器控制器将命令信号发出为与参考时钟信号的边缘对准的一系列多位命令字，使得存储器件可以使用参考时钟信号的边沿进行命令字对准。

97. 发明申请

US20120182304A1 Scalable Unified Memory Architecture 审中-公开
标题翻译：可扩展的统一内存架构
公开(公告)号：US20120182304A1
公开(公告)日：2012-07-19
申请号：US13430405
申请日：2012-03-26
申请人： Richard E. Perego
发明人： Richard E. Perego
IPC分类号： G06F15/167
CPC分类号： G09G5/363 , G06T1/60 , G09G5/393 , G09G2352/00 , G09G2360/125
摘要： A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides instructions to the computing engine. An interconnect on each module allows multiple modules to be coupled to the memory controller.
摘要翻译：存储器架构包括耦合到多个模块的存储器控制器。每个模块包括耦合到共享存储器的计算引擎。每个计算引擎能够从存储器控制器接收指令并处理接收到的指令。共享内存配置为存储主内存数据和图形数据。某些计算引擎能够处理图形数据。存储器控制器可以包括向计算引擎提供指令的图形控制器。每个模块上的互连允许多个模块耦合到存储器控制器。

98. 发明授权

US07821519B2 Scalable unified memory architecture 有权
标题翻译：可扩展的统一内存架构
公开(公告)号：US07821519B2
公开(公告)日：2010-10-26
申请号：US11058051
申请日：2005-02-15
申请人： Richard E. Perego
发明人： Richard E. Perego
IPC分类号： G06F15/167 , G06F13/14 , G06F15/80
CPC分类号： G09G5/363 , G06T1/60 , G09G5/393 , G09G2352/00 , G09G2360/125
摘要： A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides instructions to the computing engine. An interconnect on each module allows multiple modules to be coupled to the memory controller.
摘要翻译：存储器架构包括耦合到多个模块的存储器控制器。每个模块包括耦合到共享存储器的计算引擎。每个计算引擎能够从存储器控制器接收指令并处理接收到的指令。共享内存配置为存储主内存数据和图形数据。某些计算引擎能够处理图形数据。存储器控制器可以包括向计算引擎提供指令的图形控制器。每个模块上的互连允许多个模块耦合到存储器控制器。

99. 发明授权

US07320047B2 System having a controller device, a buffer device and a plurality of memory devices 失效
标题翻译：具有控制器装置，缓冲装置和多个存储装置的系统
公开(公告)号：US07320047B2
公开(公告)日：2008-01-15
申请号：US11136995
申请日：2005-05-25
申请人： Richard E. Perego , Stefanos Sidiropoulos , Ely Tsern
发明人： Richard E. Perego , Stefanos Sidiropoulos , Ely Tsern
IPC分类号： G06F12/00
CPC分类号： G11C29/028 , G06F13/1673 , G06F13/1684 , G11C5/04 , G11C7/10 , G11C29/02 , G11C29/50012
摘要： A system comprises a controller device, an integrated circuit buffer device and a first and second memory device. A first plurality of signal lines is coupled to the controller device. A second plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The second plurality of signal lines carries first address information from the integrated circuit buffer device to the first memory device. A third plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The third plurality of signal lines carries first control information from the integrated circuit buffer device to the first memory device. A first signal line is coupled to the first memory device and the integrated circuit buffer device. The first signal line carries a first signal from the integrated circuit buffer device to the first memory device. The first signal synchronizes communication of the first control information from the integrated circuit buffer device to the first memory device.
摘要翻译：一种系统包括控制器装置，集成电路缓冲装置以及第一和第二存储装置。第一多个信号线耦合到控制器设备。第二多个信号线耦合到第一存储器件和集成电路缓冲器件。第二多个信号线将第一地址信息从集成电路缓冲器装置传送到第一存储器件。第三组信号线耦合到第一存储器件和集成电路缓冲器件。第三多个信号线将第一控制信息从集成电路缓冲器装置传送到第一存储器件。第一信号线耦合到第一存储器件和集成电路缓冲器件。第一信号线将来自集成电路缓冲器件的第一信号传送到第一存储器件。第一信号使来自集成电路缓冲器的第一控制信息与第一存储器件的通信同步。

100. 发明授权

US07313639B2 Memory system and device with serialized data transfer 有权
标题翻译：具有序列化数据传输的存储器系统和设备
公开(公告)号：US07313639B2
公开(公告)日：2007-12-25
申请号：US10385908
申请日：2003-03-11
申请人： Richard E. Perego , Fredrick A. Ware
发明人： Richard E. Perego , Fredrick A. Ware
IPC分类号： G06F13/00
CPC分类号： G06F13/1684
摘要： A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each of the memory devices receives at least one of the serial streams of bits from the memory controller and converts the serial stream of bits to a set of parallel bits for storage.
摘要翻译：具有序列化数据传输的存储系统。存储器系统包括在存储器控制器和多个存储器件内。存储器控制器从主机接收多个写入数据值，并将写入数据值作为相应串行比特流输出。每个存储器件从存储器控制器接收至少一个串行比特流，并将串行比特流转换为一组并行比特以进行存储。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式