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91. 发明授权

US07361024B2 Land grid array (LGA) interposer utilizing metal-on-elastomer hemi-torus and other multiple points of contact geometries 有权
公开(公告)号：US07361024B2
公开(公告)日：2008-04-22
申请号：US11865217
申请日：2007-10-01
申请人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
发明人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
IPC分类号： H01R12/00
CPC分类号： H01R12/714 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H05K3/326 , H05K3/4007 , H05K7/1061 , H05K2201/0133 , H05K2201/0367 , H05K2201/09481 , H05K2201/09745 , H05K2201/10378 , H05K2201/10734 , Y10T29/49002 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49151 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T29/49204 , Y10T29/49208 , Y10T29/49213 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure.

92. 发明授权

US07354277B2 Land grid array (LGA) interposer utilizing metal-on-elastomer hemi-torus and other multiple points of contact geometries 有权
公开(公告)号：US07354277B2
公开(公告)日：2008-04-08
申请号：US11865293
申请日：2007-10-01
申请人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
发明人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
IPC分类号： H01R12/00
CPC分类号： H01R12/714 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H05K3/326 , H05K3/4007 , H05K7/1061 , H05K2201/0133 , H05K2201/0367 , H05K2201/09481 , H05K2201/09745 , H05K2201/10378 , H05K2201/10734 , Y10T29/49002 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49151 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T29/49204 , Y10T29/49208 , Y10T29/49213 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure.

93. 发明授权

US07250576B2 Chip package having chip extension and method 失效
标题翻译：芯片封装具有芯片扩展和方法
公开(公告)号：US07250576B2
公开(公告)日：2007-07-31
申请号：US10908615
申请日：2005-05-19
申请人： Evan G. Colgan , David L. Edwards , Benjamin V. Fasano , Kamal K. Sikka , Jeffrey A. Zitz , Wei Zou
发明人： Evan G. Colgan , David L. Edwards , Benjamin V. Fasano , Kamal K. Sikka , Jeffrey A. Zitz , Wei Zou
IPC分类号： H05K1/16
CPC分类号： H01L23/04 , H01L23/3675 , H01L23/433 , H01L24/31 , H01L2224/16225 , H01L2224/27013 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/83051 , H01L2224/83102 , H01L2224/92125 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01074 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195 , H01L2924/00 , H01L2924/00012 , H01L2224/0401
摘要： A chip package including a chip extension for containing thermal interface material (TIM) and improves chip cooling, and a related method, are disclosed. In particular, the chip package includes a chip, a cooling structure coupled to the chip via a TIM, and a chip extension may be thermally coupled to an outer edge of the chip. A TIM placed between the chip and the cooling structure is contained during thermal cycling by the chip extension such that void formation at the edge of the chip, which can move between the chip and cooling structure, is suppressed. The chip extension also improves lateral heat dissipation by providing a greater thermal contact area between the cooling structure and the chip and, if needed, the substrate at a much lower cost than using larger die with lower production unit output from a wafer.
摘要翻译：公开了一种包括用于包含热界面材料（TIM）并提高芯片冷却的芯片延伸的芯片封装以及相关方法。特别地，芯片封装包括芯片，经由TIM耦合到芯片的冷却结构，并且芯片延伸部可热耦合到芯片的外边缘。放置在芯片和冷却结构之间的TIM被芯片延伸部的热循环期间包含，从而可以抑制可在芯片和冷却结构之间移动的芯片边缘处的空隙形成。芯片延伸还通过在冷却结构和芯片之间提供更大的热接触面积，并且如果需要，以比使用具有较低的晶片生产单位输出的较大模具的成本低得多的成本来改善侧向散热。

94. 发明授权

US06955481B2 Method and apparatus for providing parallel optoelectronic communication with an electronic device 有权
标题翻译：用于提供与电子设备的平行光电通信的方法和设备
公开(公告)号：US06955481B2
公开(公告)日：2005-10-18
申请号：US10667234
申请日：2003-09-17
申请人： Evan G. Colgan , Bruce K. Furman , Daniel J. Stigliani, Jr.
发明人： Evan G. Colgan , Bruce K. Furman , Daniel J. Stigliani, Jr.
IPC分类号： G02B6/42 , G02B6/36
CPC分类号： G02B6/4214 , G02B6/4246 , G02B6/4249
摘要： An optoelectronic assembly for an electronic system includes a support electronic chip set configured for at least one of providing multiplexing, demultiplexing, coding, decoding and optoelectronic transducer driving and receive functions. A first substrate having a first surface and an opposite second surface is in communication with the support electronic chip set via the first surface while a second substrate is in communication with the second surface of the first substrate. The second substrate is configured for mounting at least one of data processing, data switching and data storage chips. An optoelectronic transducer is in signal communication with the support electronic chip set and an optical fiber array is aligned at a first end with the optoelectronic transducer and with an optical signaling medium at a second end. An electrical signal from the support electronic chip set is communicated to the optoelectronic transducer via an electrical signaling medium, and the support electronic chip set and the optoelectronic transducer share a common thermal path for cooling.
摘要翻译：一种用于电子系统的光电组件，包括配置用于提供多路复用，解复用，编码，解码和光电换能器驱动和接收功能中的至少一个的支持电子芯片组。具有第一表面和相对的第二表面的第一基板经由第一表面与支撑电子芯片组连通，而第二基板与第一基板的第二表面连通。第二基板被配置用于安装数据处理，数据交换和数据存储芯片中的至少一个。光电子传感器与支撑电子芯片组进行信号通信，光纤阵列在第一端与光电转换器对准，并在第二端与光信号介质对准。来自支持电子芯片组的电信号通过电信号介质传送到光电转换器，并且支持电子芯片组和光电转换器共享用于冷却的公共热路径。

95. 发明授权

US06256080B1 Self-aligned structures for improved wide viewing angle for liquid crystal displays 有权
标题翻译：自对准结构，用于改善液晶显示器的广视角
公开(公告)号：US06256080B1
公开(公告)日：2001-07-03
申请号：US09339262
申请日：1999-06-23
申请人： Evan G. Colgan , Shui-Chih A. Lien , Kai R. Schleupen
发明人： Evan G. Colgan , Shui-Chih A. Lien , Kai R. Schleupen
IPC分类号： G02F11337
CPC分类号： G02F1/133753 , G02F1/133512 , G02F1/133707
摘要： In accordance with the present invention, a liquid crystal display cell includes a first substrate having a light absorbent material patterned thereon. The light absorbent material includes a portion disposed within a pixel area. A conductive layer is formed on the light absorbent material for forming a first transparent electrode. A second electrode is spaced apart from the first electrode by a gap. The gap includes liquid crystal. A ridge or a trench is formed in the pixel area and projects into the liquid crystal. The ridge or trench is self-aligned to the portions of the light absorbent material in the pixel area. The first electrode and the second electrode provide an electric field therebetween wherein the ridge or trench provides pretilt control for the liquid crystal to provide an improved wide viewing angle and the portions of the light absorbent material absorb light leaked from the ridge. Other embodiments for active and passive displays are included as well as a method for employing the invention.
摘要翻译：根据本发明，液晶显示单元包括具有图案化的吸光材料的第一基板。吸光材料包括设置在像素区域内的部分。在用于形成第一透明电极的光吸收材料上形成导电层。第二电极通过间隙与第一电极间隔开。间隙包括液晶。在像素区域中形成脊或沟槽并突出到液晶中。脊或沟槽与像素区域中的光吸收材料的部分自对准。第一电极和第二电极在其间提供电场，其中脊或沟槽为液晶提供预先控制以提供改进的宽视角，并且光吸收材料的部分吸收从脊部泄漏的光。包括有源和无源显示器的其它实施例以及采用本发明的方法。

96. 发明授权

US5831710A Liquid crystal display 失效
标题翻译：液晶显示器
公开(公告)号：US5831710A
公开(公告)日：1998-11-03
申请号：US795226
申请日：1997-02-06
申请人： Evan G. Colgan , Minhua Lu , Robert Lee Melcher , James Lawrence Sanford , Kei-Hsiung Yang
发明人： Evan G. Colgan , Minhua Lu , Robert Lee Melcher , James Lawrence Sanford , Kei-Hsiung Yang
IPC分类号： G02F1/1339 , G02F1/1341 , G09F9/30
CPC分类号： G02F1/13394
摘要： A structural principle is described for control of the gap and the area around the periphery of a liquid crystal display by the formation of an insulating layer out of which, gap dimension maintaining posts and contaminant diffusion inhibiting segmented walls, remain after the display area is etched back out of the layer.
摘要翻译：描述了一种结构原理，用于通过形成绝缘层来控制液晶显示器周围的间隙和周围区域，其中间隙尺寸维持柱和污染物扩散抑制分割壁在显示区域被蚀刻之后残留退出层。

97. 发明授权

US5310602A Self-aligned process for capping copper lines 失效
标题翻译：自动对线加工铜线
公开(公告)号：US5310602A
公开(公告)日：1994-05-10
申请号：US960627
申请日：1992-10-13
申请人： Jian Li , James W. Mayer , Evan G. Colgan , Jeffrey P. Gambino
发明人： Jian Li , James W. Mayer , Evan G. Colgan , Jeffrey P. Gambino
IPC分类号： H01L21/768 , H01L23/532 , B32B9/00
CPC分类号： H01L21/76858 , H01L21/76838 , H01L21/76852 , H01L21/76856 , H01L21/76867 , H01L21/76886 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , Y10T428/238 , Y10T428/239 , Y10T428/24917
摘要： The present invention features a process and a resulting article in which copper-based multilevel interconnects are fabricated. The copper-based multilevel interconnect formed by the inventive process first includes the process step of depositing a pattern of copper lines upon or in an applicable substrate, such as silicon dioxide. The copper lines are approximately one micron thick. The lines are coated with approximately 50 to 100 nm of titanium by sputter deposition, and undergo subsequent annealing at approximately 300.degree. C. to 400.degree. C. in an argon ambient. The titanium and copper layers are annealed to provide a Cu.sub.3 Ti alloy at the copper/titanium junction. The unreacted titanium between the copper features is then stripped away by dry etching with fluorine-based etch. The remaining Cu.sub.3 Ti alloy is subsequently transformed into TiN(O) and copper by a rapid thermal annealing in an NH.sub.3 atmosphere at an approximate temperature of below 650.degree. C., and then usually at temperatures ranging from between 550.degree. C. to 650.degree. C. for approximately five minutes. The copper lines are thereby capped with a layer of TiN(O), since oxygen is incorporated into the TiN layer during the heat treatment. The TiN(O) layer is more effective as a diffusion barrier than is TiN.
摘要翻译：本发明的特征在于制造铜基多层互连的工艺和所得到的制品。由本发明的方法形成的基于铜的多层互连首先包括将铜线图案沉积在诸如二氧化硅之类的适用基底上或其中的工艺步骤。铜线约为1微米厚。线通过溅射沉积涂覆有约50至100nm的钛，并在氩气氛围中在约300℃至400℃下进行随后的退火。对钛和铜层进行退火以在铜/钛结处提供Cu 3 Ti合金。然后通过用氟基蚀刻的干蚀刻剥离铜特征之间的未反应的钛。剩余的Cu3Ti合金随后在NH3气氛中在大约650℃左右的快速热退火下转化成TiN（O）和铜，然后通常在550℃至650℃的温度范围内约五分钟。因此，铜线由TiN（O）层覆盖，因为在热处理期间氧被并入到TiN层中。作为扩散阻挡层，TiN（O）层比TiN更有效。

98. 发明授权

US5221449A Method of making Alpha-Ta thin films 失效
标题翻译：制造Alpha-Ta薄膜的方法
公开(公告)号：US5221449A
公开(公告)日：1993-06-22
申请号：US910924
申请日：1992-07-09
申请人： Evan G. Colgan , Peter M. Fryer
发明人： Evan G. Colgan , Peter M. Fryer
IPC分类号： C23C14/14 , H01L21/28 , H01L21/285 , H01L21/336 , H01L21/768
CPC分类号： H01L21/76876 , C23C14/14 , H01L21/28079 , H01L21/28568 , H01L21/76841 , H01L29/6675
摘要： The present invention relates generally to a structure and a method of making Alpha-Ta films, and more particularly, to a structure and a method of making Alpha-Ta in thin films. A seed layer of Ta reactively sputtered in a nitrogen containing environment is grown on the substrate, and using this seed layer of Ta(N) layers of Alpha-Ta are then formed.
摘要翻译：本发明一般涉及制造α-Ta膜的结构和方法，更具体地说，涉及在薄膜中制造α-Ta的结构和方法。在含氮环境中反应溅射的Ta晶种层生长在衬底上，然后形成Ta（N）层的α-Ta种子层。

99. 发明授权

US09207002B2 Contaminant separator for a vapor-compression refrigeration apparatus 有权
标题翻译：用于蒸气压缩式制冷装置的污染物分离器
公开(公告)号：US09207002B2
公开(公告)日：2015-12-08
申请号：US13271304
申请日：2011-10-12
申请人： Levi A. Campbell , Richard C. Chu , Evan G. Colgan , Milnes P. David , Michael J. Ellsworth, Jr. , Madhusudan K. Iyengar , Robert E. Simons
发明人： Levi A. Campbell , Richard C. Chu , Evan G. Colgan , Milnes P. David , Michael J. Ellsworth, Jr. , Madhusudan K. Iyengar , Robert E. Simons
IPC分类号： F25D23/12 , F25B21/02 , F25B43/00 , H05K7/20 , B23P15/26
CPC分类号： F25B21/02 , B23P15/26 , F25B43/00 , F25B43/003 , F25B2400/01 , H05K7/20809 , H05K7/20836 , Y10T29/49359
摘要： Apparatuses and methods are provided for facilitating cooling of an electronic component. The apparatus includes a vapor-compression refrigeration system, which includes an expansion component, an evaporator, a compressor and a condenser coupled in fluid communication. The evaporator is coupled to and cools the electronic component. The apparatus further includes a contaminant separator coupled in fluid communication with the refrigerant flow path. The separator includes a refrigerant cold filter and a thermoelectric array. At least a portion of refrigerant passing through the refrigerant flow path passes through the cold filter, and the thermoelectric array provides cooling to the cold filter to cool refrigerant passing through the filter. By cooling refrigerant passing through the filter, contaminants solidify from the refrigerant, and are deposited in the cold filter. The separator may further include a refrigerant hot filter coupled to a hot side of the thermoelectric array for further filtering the refrigerant.
摘要翻译：提供了便于冷却电子部件的装置和方法。该装置包括蒸气压缩式制冷系统，其包括膨胀部件，蒸发器，压缩机和流体连通的冷凝器。蒸发器与电子部件联接并冷却。该装置还包括与制冷剂流动路径流体连通的污染物分离器。分离器包括制冷剂冷滤器和热电阵列。通过制冷剂流路的制冷剂的至少一部分通过冷过滤器，并且热电阵列向冷过滤器提供冷却以冷却通过过滤器的制冷剂。通过冷却通过过滤器的制冷剂，污染物从制冷剂中固化，并沉积在冷过滤器中。分离器还可以包括耦合到热电阵列的热侧的制冷剂热过滤器，用于进一步过滤制冷剂。

100. 发明授权

US08823164B2 Heatsink attachment module 有权
标题翻译：散热器附件模块
公开(公告)号：US08823164B2
公开(公告)日：2014-09-02
申请号：US13284522
申请日：2011-10-28
申请人： Evan G. Colgan , Michael A. Gaynes , Jeffrey A. Zitz
发明人： Evan G. Colgan , Michael A. Gaynes , Jeffrey A. Zitz
IPC分类号： H01L23/34
CPC分类号： H01L21/50 , H01L23/3128 , H01L23/433 , H01L24/16 , H01L24/32 , H01L24/72 , H01L24/73 , H01L24/90 , H01L24/92 , H01L2224/131 , H01L2224/16225 , H01L2224/32225 , H01L2224/73253 , H01L2224/81815 , H01L2224/83104 , H01L2224/83901 , H01L2224/921 , H01L2924/10253 , H01L2924/15787 , H01L2924/00 , H01L2924/00014 , H01L2924/00012 , H01L2224/83 , H01L2224/90 , H01L2924/014
摘要： A chip packaging apparatus includes a substrate, a load frame attached to the substrate by an adhesive material, the load frame being formed to define an aperture and a semiconductor chip mounted on the substrate within the aperture. A thickness of the adhesive material between the load frame and the substrate is varied and adjusted such that a surface of the load frame opposite the substrate is disposed substantially in parallel to a surface of the chip opposite the substrate.
摘要翻译：芯片封装设备包括基板，通过粘合剂材料附接到基板的负载框架，所述负载框架形成为限定孔和安装在孔内的基板上的半导体芯片。负载框架和基板之间的粘合材料的厚度被改变和调节，使得与基板相对的负载框架的表面基本上平行于与基板相对的芯片的表面平行。

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