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91. 发明授权

US07192876B2 Transistor with independent gate structures 有权
标题翻译：具有独立门结构的晶体管
公开(公告)号：US07192876B2
公开(公告)日：2007-03-20
申请号：US10443375
申请日：2003-05-22
申请人： Leo Mathew , Robert F. Steimle , Ramachandran Muralidhar
发明人： Leo Mathew , Robert F. Steimle , Ramachandran Muralidhar
IPC分类号： H01L21/308
CPC分类号： H01L29/785 , G11C16/0458 , G11C16/0475 , H01L27/115 , H01L27/11521 , H01L29/66795 , H01L29/66818 , H01L29/7881 , H01L29/7887 , H01L29/792 , H01L29/7923
摘要： A method of making a transistor with independent gate structures. The gate structures are each adjacent to sidewalls of a semiconductor structure. The method includes depositing at least one conformal layer that includes a layer of gate material over a semiconductor structure that includes the channel region. A planar layer is formed over the wafer. The planar layer has a top surface below the top surface of the rat least one conformal layer at a location over the substrate. The at least one conformal layers are etched to remove the gate material over the semiconductor structure.
摘要翻译：制造具有独立栅极结构的晶体管的方法。栅极结构各自与半导体结构的侧壁相邻。该方法包括在包括沟道区域的半导体结构上沉积包括栅极材料层的至少一个共形层。在晶片上形成平面层。平面层在衬底上方的位置处具有在大致最小一个共形层的顶表面下方的顶表面。蚀刻至少一个共形层以去除半导体结构上的栅极材料。

92. 发明授权

US07160775B2 Method of discharging a semiconductor device 有权
标题翻译：放电半导体器件的方法
公开(公告)号：US07160775B2
公开(公告)日：2007-01-09
申请号：US10912825
申请日：2004-08-06
申请人： Erwin J. Prinz , Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Robert F. Steimle , Craig T. Swift , Bruce E. White
发明人： Erwin J. Prinz , Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Robert F. Steimle , Craig T. Swift , Bruce E. White
IPC分类号： H01L21/336
CPC分类号： B82Y10/00 , G11C16/0475 , G11C16/14 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L29/42332
摘要： In one embodiment, a method for discharging a semiconductor device includes providing a semiconductor substrate, forming a hole blocking dielectric layer over the semiconductor substrate, forming nanoclusters over the hole blocking dielectric layer, forming a charge trapping layer over the nanoclusters, and applying an electric field to the nanoclusters to discharge the semiconductor device. Applying the electric field may occur while applying ultraviolet (UV) light. In one embodiment, the hole blocking dielectric layer comprises forming the hole blocking dielectric layer having a thickness greater than approximately 50 Angstroms.
摘要翻译：在一个实施例中，一种用于放电半导体器件的方法包括提供半导体衬底，在半导体衬底上形成空穴阻挡电介质层，在空穴阻挡介电层上形成纳米团簇，在纳米团簇上形成电荷俘获层，并施加电场到纳米团簇放电半导体器件。施加紫外线（UV）光时可能会发生电场。在一个实施例中，空穴阻挡介电层包括形成厚度大于约50埃的空穴阻挡介电层。

93. 发明授权

US07105395B2 Programming and erasing structure for an NVM cell 有权
标题翻译： NVM单元的编程和擦除结构
公开(公告)号：US07105395B2
公开(公告)日：2006-09-12
申请号：US10930891
申请日：2004-08-31
申请人： James David Burnett , Gowrishankar L. Chindalore , Craig T. Swift , Ramachandran Muralidhar
发明人： James David Burnett , Gowrishankar L. Chindalore , Craig T. Swift , Ramachandran Muralidhar
IPC分类号： H01L29/72
CPC分类号： H01L29/0847 , H01L29/7881 , H01L29/7885
摘要： A non-volatile memory (NVM) has a silicon germanium (SiGe) drain that is progressively more heavily doped toward the surface of the substrate. The substrate is preferably silicon and the drain is formed by first forming a cavity in the substrate in the drain location. SiGe is epitaxially grown in the cavity with an increasing doping level. Thus, the PN junction between the substrate and the drain is lightly doped on both the P and N side. The drain progressively becomes more heavily doped until the maximum desired doping level is reached, and the remaining portion of the SiGe drain is doped at this maximum desired level. As a further enhancement, the perimeter of the SiGe in the substrate is the same conductivity type as that of the substrate and channel. Thus a portion of the channel is in the SiGe.
摘要翻译：非易失性存储器（NVM）具有朝向衬底表面逐渐更加掺杂的硅锗（SiGe）漏极。衬底优选为硅，并且通过首先在漏极位置中的衬底中形成空腔来形成漏极。 SiGe在掺杂水平增加的情况下外延生长。因此，衬底和漏极之间的PN结在P和N侧都被轻掺杂。漏极逐渐变得更加重掺杂，直到达到最大期望的掺杂水平，并且SiGe漏极的剩余部分以该最大期望水平掺杂。作为进一步的增强，衬底中SiGe的周长与衬底和沟道的导电类型相同。因此，通道的一部分在SiGe中。

94. 发明申请

US20060197140A1 Vertical transistor NVM with body contact structure and method 审中-公开
标题翻译：垂直晶体管NVM具有体接触结构和方法
公开(公告)号：US20060197140A1
公开(公告)日：2006-09-07
申请号：US11072878
申请日：2005-03-04
申请人： Ramachandran Muralidhar , Yang Du , Leo Mathew
发明人： Ramachandran Muralidhar , Yang Du , Leo Mathew
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L29/40114 , H01L29/66825 , H01L29/7851 , H01L29/7881
摘要： A semiconductor device (151) is provided which comprises (a) a semiconductor substrate (103); (b) a fin (109) comprising a semiconductor material and being in electrical contact with the substrate; (c) a first floating gate (121) disposed on a first side of said fin; and (d) a control gate (107).
摘要翻译：提供半导体器件（151），其包括（a）半导体衬底（103）; （b）包括半导体材料并与基底电接触的翅片（109）; （c）设置在所述散热片的第一侧上的第一浮动栅极（121）和（d）控制门（107）。

95. 发明申请

US20050124130A1 Semiconductor fabrication process with asymmetrical conductive spacers 有权
标题翻译：具有不对称导电间隔物的半导体制造工艺
公开(公告)号：US20050124130A1
公开(公告)日：2005-06-09
申请号：US11036860
申请日：2005-01-13
申请人： Leo Mathew , Ramachandran Muralidhar
发明人： Leo Mathew , Ramachandran Muralidhar
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L29/78
CPC分类号： H01L29/66659 , H01L21/26586 , H01L21/823468 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7835 , H01L29/7842 , Y10S257/90
摘要： A semiconductor process and resulting transistor includes forming conductive extension spacers (146, 150) on either side of a gate electrode (116). Conductive extensions (146, 150) and gate electrode 116 are independently doped such that each of the structures may be n-type or p-type. Source/drain regions (156) are implanted laterally disposed on either side of the spacers (146, 150). Spacers (146, 150) may be independently doped by using a first angled implant (132) to dope first extension spacer (146) and a second angled implant (140) to dope second spacer (150). In one embodiment, the use of differently doped extension spacers (146, 150) eliminates the need for threshold adjustment channel implants.
摘要翻译：半导体工艺和所得晶体管包括在栅电极（116）的任一侧上形成导电延伸间隔物（146,150）。导电延伸部（146,150）和栅电极116被独立地掺杂，使得每个结构可以是n型或p型。源极/漏极区域（156）被植入在间隔物（146,150）的任一侧上。间隔物（146,150）可以通过使用第一成角度的植入物（132）来掺杂第一延伸间隔物（146）和第二成角度的植入物（140）以掺杂第二间隔物（150）来独立地掺杂。在一个实施例中，使用不同掺杂的延伸间隔物（146,150）消除了对阈值调整通道植入物的需要。

96. 发明授权

US06831310B1 Integrated circuit having multiple memory types and method of formation 失效
标题翻译：具有多种存储器类型和形成方法的集成电路
公开(公告)号：US06831310B1
公开(公告)日：2004-12-14
申请号：US10705504
申请日：2003-11-10
申请人： Leo Mathew , Ramachandran Muralidhar
发明人： Leo Mathew , Ramachandran Muralidhar
IPC分类号： H01L2980
CPC分类号： H01L27/108 , B82Y10/00 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/785 , H01L29/7881
摘要： A transistor (10) is formed having three separately controllable gates (44, 42, 18). The three gate regions may be electrically biased differently and the gate regions may have different conductivity properties. The dielectrics on the channel sidewall may be different than the dielectrics on the top of the channel. Electrical contacts to source, drain and the three gates is selectively made. By including charge storage layers, such as nanoclusters, adjacent the transistor channel and controlling the charge storage layers via the three gate regions, both volatile and non-volatile memory cells are realized using the same process to create a universal memory process. When implemented as a volatile cell, the height of the transistor and the characteristics of channel sidewall dielectrics control the memory retention characteristics. When implemented as a nonvolatile cell, the width of the transistor and the characteristics of the overlying channel dielectrics control the memory retention characteristics.
摘要翻译：晶体管（10）形成有三个可分别控制的栅极（44,42,18）。三个栅极区域可以被不同地电偏置，并且栅极区域可以具有不同的导电性质。通道侧壁上的电介质可以不同于通道顶部的电介质。选择性地制造到源极，漏极和三个栅极的电接触。通过包括与晶体管沟道相邻的电荷存储层，例如纳米团簇，并通过三个栅极区域控制电荷存储层，使用相同的过程实现易失性和非易失性存储单元，从而创建通用存储器处理。当实现为易失性单元时，晶体管的高度和通道侧壁电介质的特性控制存储器保持特性。当被实现为非易失性单元时，晶体管的宽度和上覆通道电介质的特性控制存储器保持特性。

97. 发明授权

US06784103B1 Method of formation of nanocrystals on a semiconductor structure 有权
标题翻译：在半导体结构上形成纳米晶体的方法
公开(公告)号：US06784103B1
公开(公告)日：2004-08-31
申请号：US10442500
申请日：2003-05-21
申请人： Rajesh A. Rao , Tushar P. Merchant , Ramachandran Muralidhar
发明人： Rajesh A. Rao , Tushar P. Merchant , Ramachandran Muralidhar
IPC分类号： H01L2144
CPC分类号： B82Y10/00 , H01L21/02381 , H01L21/02488 , H01L21/02532 , H01L21/02595 , H01L21/0262 , H01L21/28273 , H01L29/42332
摘要： Nanocrystals (22) are formed in a semiconductor, such as for example, in a memory having a floating gate. A dielectric (18) overlies a substrate (12) and is placed in a chemical vapor deposition chamber (34). A first precursor gas, such as disilane (36), is flowed into the chemical vapor deposition chamber during a first phase to nucleate the nanocrystals (22) on the dielectric with first predetermined processing conditions existing within the chemical vapor deposition chamber for a first time period. A second precursor gas, such as silane, is flowed into the chemical vapor deposition chamber during a second phase subsequent to the first phase to grow the nanocrystals under second predetermined processing conditions existing within the chemical vapor deposition chamber for a second time period.
摘要翻译：纳米晶体（22）形成在半导体中，例如在具有浮动栅极的存储器中。电介质（18）覆盖在衬底（12）上并且被放置在化学气相沉积室（34）中。第一前体气体，例如乙硅烷（36）在第一阶段期间流入化学气相沉积室，以使化学气相沉积室内存在的第一预定处理条件第一次使介质上的纳米晶体（22）成核期。第二前体气体，例如硅烷，在第一阶段之后的第二阶段期间流入化学气相沉积室，以在第二时间段内在化学气相沉积室内存在的第二预定处理条件下生长纳米晶体。

98. 发明授权

US06413819B1 Memory device and method for using prefabricated isolated storage elements 有权
标题翻译：使用预制隔离存储元件的存储器件和方法
公开(公告)号：US06413819B1
公开(公告)日：2002-07-02
申请号：US09595821
申请日：2000-06-16
申请人： Sufi Zafar , Ramachandran Muralidhar , Bich-Yen Nguyen , Sucharita Madhukar , Daniel T. Pham , Michael A. Sadd , Chitra K. Subramanian
发明人： Sufi Zafar , Ramachandran Muralidhar , Bich-Yen Nguyen , Sucharita Madhukar , Daniel T. Pham , Michael A. Sadd , Chitra K. Subramanian
IPC分类号： H01L21336
CPC分类号： B82Y10/00 , H01L21/28273 , H01L29/7883 , H01L29/7888
摘要： A semiconductor device that includes a floating gate made up of a plurality of pre-formed isolated storage elements (18) and a method for making such a device is presented. The device is formed by first providing a semiconductor layer (12) upon which a first gate insulator (14) is formed. A plurality of pre-fabricated isolated storage elements (18) is then deposited on the first gate insulator (14). This deposition step may be accomplished by immersion in a colloidal solution (16) that includes a solvent and pre-fabricated isolated storage elements (18). Once deposited, the solvent of the solution (16) can be removed, leaving the pre-fabricated isolated storage elements (18) deposited on the first gate insulator (14). After depositing the pre-fabricated isolated storage elements (18), a second gate insulator (20) is formed over the pre-fabricated isolated storage elements (18). A gate electrode (24) is then formed over the second gate insulator (20), and portions the first and second gate insulators and the plurality of pre-fabricated isolated storage elements that do not underlie the gate electrode are selectively removed. A source region (32) and a drain region (34) are then formed in the semiconductor layer (12) such that a channel region is formed between underlying the gate electrode (24).
摘要翻译：提供了一种半导体器件，其包括由多个预先形成的隔离存储元件（18）构成的浮动栅极和用于制造这种器件的方法。该器件通过首先提供形成第一栅极绝缘体（14）的半导体层（12）形成。然后，多个预制隔离存储元件（18）沉积在第一栅极绝缘体（14）上。该沉积步骤可以通过浸入包括溶剂和预制隔离存储元件（18）的胶体溶液（16）中来实现。一旦沉积，可以除去溶液（16）的溶剂，留下沉积在第一栅极绝缘体（14）上的预制隔离存储元件（18）。在沉积预制隔离存储元件（18）之后，在预制隔离存储元件（18）上形成第二栅极绝缘体（20）。然后，在第二栅极绝缘体（20）之上形成栅电极（24），并且选择性地去除不在栅电极下面的第一和第二栅极绝缘体和多个预制隔离存储元件的部分。然后在半导体层（12）中形成源极区（32）和漏极区（34），使得在栅电极（24）下方形成沟道区。

99. 发明授权

US06330184B1 Method of operating a semiconductor device 有权
标题翻译：操作半导体器件的方法
公开(公告)号：US06330184B1
公开(公告)日：2001-12-11
申请号：US09659105
申请日：2000-09-11
申请人： Bruce E. White , Bo Jiang , Ramachandran Muralidhar
发明人： Bruce E. White , Bo Jiang , Ramachandran Muralidhar
IPC分类号： G11C1604
CPC分类号： G11C16/0475 , G11C11/5621 , G11C11/5628 , G11C11/5671 , G11C16/0458 , G11C16/10 , G11C16/3418 , H01L29/7887
摘要： A method of operating a semiconductor device that includes a first memory cell with discontinuous storage elements or dots (108) in lieu of a conventional floating gate can be programmed to at least one of three different states. The different states are possible because the read current for the memory cell is different when the dots are programmed near the source region or near the drain region. Embodiments may use two different potentials for power supplies or three different potentials. The two-potential embodiment simplifies the design, whereas the three-potential embodiment has a reduced risk of disturb problems in adjacent unselected memory cells (100B, 100C, and 100D).
摘要翻译：一种操作包括具有不连续存储元件的第一存储单元或代替常规浮动栅极的点的半导体器件的方法可被编程为三种不同状态中的至少一种。不同的状态是可能的，因为当点被编程在源极区域附近或靠近漏极区域时，存储器单元的读取电流是不同的。实施例可以使用两种不同的电源或三种不同的电位。双电位实施例简化了设计，而三电位实施例降低了相邻未选择的存储单元（100B，100C和100D）中的干扰问题的风险。

100. 发明授权

US08575588B2 Phase change memory cell with heater and method therefor 有权
标题翻译：具有加热器的相变存储器单元及其方法
公开(公告)号：US08575588B2
公开(公告)日：2013-11-05
申请号：US13238791
申请日：2011-09-21
申请人： Leo Mathew , Dharmesh Jawarani , Tushar P. Merchant , Ramachandran Muralidhar
发明人： Leo Mathew , Dharmesh Jawarani , Tushar P. Merchant , Ramachandran Muralidhar
IPC分类号： H01L45/00
CPC分类号： H01L45/1675 , G11C13/0004 , H01L27/2436 , H01L45/06 , H01L45/1226 , H01L45/126 , H01L45/144
摘要： A method for forming a phase change memory cell (PCM) includes forming a heater for the phase change memory and forming a phase change structrure electrically coupled to the heater. The forming a heater includes siliciding a material including silicon to form a silicide structure, wherein the heater includes at least a portion of the silicide structure. The phase change structure exhibits a first resistive value when in a first phase state and exhibits a second resistive value when in a second phase state. The silicide structure produces heat when current flows through the silicide structure for changing the phase state of the phase change structure.
摘要翻译：形成相变存储单元（PCM）的方法包括形成用于相变存储器的加热器，并形成电耦合到加热器的相变结构。形成加热器包括将包括硅的材料硅化以形成硅化物结构，其中加热器包括至少一部分硅化物结构。当处于第一相位状态时，相变结构呈现第一电阻值，并且当处于第二相位状态时呈现第二电阻值。当电流流过硅化物结构以改变相变结构的相位状态时，硅化物结构产生热量。

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