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91. 发明授权

US07994038B2 Method to reduce MOL damage on NiSi 有权
标题翻译：减少NiSi上MOL损伤的方法
公开(公告)号：US07994038B2
公开(公告)日：2011-08-09
申请号：US12366378
申请日：2009-02-05
申请人： Karthik Ramani , Paul R. Besser
发明人： Karthik Ramani , Paul R. Besser
IPC分类号： H01L21/3205
CPC分类号： H01L21/823807 , H01L21/28052 , H01L21/823814 , H01L21/823835 , H01L29/458 , H01L29/665 , H01L29/6653 , H01L29/7843
摘要： Transistor devices are formed with nickel silicide layers formulated to prevent degradation upon removal of overlying stress liners. Embodiments include transistors with nickel silicide layers having a platinum composition gradient increasing in platinum content toward the upper surfaces thereof, i.e., increasing in platinum in a direction away from the gate electrode and source/drain regions. Embodiments include forming a first layer of nickel having a first amount of platinum and forming, on the first layer of nickel, a second layer of nickel having a second amount of platinum, the second weight percent of platinum being greater than the first weight percent. The layers of nickel are then annealed to form a nickel silicide layer having the platinum composition gradient increasing in platinum toward the upper surface. The platinum concentration gradient protects the nickel silicide layer during subsequent processing, as during etching to remove overlying stress liners, thereby avoiding a decrease in device performance.
摘要翻译：晶体管器件形成有硅化镍层，配制成防止去除上覆应力衬垫时的退化。实施方案包括具有镍化硅层的晶体管，其铂组分梯度朝向其上表面增加铂含量，即铂在远离栅电极和源/漏区的方向上增加。实施例包括形成具有第一量的铂的第一镍层，并在第一层镍上形成具有第二量铂的第二层镍，第二重量百分比的铂大于第一重量百分数。然后将镍层退火以形成铂化合物梯度朝向上表面逐渐增加的铂硅化镍层。铂浓度梯度在后续处理期间保护硅化镍层，如在蚀刻期间去除上覆的应力衬垫，从而避免器件性能的降低。

92. 发明授权

US07910996B2 Semiconductor device and method of manufacturing a semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07910996B2
公开(公告)日：2011-03-22
申请号：US12496133
申请日：2009-07-01
申请人： Paul R. Besser , Scott D. Luning
发明人： Paul R. Besser , Scott D. Luning
IPC分类号： H01L29/12
CPC分类号： H01L29/66628 , H01L29/66772
摘要： A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion of the major surface and on an active region forming a sidewall of the trench.
摘要翻译：公开了一种半导体器件，其具有覆盖具有主表面的半导体层的导电栅极结构。隔离材料凹陷在半导体层的主表面下方的沟槽区域内。形成外延层，覆盖主表面的一部分和形成沟槽侧壁的有源区。

93. 发明申请

US20080182407A1 METHOD OF FORMING VIAS IN A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：在半导体器件中形成VIAS的方法
公开(公告)号：US20080182407A1
公开(公告)日：2008-07-31
申请号：US11669700
申请日：2007-01-31
申请人： Jun Zhai , Christy Woo , Kok-Yong Yiang , Paul R. Besser , Richard C. Blish , Christine Hau-Reige
发明人： Jun Zhai , Christy Woo , Kok-Yong Yiang , Paul R. Besser , Richard C. Blish , Christine Hau-Reige
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76852 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A via is formed in contact with a conductive line, whereby the via is offset from the conductive line so that the via extends beyond the conductive line. In accordance with a specific embodiment, a portion of the via contacts a sidewall of the conductive line.
摘要翻译：通孔形成为与导电线接触，由此通孔偏离导线，使得通孔延伸超过导线。根据具体实施例，通孔的一部分接触导线的侧壁。

94. 发明申请

US20080150011A1 INTEGRATED CIRCUIT SYSTEM WITH MEMORY SYSTEM 审中-公开
标题翻译：具有存储器系统的集成电路系统
公开(公告)号：US20080150011A1
公开(公告)日：2008-06-26
申请号：US11958646
申请日：2007-12-18
申请人： Simon Siu-Sing Chan , Lei Xue , YouSeok Suh , Amol Ramesh Joshi , Hidehiko Shiraiwa , Harpreet Sachar , Kuo-Tung Chang , Connie Pin Chin Wang , Paul R. Besser , Shenqing Fang , Meng Ding , Takashi Orimoto , Wei Zheng , Fred TK Cheung
发明人： Simon Siu-Sing Chan , Lei Xue , YouSeok Suh , Amol Ramesh Joshi , Hidehiko Shiraiwa , Harpreet Sachar , Kuo-Tung Chang , Connie Pin Chin Wang , Paul R. Besser , Shenqing Fang , Meng Ding , Takashi Orimoto , Wei Zheng , Fred TK Cheung
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： A method for forming an integrated circuit system is provided including forming a substrate having a core region and a periphery region, forming a charge storage stack over the substrate in the core region, forming a gate stack with a stack header having a metal portion over the substrate in the periphery region, and forming a memory system with the stack header over the charge storage stack.
摘要翻译：提供一种用于形成集成电路系统的方法，包括形成具有芯区域和周边区域的衬底，在芯区域中的衬底上形成电荷存储堆叠，形成具有堆叠集管的栅极堆叠，堆叠集束具有金属部分衬底，并且在电荷存储堆叠上形成具有堆叠头的存储器系统。

95. 发明授权

US06514858B1 Test structure for providing depth of polish feedback 失效
标题翻译：提供抛光反馈深度的测试结构
公开(公告)号：US06514858B1
公开(公告)日：2003-02-04
申请号：US09829202
申请日：2001-04-09
申请人： Frederick N. Hause , Paul R. Besser , Frank Mauersberger , Errol Todd Ryan , William S. Brennan , John A. Iacoponi , Peter J. Beckage
发明人： Frederick N. Hause , Paul R. Besser , Frank Mauersberger , Errol Todd Ryan , William S. Brennan , John A. Iacoponi , Peter J. Beckage
IPC分类号： H01L214763
CPC分类号： H01L22/34 , B24B37/042 , B24B49/00 , H01L21/31053 , H01L21/7684 , H01L2924/0002 , H01L2924/00
摘要： A test structure useful in controlling a polishing process of a semiconductor device is provided. The test structure is comprised of a structure layer, a first process layer, and interconnects. The first process layer is positioned above the structure layer and has a plurality of openings formed therein and extending at least partially therethrough to a preselected depth. At least a portion of the plurality of openings have a tapered region progressively narrowing in a direction from the first process layer toward the structure layer. The openings are spaced a preselected distance X apart. The interconnects are formed in the plurality of openings including the tapered region. Thus, as the process layer and interconnects are removed by the polishing process, the distance X increases, indicating the depth of the polishing process.
摘要翻译：提供了一种用于控制半导体器件的抛光工艺的测试结构。测试结构由结构层，第一处理层和互连构成。第一处理层位于结构层上方，并且具有形成在其中并且至少部分地穿过其延伸到预选深度的多个开口。多个开口的至少一部分具有在从第一处理层朝向结构层的方向上逐渐变窄的锥形区域。开口间隔开预定距离X. 互连形成在包括锥形区域的多个开口中。因此，当通过抛光工艺去除工艺层和互连件时，距离X增加，表示抛光过程的深度。

96. 发明授权

US06444513B1 Metal gate stack with etch stop layer having implanted metal species 有权
标题翻译：具有蚀刻停止层的具有植入金属物质的金属栅极叠层
公开(公告)号：US06444513B1
公开(公告)日：2002-09-03
申请号：US09810348
申请日：2001-03-19
申请人： Paul R. Besser , Srikanteswara Dakshina-Murthy
发明人： Paul R. Besser , Srikanteswara Dakshina-Murthy
IPC分类号： H01L218238
CPC分类号： H01L29/4966 , H01L21/28088 , Y10S438/947 , Y10S438/949
摘要： A metal gate structure and method of forming the same introduces metal impurities into a first metal layer, made of TiN, for example. The impurities create a surface region of greater etch selectivity that prevents overetching of the TiN during the etching of an overlying tungsten gate during the formation of the metal gate structure. The prevention of the overetching of the TiN protects the gate oxide from undesirable degradation. The provision of aluminum or tantalum as the metal impurities provides adequate etch stopping capability and does not undesirably affect the work function of the TiN.
摘要翻译：金属栅结构及其形成方法将金属杂质引入例如由TiN制成的第一金属层中。这些杂质产生更大的蚀刻选择性的表面区域，其防止了在形成金属栅极结构期间在覆盖钨栅的蚀刻过程中TiN的过蚀刻。防止TiN的过蚀刻保护栅极氧化物免受不希望的退化。提供铝或钽作为金属杂质提供了足够的蚀刻停止能力，并且不会不希望地影响TiN的功函数。

97. 发明授权

US06406993B1 Method of defining small openings in dielectric layers 有权
标题翻译：定义介电层中小开口的方法
公开(公告)号：US06406993B1
公开(公告)日：2002-06-18
申请号：US09523439
申请日：2000-03-10
申请人： Srikanteswara Dakshina-Murthy , Paul R. Besser , Jonathan B. Smith , Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Lie Larry Zhao , Nicholas J. Kepler
发明人： Srikanteswara Dakshina-Murthy , Paul R. Besser , Jonathan B. Smith , Eric M. Apelgren , Christian Zistl , Jeremy I. Martin , Lie Larry Zhao , Nicholas J. Kepler
IPC分类号： H01L214763
CPC分类号： H01L21/76816 , H01L21/76831
摘要： The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises forming a layer of dielectric material, forming a hard mask layer above the layer of dielectric material, and forming an opening in the hard mask layer. The method further comprises forming a sidewall spacer in the opening in the hard mask layer that defines a reduced opening, forming an opening in the layer of dielectric material below the reduced opening, and forming a conductive interconnection in the opening in the dielectric layer.
摘要翻译：本发明涉及一种形成半导体器件的方法。在一个说明性实施例中，该方法包括形成电介质材料层，在介电材料层之上形成硬掩模层，并在硬掩模层中形成开口。所述方法还包括在所述硬掩模层中的所述开口中形成侧壁间隔物，所述开口限定缩小的开口，在所述还原开口下方的介电材料层中形成开口，以及在所述电介质层的所述开口中形成导电互连。

98. 发明授权

US06329277B1 Method of forming cobalt silicide 有权
标题翻译：形成硅化钴的方法
公开(公告)号：US06329277B1
公开(公告)日：2001-12-11
申请号：US09417839
申请日：1999-10-14
申请人： Bill Yowjuang Liu , Paul R. Besser
发明人： Bill Yowjuang Liu , Paul R. Besser
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L21/28518
摘要： A semiconductor arrangement and method of forming silicide regions includes conformally depositing a reducing material layer on a silicon substrate. A refractory metal layer is then conformally deposited on the reducing material layer. Annealing is then performed to form a refractory metal silicide layer on the silicon substrate. The metal silicide layer is a cobalt silicide and the reducing material layer includes at least one of tantalum, magnesium, aluminum or calcium. The reducing material reduces native oxide on a silicon substrate to allow the cobalt silicide to form.
摘要翻译：形成硅化物区域的半导体布置和方法包括在硅衬底上共形沉积还原材料层。然后将难熔金属层共形沉积在还原材料层上。然后进行退火以在硅衬底上形成难熔金属硅化物层。金属硅化物层是硅化钴，还原材料层包括钽，镁，铝或钙中的至少一种。还原材料减少硅衬底上的自然氧化物以形成硅化钴。

99. 发明授权

US06239494B1 Wire bonding CU interconnects 有权
标题翻译：线接CU互连
公开(公告)号：US06239494B1
公开(公告)日：2001-05-29
申请号：US09295357
申请日：1999-04-21
申请人： Paul R. Besser , Robin W. Cheung
发明人： Paul R. Besser , Robin W. Cheung
IPC分类号： H01L2348
CPC分类号： H01L24/05 , H01L23/53233 , H01L23/53238 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05073 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05187 , H01L2224/05624 , H01L2224/45124 , H01L2224/45144 , H01L2224/48624 , H01L2224/48724 , H01L2224/85375 , H01L2924/01005 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/30105 , H01L2924/00014 , H01L2924/00
摘要： Wire bonding to a Cu interconnect via and Al pad with reduced Al and Cu inter-diffusion is achieved by interposing a barrier layer between the Cu interconnect and Al pad. Embodiments include forming a barrier layer of Ti, Ta, W, alloy thereof or nitride thereof, between the Cu interconnect and the Al pad.
摘要翻译：通过在Cu互连和Al焊盘之间插入势垒层，实现了通过Al和Cu互扩散而减少的Cu互连通孔和Al焊盘的引线接合。实施例包括在Cu互连和Al衬垫之间形成Ti，Ta，W的阻挡层，其合金或其氮化物。

100. 发明授权

US06204177B1 Method of forming junction leakage free metal silicide in a semiconductor wafer by alloying refractory metal 有权
$Method of forming junction leakage free metal silicide in a semiconductor wafer by alloying refractory metal$
标题翻译：通过合金化难熔金属在半导体晶片中形成结无漏电金属硅化物的方法
公开(公告)号：US06204177B1
公开(公告)日：2001-03-20
申请号：US09185515
申请日：1998-11-04
申请人： Paul R. Besser , Nick Kepler , Karsten Wieczorek
发明人： Paul R. Besser , Nick Kepler , Karsten Wieczorek
IPC分类号： H01L2144
CPC分类号： H01L29/665 , H01L21/28518 , H01L29/456 , H01L29/4933
摘要： A method of forming metal silicide in a semiconductor wafer with reduced junction leakage introduces an alloy at cobalt grain boundaries within a cobalt layer that overlays a silicon layer. The alloy element can be precipitated during deposition of the cobalt and the alloy element, or by an intermediate anneal after deposition. The cobalt layer and the silicon layer are then annealed to form metal silicide regions. By precipitating an alloy at the cobalt grain boundaries, cobalt diffusion at the grain boundaries is retarded during a first rapid thermal annealing step. Bulk diffusion is encouraged, and a more uniform silicide film with reduced interface roughness is produced. Since the interface roughness is reduced with the methods of the present invention, junction leakage is reduced. This allows shallower junctions to be fabricated, leading to devices with improved performance.
摘要翻译：在具有减少的结漏电的半导体晶片中形成金属硅化物的方法在覆盖硅层的钴层内的钴晶界处引入合金。在钴和合金元素的沉积期间，或者通过沉积后的中间退火，合金元素可以沉淀。然后将钴层和硅层退火以形成金属硅化物区域。通过在钴晶界析出合金，在第一快速热退火步骤期间，在晶界处的钴扩散被延迟。鼓励扩散，并产生具有降低的界面粗糙度的更均匀的硅化物膜。由于通过本发明的方法减小了界面粗糙度，所以结漏电减少。这允许制造较浅的结，导致具有改进性能的器件。

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