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91. 发明授权

US07689129B2 System-in-package optical transceiver in optical communication with a plurality of other system-in-package optical transceivers via an optical transmission line 有权
标题翻译：通过光传输线与多个其它系统级封装光收发器进行光通信的系统级封装光收发器
公开(公告)号：US07689129B2
公开(公告)日：2010-03-30
申请号：US11201234
申请日：2005-08-10
申请人： Seiji Karashima , Seiichi Nakatani , Yoshiyuki Saito
发明人： Seiji Karashima , Seiichi Nakatani , Yoshiyuki Saito
IPC分类号： H04B10/00
CPC分类号： G06F15/16 , H04L12/00
摘要： A parallel computation apparatus as a multiprocessor includes functional modules as a plurality of processors having an optical communication function and capable of mutually cooperating, and an optical transmission line interconnecting the plurality of processors. Among the plurality of functional modules, the first functional module having a first information processing capacity has a function of determining whether information processing of a first information processing amount can be completed based on the first information processing capacity, and outputting a second information processing amount obtained by subtracting an information processing amount based on the first information processing capacity from the first information processing amount to at least one of the other functional modules.
摘要翻译：作为多处理器的并行计算装置包括具有光通信功能并且能够相互配合的多个处理器的功能模块以及互连多个处理器的光传输线。在多个功能模块中，具有第一信息处理能力的第一功能模块具有根据第一信息处理能力确定是否能够完成第一信息处理量的信息处理的功能，并且输出获得的第二信息处理量通过从第一信息处理量减去基于第一信息处理能力的信息处理量到至少一个其他功能模块。

92. 发明授权

US07683874B2 Liquid crystal display device 失效
标题翻译：液晶显示装置
公开(公告)号：US07683874B2
公开(公告)日：2010-03-23
申请号：US11905356
申请日：2007-09-28
申请人： Takahiro Fujioka , Shigeru Ito , Mitsuru Goto , Yozo Nakayasu , Yoshiyuki Saito
发明人： Takahiro Fujioka , Shigeru Ito , Mitsuru Goto , Yozo Nakayasu , Yoshiyuki Saito
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/2011 , G09G5/18 , G09G2370/08
摘要： A liquid crystal display device capable of improving display quality by enabling proper execution of receipt and acceptance of image signals through compensation for variation in duty ratios of clock signals as input to liquid crystal driver circuitry, is provided. In a liquid crystal display device comprising a liquid crystal display element and liquid crystal driver circuitry, the liquid crystal driver circuitry is operable to receive an image signal as input thereto for taking it into a bus at the timing of a change of an internal clock signal from a first level to a second level or alternatively its change from the second level to the first level and then select from the image signal as taken or “accepted” into the bus a voltage used to drive the liquid crystal display element, wherein the internal clock signal is the clock signal that causes a first level period and a second level period of an external clock signal being input to the liquid crystal driver circuitry to be made identical or equalized by a clock compensation circuit to specified values respectively.
摘要翻译：提供一种液晶显示装置，其能够通过对作为输入到液晶驱动电路的时钟信号的占空比的变化进行补偿来适当地执行图像信号的接收和接收来提高显示质量。在包括液晶显示元件和液晶驱动器电路的液晶显示装置中，液晶驱动器电路可操作以接收作为其输入的图像信号，以在内部时钟信号改变的定时将其输入总线从第一电平到第二电平或者其从第二电平到第一电平的变化，然后从图像信号中选择被采取或“接受”到总线中用于驱动液晶显示元件的电压，其中内部时钟信号是使得输入到液晶驱动器电路的外部时钟信号的第一电平周期和第二电平周期分别由时钟补偿电路相同或均衡的时钟信号。

93. 发明申请

US20090106460A1 REMOVABLE MEMORY DEVICE, PHASE SYNCHRONIZING METHOD, PHASE SYNCHRONIZING PROGRAM, MEDIUM RECORDING THE SAME, AND HOST TERMINAL 有权
标题翻译：可拆卸存储器件，相位同步方法，相位同步程序，记录其中的介质和终端
公开(公告)号：US20090106460A1
公开(公告)日：2009-04-23
申请号：US12295051
申请日：2007-02-20
申请人： Hiroshi Suenaga , Osamu Shibata , Noriaki Takeda , Toru Iwata , Takaharu Yoshida , Yoshiyuki Saito
发明人： Hiroshi Suenaga , Osamu Shibata , Noriaki Takeda , Toru Iwata , Takaharu Yoshida , Yoshiyuki Saito
IPC分类号： G06F3/00
CPC分类号： H04L7/10 , G06F1/12 , H04L7/0008 , H04L7/033 , H04L7/044 , H04L7/046
摘要： An object of the present invention is to provide a technique to improve the data transmission efficiency which allows correct reception of the data at the same time. A removable memory device that transmits/receives data to and from a host terminal, which includes: a clock reception section 41 of receiving transmission/reception clock, which is used for transmitting/receiving data between the host terminal and the removable memory device, from the host terminal; a phase synchronization pattern generation section 45 of generating a phase synchronization pattern, which is for adjusting a phase of internal reception clock which the host terminal incorporates for receiving data from the removable memory device, based on the transmission/reception clock; and a transmission section of transmitting the generated phase synchronization pattern to the host terminal, and in which the phase synchronization pattern includes a first level signal which lasts for at least two cycles, and a second level signal which follows the first level signal and lasts for one cycle, is provided.
摘要翻译：本发明的目的是提供一种提高数据传输效率的技术，其允许同时正确地接收数据。一种向主机终端发送/接收数据的可移动存储装置，包括：用于在主机终端和可移动存储装置之间发送/接收数据的接收发送/接收时钟的时钟接收部分41，主机终端; 生成相位同步模式的相位同步模式生成部45，用于基于发送/接收时钟来调整主机终端结合的用于从可移动存储装置接收数据的内部接收时钟的相位; 以及发送部，其将生成的相位同步模式发送到主机终端，并且其中相位同步模式包括持续至少两个周期的第一电平信号，以及跟随第一电平信号并持续的第二电平信号提供一个循环。

94. 发明申请

US20090008131A1 Flexible printed-circuit board 审中-公开
标题翻译：柔性印刷电路板
公开(公告)号：US20090008131A1
公开(公告)日：2009-01-08
申请号：US11659131
申请日：2005-07-28
申请人： Osamu Shibata , Takeshi Nakayama , Yoshiyuki Saito
发明人： Osamu Shibata , Takeshi Nakayama , Yoshiyuki Saito
IPC分类号： H05K1/02
CPC分类号： H05K1/0219 , H05K1/0237 , H05K1/118 , H05K2201/055 , H05K2201/09236 , H05K2201/09445 , H05K2201/09727
摘要： A flexible printed board that is adapted to high-speed transmission and can mount a plurality of connectors at low cost is provided. The board comprises a flexible printed board body 100 that has a first side 100a and a second side 100b opposed to each other, and an overlap portion 105 formed by bending its one end; a plurality of wiring lines 101 that are arranged on the first side 100a of the body substantially in parallel to each other; first pads 103 that are connected to respective ends of wiring lines, wider than the wiring lines and formed on the first-side surface 105a of the overlap potion; and second pads 104 that are located at respective ends of wiring lines, wider than the wiring lines and formed on the second-side surface 105b of the overlap potion. The wiring lines 101a with the first pads connected thereto and the wiring lines 101b with the second pads 104 connected thereto are alternatively arranged on the first side.
摘要翻译：提供了适用于高速传输并可以以低成本安装多个连接器的柔性印刷电路板。板包括具有彼此相对的第一侧100a和第二侧面100b的柔性印刷电路板主体100和通过使其一端弯曲形成的重叠部分105; 布置在主体的第一侧100a上的多个布线101基本上彼此平行; 第一焊盘103，其连接到布线的相应端部，比布线宽，并形成在重叠部分的第一侧表面105a上; 以及第二焊盘104，其位于布线的相应端部，比布线宽，并且形成在重叠部分的第二侧表面105b上。具有与其连接的第一焊盘的布线101a和与其连接的第二焊盘104的布线101b交替布置在第一侧上。

95. 发明申请

US20070252659A1 Filter Circuit, Differential Transmission System Having Same, and Power Supply 审中-公开
标题翻译：滤波电路，差分传输系统和电源
公开(公告)号：US20070252659A1
公开(公告)日：2007-11-01
申请号：US11664129
申请日：2005-08-01
申请人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito , Noboru Katta , Yuji Mizuguchi
发明人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito , Noboru Katta , Yuji Mizuguchi
IPC分类号： H03H7/38
CPC分类号： H01F17/0013 , H01F2017/0093 , H03H7/09 , H03H7/427 , H03H2001/0085 , H04B3/30 , H04L12/40032 , H04L2012/40215 , H04L2012/4026
摘要： In a filter circuit (1), a common mode choke (2) and a normal mode choke (3) have extremely high and low impedances, respectively, for common mode signals received through two input terminals (1a and 1b). The chokes have the opposite impedance characteristics for differential signals. In particular, the difference in impedance is large. Furthermore, the normal mode choke (3) is installed as a previous stage of the common mode choke (2). Accordingly, common mode noises which enter the two input terminals (1a and 1b) penetrate the normal mode choke (3), but neither penetrate the common mode choke (2) nor are reflected from the common mode choke (2). In particular, common mode currents flow through the normal mode choke (3) but do not flow through the common mode choke (2).
摘要翻译：在滤波器电路（1）中，对于通过两个输入端子（1a和1b）接收的共模信号，共模扼流圈（2）和正常模式扼流圈（3）分别具有极高和低阻抗。扼流圈对差分信号具有相反的阻抗特性。特别地，阻抗的差异很大。此外，正常模式扼流圈（3）安装为共模扼流圈（2）的前一级。因此，进入两个输入端子（1a和1b）的共模噪声穿透正常模式扼流圈（3），但都不穿透共模扼流圈（2），也不会从共模扼流圈（2）反射。特别地，共模电流流过正常模式扼流圈（3），但不流过共模扼流圈（2）。

96. 发明申请

US20070124926A1 CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：电路板及其制造方法
公开(公告)号：US20070124926A1
公开(公告)日：2007-06-07
申请号：US11674454
申请日：2007-02-13
申请人： Yukihiro Ishimaru , Seiichi Nakatani , Yoshiyuki Saito
发明人： Yukihiro Ishimaru , Seiichi Nakatani , Yoshiyuki Saito
IPC分类号： H05K1/03
CPC分类号： H05K3/4038 , H05K1/167 , H05K3/105 , H05K3/4644 , H05K2201/0326 , H05K2203/107 , H05K2203/171 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165
摘要： In a circuit board according to the present invention, on a substrate, in at least a portion of a phase change layer including a phase change material that is capable of changing alternately between an electrically insulating state and an electrically conductive state, a conductive path is formed that has been put into an electrically conductive state by a phase change in the phase change layer, wherein the phase change material includes a chalcogenide semiconductor, changes between the electrically insulating state and the electrically conductive state by irradiation of laser light, goes into the electrically conductive state in a crystalline phase, and goes into the electrically insulating state in an amorphous phase. In this way, a conductive path is formed by irradiating laser light onto a phase change layer using phase change in a phase change layer formed from a phase change material that is capable of changing alternately between an electrically insulating state and an electrically conductive state, and therefore very small-dimension minute vias and conductors can be formed. Furthermore, subsequent repair, rework, or trimming also is easy.
摘要翻译：在根据本发明的电路板中，在基板上，在包括能够在电绝缘状态和导电状态之间交替变化的相变材料的相变层的至少一部分中，导电路径为形成为通过相变层中的相变而导致导电状态，其中相变材料包括硫族化物半导体，通过激光的照射在电绝缘状态和导电状态之间的变化进入在结晶相中导电状态，并且在非晶相中进入电绝缘状态。以这种方式，通过使用在能够在电绝缘状态和导电状态之间交替变化的相变材料形成的相变层中的相变来将激光照射到相变层上形成导电路径，以及因此可以形成非常小尺寸的微通孔和导体。此外，随后的修理，返修或修整也很容易。

97. 发明授权

US07161762B2 Magnetic recording and reproduction apparatus 失效
标题翻译：磁记录和再现设备
公开(公告)号：US07161762B2
公开(公告)日：2007-01-09
申请号：US10803127
申请日：2004-03-17
申请人： Koichiro Hirabayashi , Yoshiyuki Saito , Hiroshi Kurumatani
发明人： Koichiro Hirabayashi , Yoshiyuki Saito , Hiroshi Kurumatani
IPC分类号： G11B15/20
CPC分类号： G11B15/6656
摘要： A magnetic recording and reproduction apparatus includes a main chassis having a rotatable head cylinder provided thereon; a sub chassis on which a tape cassette is mountable; and a plurality of tape pull-out members acting so as to pull out a tape from the tape cassette. The sub chassis is movable with respect to the main chassis between a tape cassette mountable position and a tape pull-out completion position, and the tape cassette mountable position is the position at which the tape cassette is mountable on the sub chassis and the tape pull-out completion position is the position at which information recording to, and information reproduction from, the tape which has been pulled out from the tape cassette and wound around the rotatable head cylinder can be performed. All the plurality of tape pull-out members are mounted on the sub chassis.
摘要翻译：一种磁记录和再现装置，包括：一个设置在其上的可旋转头筒的主底盘; 可安装盒式磁带的副机架; 以及用于从带盒拉出带子的多个带拉出构件。副底盘可以在盒式磁带可安装位置和磁带拉出完成位置之间相对于主机架移动，并且磁带盒可安装位置是磁带盒可安装在副机架上的位置，磁带拉 - 完成位置是可以执行从磁带盒拉出并缠绕在可旋转磁头气缸上的磁带的信息记录和信息再现的位置。所有多个磁带拉出构件安装在副机架上。

98. 发明申请

US20060117883A1 Worm support device and power assist unit having the same 有权
公开(公告)号：US20060117883A1
公开(公告)日：2006-06-08
申请号：US10537791
申请日：2003-12-05
申请人： Hirotaka Yasuda , Hirotsugu Kusano , Wataru Yamada , Yoshiyuki Saito , Shuzo Hirakushi
发明人： Hirotaka Yasuda , Hirotsugu Kusano , Wataru Yamada , Yoshiyuki Saito , Shuzo Hirakushi
IPC分类号： F16H35/00
CPC分类号： B62D5/0409 , F16C19/06 , F16C19/54 , F16C33/585 , F16C2240/76 , F16C2326/24 , F16C2361/61 , F16C2380/27 , F16H1/16 , F16H55/24 , F16H57/021 , F16H2057/0213 , Y10T74/19828
摘要： Deep groove ball bearings are used as bearings supporting both side portions of a worm. In the first bearing on the side of a motor, the curvature radius of a raceway groove in an inner ring or the curvature radius of a raceway groove in an outer ring are set to a specific numerical range with respect to the diameter of a ball.

99. 发明申请

US20060036831A1 Multiprocessor 有权
标题翻译：多处理器
公开(公告)号：US20060036831A1
公开(公告)日：2006-02-16
申请号：US11201234
申请日：2005-08-10
申请人： Seiji Karashima , Seiichi Nakatani , Yoshiyuki Saito
发明人： Seiji Karashima , Seiichi Nakatani , Yoshiyuki Saito
IPC分类号： G06F12/10 , G06F9/34
CPC分类号： G06F15/16 , H04L12/00
摘要： A parallel computation apparatus as a multiprocessor includes functional modules as a plurality of processors having an optical communication function and capable of mutually cooperating, and an optical transmission line interconnecting the plurality of processors. Among the plurality of functional modules, the first functional module having a first information processing capacity has a function of determining whether information processing of a first information processing amount can be completed based on the first information processing capacity, and outputting a second information processing amount obtained by subtracting an information processing amount based on the first information processing capacity from the first information processing amount to at least one of the other functional modules.
摘要翻译：作为多处理器的并行计算装置包括具有光通信功能并且能够相互配合的多个处理器的功能模块以及互连多个处理器的光传输线。在多个功能模块中，具有第一信息处理能力的第一功能模块具有根据第一信息处理能力确定是否能够完成第一信息处理量的信息处理的功能，并且输出获得的第二信息处理量通过从第一信息处理量减去基于第一信息处理能力的信息处理量到至少一个其他功能模块。

100. 发明申请

US20050219006A1 Differential transmission circuit and common mode choke coil 失效
标题翻译：差动传输电路和共模扼流线圈
公开(公告)号：US20050219006A1
公开(公告)日：2005-10-06
申请号：US11085078
申请日：2005-03-22
申请人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito
发明人： Hiroshi Suenaga , Osamu Shibata , Yoshiyuki Saito
IPC分类号： H01F17/06 , H01P5/00 , H03H7/38 , H03H7/42 , H04B3/28 , H04B3/30 , H04L25/02
CPC分类号： H01F17/06 , H01F2017/0093 , H01F2017/067 , H04L25/0272
摘要： A first transmission line for transmitting a first signal and a second transmission line for transmitting a second signal, which has the reverse phase of the first signal, are connected in series with a common mode choke coil. A third transmission line and fourth transmission line are each connected in series with the common mode choke coil, and transmit the first and second signals. A semiconductor device is connected in series with the third and fourth transmission lines, so as to transmit and receive the first and second signals. One end of a first terminator is connected in parallel with the first transmission line, and the other end is connected to the common mode choke coil. One end of a second terminator is connected in parallel with the second transmission line, and the other end is connected to the common mode choke coil. The noise eliminating capability of the common mode choke coil is increase by means of this structure.
摘要翻译：用于发送第一信号的第一传输线和用于发送具有第一信号的相反相位的第二信号的第二传输线与共模扼流线圈串联连接。第三传输线和第四传输线各自与共模扼流线圈串联连接，并发送第一和第二信号。半导体器件与第三和第四传输线串联连接，以便发送和接收第一和第二信号。第一终端器的一端与第一传输线并联连接，另一端连接到共模扼流线圈。第二终端器的一端与第二传输线并联连接，另一端连接到共模扼流线圈。通过这种结构，增加了共模扼流线圈的噪声消除能力。

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