专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US06808850B2 Performing optical proximity correction on trim-level segments not abutting features to be printed 有权
公开(公告)号：US06808850B2
公开(公告)日：2004-10-26
申请号：US10277250
申请日：2002-10-21
申请人： Christophe Pierrat
发明人： Christophe Pierrat
IPC分类号： G03F900
CPC分类号： G03F1/36 , G03F1/26 , G03F1/30 , G03F1/70 , G03F7/70441
摘要： One embodiment of the invention provides a system that performs optical proximity correction (OPC) on selected segments on a trim mask used in fabricating an integrated circuit. Upon receiving the trim mask, the system identifies selected segments on the trim mask that do not abut any feature to be printed on the integrated circuit. Next, the system performs a number of OPC operations. The system performs a first OPC operation on the selected segments to correct the selected segments. The system also performs a second OPC operation to correct segments on the trim mask that do abut features to be printed on the integrated circuit. The system additionally performs a third OPC operation on an associated phase shifting mask to correct segments that abut features to be printed on the integrated circuit. (Note that the first, second and third OPC operations can be performed separately or at the same time.)

92. 发明授权

US06777141B2 Phase shift mask including sub-resolution assist features for isolated spaces 有权
标题翻译：相移掩模包括用于隔离空间的子分辨率辅助功能
公开(公告)号：US06777141B2
公开(公告)日：2004-08-17
申请号：US10244226
申请日：2002-09-16
申请人： Christophe Pierrat
发明人： Christophe Pierrat
IPC分类号： G03F900
CPC分类号： G03F1/30 , G03F1/36
摘要： A method extends the use of phase shift techniques to complex layouts, and includes identifying a pattern, and automatically mapping the phase shifting regions for implementation of such features. The pattern includes small features having a dimension smaller than a first particular feature size, and at least one relatively large feature, the at least one relatively large feature and another feature in the pattern having respective sides separated by a narrow space. Phase shift regions are laid out including a first set of phase shift regions to define said small features, and a second set of phase shift regions to assist definition of said side of said relatively large feature. An opaque feature is used to define the relatively large feature, and a phase shift region in the second set is a sub-resolution window inside the perimeter of the opaque feature.
摘要翻译：一种方法将相移技术的使用扩展到复杂的布局，并且包括识别图案，并且自动映射用于实现这些特征的相移区域。该图案包括具有小于第一特定特征尺寸的尺寸的小特征以及至少一个相对较大的特征，该图案中的至少一个相对大的特征和另一特征具有由狭窄空间分开的相应侧面。布置相移区域，其包括第一组相移区域以限定所述小特征，以及第二组相移区域，以辅助所述相对较大特征的所述侧面的定义。使用不透明特征来定义相对较大的特征，并且第二组中的相移区域是不透明特征的周边内的子分辨率窗口。

93. 发明授权

US06681379B2 Phase shifting design and layout for static random access memory 有权
标题翻译：静态随机存取存储器的相移设计和布局
公开(公告)号：US06681379B2
公开(公告)日：2004-01-20
申请号：US09996973
申请日：2001-11-15
申请人： Christophe Pierrat , Michel Luc Côté
发明人： Christophe Pierrat , Michel Luc Côté
IPC分类号： G06F1750
CPC分类号： G03F7/70433 , G03F1/26 , G03F1/30 , G03F1/36 , G03F1/70 , G03F7/70425 , G03F7/70466
摘要： Methods and apparatuses for fully defining static random access memory (SRAM) using phase shifting layouts are described. The approach includes identifying that a layout includes SRAM cells and defining phase shifting regions in a mask description to fully define the SRAM cells. The phase conflicts between adjacent phase shifters are resolved by selecting cutting patterns designed for the SRAM shape and functional structure. Additionally, the transistor gates of the SRAM cells can be reduced in size relative to the original SRAM layout design. Thus, an SRAM cell can be lithographically printed with small, consistent critical dimensions including extremely small gate lengths resulting in higher yields and improved performance.
摘要翻译：描述了使用相移布局完全定义静态随机存取存储器（SRAM）的方法和装置。该方法包括识别布局包括SRAM单元并且在掩模描述中定义相移区域以完全限定SRAM单元。通过选择为SRAM形状和功能结构设计的切割图案来解决相邻移相器之间的相位冲突。另外，相对于原始的SRAM布局设计，SRAM单元的晶体管栅极的尺寸可以减小。因此，SRAM单元可以被光刻印刷，具有小的，一致的临界尺寸，包括非常小的栅极长度，导致更高的产量和改进的性能。

94. 发明授权

US06653026B2 Structure and method of correcting proximity effects in a tri-tone attenuated phase-shifting mask 有权
公开(公告)号：US06653026B2
公开(公告)日：2003-11-25
申请号：US09746369
申请日：2000-12-20
申请人： Christophe Pierrat , Youping Zhang
发明人： Christophe Pierrat , Youping Zhang
IPC分类号： G03F900
CPC分类号： G03F1/29 , G03F1/32 , G03F1/36
摘要： A structure and method are provided for correcting the optical proximity effects on a tri-tone attenuated phase-shifting mask. An attenuated rim, formed by an opaque region and an attenuated phase-shifting region, can be kept at a predetermined width across the mask or for certain types of structures. Typically, the attenuated rim is made as large as possible to maximize the effect of the attenuated phase-shifting region while still preventing the printing of larger portions of the attenuated phase-shifting region during the development process.

95. 发明授权

US06625801B1 Dissection of printed edges from a fabrication layout for correcting proximity effects 有权
公开(公告)号：US06625801B1
公开(公告)日：2003-09-23
申请号：US09676375
申请日：2000-09-29
申请人： Christophe Pierrat , Youping Zhang
发明人： Christophe Pierrat , Youping Zhang
IPC分类号： G06F1750
CPC分类号： G03F1/36 , Y10T428/24802
摘要： Techniques for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Techniques include correcting for proximity effects associated with an edge in a first fabrication layout by determining whether any portion of the edge corresponds to a target edge in a design layer. The first fabrication layout corresponds to the design layer that indicates target edges for a printed features layer. If any portion of the edge corresponds to the target edge, then it is determined whether to establish an evaluation point on the edge. Then it is determined how to correct the edge for proximity effects based on the evaluation point. In case it is determined that no portion of the edge corresponds to the target edge, then no evaluation point is selected on the edge.

96. 发明授权

US06610449B2 Phase shift masking for “double-T” intersecting lines 有权
标题翻译： “双T”相交线的相移屏蔽
公开(公告)号：US06610449B2
公开(公告)日：2003-08-26
申请号：US10224064
申请日：2002-08-20
申请人： Christophe Pierrat
发明人： Christophe Pierrat
IPC分类号： G03F900
CPC分类号： G03F1/30 , G03F1/36
摘要： Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex “double-T” layouts in the layers of integrated circuits, beyond selected critical dimension features such as transistor gates to which such structures have been limited in the past. The method includes identifying features, including “double-T” features, for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and application of sub-resolution assist features within phase shift regions and optical proximity correction features to phase shift regions. Both opaque field phase shift masks and complementary binary masks defining interconnect structures and other types of structures that are not defined using phase shifting, necessary for completion of the layout of the layer are produced.
摘要翻译：提供的技术用于将相移技术的使用扩展到实现用于集成电路层中的复杂“双T”布局的掩模，超出了过去已经限制了这种结构的所选临界尺寸特征，例如晶体管栅极。该方法包括识别特征，包括可以应用相移的“双T”特征，自动映射用于实现这些特征的相移区域，解决根据给定设计规则可能发生的相位冲突，以及应用相移区域内的辅助分辨率辅助功能和相移区域的光学接近校正特征。产生不完整的场相移掩模和定义互连结构的互补二进制掩模和不使用相移定义的其它类型的结构，这些结构对于完成层的布局是必需的。

97. 发明授权

US06577010B2 Stepped photoresist profile and opening formed using the profile 有权
公开(公告)号：US06577010B2
公开(公告)日：2003-06-10
申请号：US09996253
申请日：2001-11-28
申请人： Shubneesh Batra , Christophe Pierrat
发明人： Shubneesh Batra , Christophe Pierrat
IPC分类号： H01L2348
CPC分类号： H01L21/308 , H01L21/0274 , H01L21/76804 , H01L29/8126
摘要： Stepped photoresist profiles provide various methods of forming profiles in an underlying substrate. The stepped photoresist profiles are formed in two layers of photoresist that are disposed over the substrate. The substrate is then etched twice using a respective opening in each photoresist layer to create a stepped profile in the substrate.

98. 发明授权

US06503666B1 Phase shift masking for complex patterns 有权
标题翻译：复杂图案的相移屏蔽
公开(公告)号：US06503666B1
公开(公告)日：2003-01-07
申请号：US09669359
申请日：2000-09-26
申请人： Christophe Pierrat
发明人： Christophe Pierrat
IPC分类号： G03F900
CPC分类号： G03F1/26 , G03F1/29 , G03F1/30 , G03F1/70
摘要： Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex layouts in the layers of integrated circuits, beyond selected critical dimension features such as transistor gates to which such structures have been limited in the past. The method includes identifying features for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and application of sub-resolution assist features within phase shift regions and optical proximity correction features to phase shift regions. Both opaque field phase shift masks and complementary binary masks defining interconnect structures and other types of structures that are not defined using phase shifting, necessary for completion of the layout of the layer are produced.
摘要翻译：提供了技术，用于将相移技术的使用扩展到在集成电路层中复杂布局的掩模的实现，超出了过去已经限制了这种结构的所选临界尺寸特征，例如晶体管栅极。该方法包括识别可以对其进行相移的特征，自动映射用于实现这些特征的相移区域，解决根据给定设计规则可能发生的相位冲突，以及在相移区域内应用子分辨率辅助特征和光学邻近校正特征到相移区域。产生不完整的场相移掩模和定义互连结构的互补二进制掩模和不使用相移定义的其它类型的结构，这些结构对于完成层的布局是必需的。

99. 发明授权

US06472280B2 Method for forming a spacer for semiconductor manufacture 失效
标题翻译：用于形成用于半导体制造的间隔物的方法
公开(公告)号：US06472280B2
公开(公告)日：2002-10-29
申请号：US09817728
申请日：2001-03-26
申请人： Nanseng Jeng , Christophe Pierrat
发明人： Nanseng Jeng , Christophe Pierrat
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/0337
摘要： Methods for forming self-aligned photosensitive material spacers about protruding structures in semiconductor devices. One embodiment of the invention is a method for forming a LDD structure, utilizing disposable photosensitive material spacers. A second embodiment of the invention includes a method for forming a transistor, having salicided source/drain regions, utilizing photosensitive polyimide spacers for forming the salicided source/drain regions, without disposing of the spacers. A third embodiment of the invention includes a method for creating an offset from a protruding structure on a semiconductor substrate, using disposable photosensitive material spacers.
摘要翻译：用于在半导体器件中形成围绕突出结构的自对准感光材料间隔物的方法。本发明的一个实施例是一种利用一次性感光材料间隔物形成LDD结构的方法。本发明的第二实施例包括一种用于形成具有水银源/漏极区域的晶体管的方法，其利用光敏聚酰亚胺间隔物来形成水银源/漏区，而不处理间隔物。本发明的第三实施例包括使用一次性感光材料间隔件从半导体衬底上的突出结构产生偏移的方法。

100. 发明授权

US06453457B1 Selection of evaluation point locations based on proximity effects model amplitudes for correcting proximity effects in a fabrication layout 有权
标题翻译：基于邻近效应的评估点位置的选择用于在制造布局中校正邻近效应的模型幅度
公开(公告)号：US06453457B1
公开(公告)日：2002-09-17
申请号：US09676356
申请日：2000-09-29
申请人： Christophe Pierrat , Youping Zhang
发明人： Christophe Pierrat , Youping Zhang
IPC分类号： G06F1750
CPC分类号： G03F1/36 , G03F1/70 , Y10S977/734
摘要： Techniques for fabricating a device include forming a fabrication layout such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Included are techniques that correct for proximity effects associated with an edge in a layout corresponding to a design layer. An evaluation point is determined for the edge based on a profile of amplitudes output from a proximity effects model along a transect. The transect includes a target edge in the design layer corresponding to the edge. It is then determined how to correct at least a portion of the edge for proximity effects based on an analysis at the evaluation point. In other techniques, a dissection length parameter is derived based on a profile of amplitudes output by a proximity effects model along a transect. The transect includes a second edge in a second layout. An evaluation point is determined for a first edge based on the dissection length parameter. Then it is determined how to correct at least a portion of the first edge based on an analysis at the evaluation point.
摘要翻译：用于制造器件的技术包括形成用于物理设计层（例如集成电路的设计）的掩模布局的制造布局，以及识别与设计层对应的多边形的边缘上的评估点，用于校正邻近效应。包括的技术是校正与对应于设计层的布局中的边缘相关联的邻近效应。基于沿着截面的邻近效应模型输出的幅度分布，确定边缘的评估点。横断面包括对应于边缘的设计层中的目标边缘。然后基于评估点的分析确定如何校正边缘的至少一部分以用于邻近效应。在其他技术中，解剖长度参数是基于沿着截面的邻近效应模型输出的幅度分布导出的。横断面包括第二布局中的第二边缘。基于解剖长度参数确定第一边缘的评估点。然后，基于评估点的分析，确定如何校正第一边缘的至少一部分。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式