专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明申请

US20100279521A1 LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES 有权
标题翻译：土地网阵列（LGA）利用金属激光器热电偶和其他多点接触几何
公开(公告)号：US20100279521A1
公开(公告)日：2010-11-04
申请号：US12061774
申请日：2008-04-03
申请人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
发明人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
IPC分类号： H01R12/00
CPC分类号： H01R12/714 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H05K3/326 , H05K3/4007 , H05K7/1061 , H05K2201/0133 , H05K2201/0367 , H05K2201/09481 , H05K2201/09745 , H05K2201/10378 , H05K2201/10734 , Y10T29/49002 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49151 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T29/49204 , Y10T29/49208 , Y10T29/49213 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.
摘要翻译：一种制造包括电绝缘载体平面的平面栅格阵列（LGA）插入器结构以及安装在所述载体平面的第一表面上的至少一个插入件的方法。插入件在横截面中具有半环形结构，并由介电弹性体材料构成。多个导电元件围绕至少一个半环形插入器的表面布置，并且从其最上端向内和向下自由地延伸，与位于电绝缘载体平面相反侧的至少一个部件电接触。

92. 发明授权

US07658616B2 Groups of land grid interposers of different heights having metal-on elastomer hemi-torus shapes providing for electrical contact with at least one component on an opposite side of an electrically insulating carrier plate mounting interposers 失效
标题翻译：具有不同高度的地面栅格插入件组具有金属弹性体半环形状，其提供与电绝缘载板安装插入件的相对侧上的至少一个部件的电接触
公开(公告)号：US07658616B2
公开(公告)日：2010-02-09
申请号：US12328026
申请日：2008-12-04
申请人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
发明人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
IPC分类号： H01R12/00
CPC分类号： H01R12/714 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H05K3/326 , H05K3/4007 , H05K7/1061 , H05K2201/0133 , H05K2201/0367 , H05K2201/09481 , H05K2201/09745 , H05K2201/10378 , H05K2201/10734 , Y10T29/49002 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49151 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T29/49204 , Y10T29/49208 , Y10T29/49213 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and interposer groupings of different height being mounted on a first surface of said carrier plane. Each interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of each hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.
摘要翻译：包括电绝缘载体平面和不同高度的插入物分组的平面栅格阵列（LGA）插入器结构安装在所述载体平面的第一表面上。每个插入件在横截面中具有半环形结构并且由介电弹性体材料构成。多个导电元件围绕每个半环形插入器的表面布置，并且从其最上端向内和向下自由地延伸，与位于电绝缘载体平面相反侧的至少一个部件电接触。

93. 发明授权

US07636262B2 Synchronous memory having shared CRC and strobe pin 失效
标题翻译：具有共享CRC和选通引脚的同步存储器
公开(公告)号：US07636262B2
公开(公告)日：2009-12-22
申请号：US11923691
申请日：2007-10-25
申请人： Kyu-Hyoun Kim , Paul W. Coteus
发明人： Kyu-Hyoun Kim , Paul W. Coteus
IPC分类号： G11C7/10
CPC分类号： G06F13/1689 , G06F11/1004
摘要： A memory system having a memory element chip (DRAM) and a memory controller chips having a plurality of drivers and receivers and latches for transferred data. For writes clocks, write data and write for CRC (cyclic redundancy checks) is transferred to the DRAM from the memory controller and latched for error checking. The reads are clocked and the read data is received and transferred to a read data latch with also receives a clocked read strobe for verification of data integrity from DRAM. Each chip has a bi-functional pin that acts as a shared CRC pin during write and acts as a shared strobe pin during READ. Data transfers with the CRC signal and DQS signal are transferred across two paths CRC0/DQS and CRC1/DQS1. One could also transfer the CRC signal across one path with only the CRC0/DQS signal. Read operations have no CRC, and have no need for CRC because transfer errors during read can be detected by memory error correction coding (ECC). Write data provides source synchronous I/O data to said memory element chip needed for modem high speed memory communications.
摘要翻译：具有存储元件芯片（DRAM）的存储器系统和具有用于传送数据的多个驱动器和接收器以及锁存器的存储器控制器芯片。对于写时钟，写入数据和写入CRC（循环冗余校验）从存储器控制器传送到DRAM，并锁存进行错误检查。读取被计时，并且读取的数据被接收并被传送到读取数据锁存器，同时还接收用于从DRAM确认数据完整性的时钟读选通脉冲。每个芯片都有一个双功能引脚，在写入期间充当共享的CRC引脚，并在读取期间充当共享的选通引脚。具有CRC信号和DQS信号的数据传输通过两个路径CRC0 / DQS和CRC1 / DQS1传送。也可以通过CRC0 / DQS信号在一个路径上传送CRC信号。读操作没有CRC，并且不需要CRC，因为可以通过存储器纠错编码（ECC）来检测读取期间的传输错误。写入数据将源同步I / O数据提供给调制解调器高速存储器通信所需的所述存储器元件芯片。

94. 发明申请

US20090273960A1 SYSTEM FOR PROVIDING ON-DIE TERMINATION OF A CONTROL SIGNAL BUS 有权
标题翻译：用于提供控制信号总线接线端子的系统
公开(公告)号：US20090273960A1
公开(公告)日：2009-11-05
申请号：US12112391
申请日：2008-04-30
申请人： Kyu-hyoun Kim , Paul W. Coteus
发明人： Kyu-hyoun Kim , Paul W. Coteus
IPC分类号： G11C5/02 , G11C7/00 , H03K19/003
CPC分类号： G11C7/1078 , G11C7/1048 , G11C7/109 , H04L25/0298
摘要： A system for providing on-die termination (ODT) of a control signal bus. The system includes a memory device that includes a plurality of data bus connectors, one or both of a load signal connector and a reset signal connector, a control bus connector, an ODT, and a mechanism. The ODT is in communication with the control bus connector, and the ODT provides a level of termination resistance to a control bus connected to the control bus connector. The mechanism latches data received via the data bus connectors in response to a signal received via one or both of the load signal connector and the reset signal connector. The data is utilized to set the level of termination resistance provided by the ODT.
摘要翻译：一种用于提供控制信号总线的管芯端接（ODT）的系统。该系统包括存储器件，其包括多个数据总线连接器，负载信号连接器和复位信号连接器中的一个或两个，控制总线连接器，ODT和机构。 ODT与控制总线连接器通信，ODT为连接到控制总线连接器的控制总线提供一定程度的终端电阻。该机构响应于经由一个或两个负载信号连接器和复位信号连接器接收到的信号，锁存经由数据总线连接器接收的数据。该数据用于设置由ODT提供的终端电阻的电平。

95. 发明授权

US07612621B2 System for providing open-loop quadrature clock generation 失效
标题翻译：提供开环正交时钟生成系统
公开(公告)号：US07612621B2
公开(公告)日：2009-11-03
申请号：US11749409
申请日：2007-05-16
申请人： Kyu-hyoun Kim , Paul W. Coteus , Daniel M. Dreps
发明人： Kyu-hyoun Kim , Paul W. Coteus , Daniel M. Dreps
IPC分类号： H03B27/00
CPC分类号： H03K5/151 , H03K5/13 , H03K2005/00052 , H03K2005/00234
摘要： A system for providing open-loop quadrature clock generation. The system is implemented by a ring oscillator structure that includes input inverters for receiving an input clock, forward direction loop inverters, backward direction loop inverters, one or more outputs, and cross-coupled latches connected between any two opposite nodes.
摘要翻译：一种用于提供开环正交时钟生成的系统。该系统由环形振荡器结构实现，该环形振荡器结构包括用于接收输入时钟的输入反相器，正向环路逆变器，反向环路逆变器，一个或多个输出以及连接在任何两个相对节点之间的交叉耦合的锁存器。

96. 发明申请

US20090187794A1 SYSTEM AND METHOD FOR PROVIDING A MEMORY DEVICE HAVING A SHARED ERROR FEEDBACK PIN 有权
标题翻译：用于提供具有共享错误反馈PIN的存储器件的系统和方法
公开(公告)号：US20090187794A1
公开(公告)日：2009-07-23
申请号：US12018030
申请日：2008-01-22
申请人： Kyu-hyoun Kim , Paul W. Coteus , Timothy J. Dell
发明人： Kyu-hyoun Kim , Paul W. Coteus , Timothy J. Dell
IPC分类号： G06F11/00
CPC分类号： G06F11/1004
摘要： A system and method for providing a memory device having a shared error feedback pin. The system includes a memory device having a data interface configured to receive data bits and CRC bits, CRC receiving circuitry, CRC creation circuitry, a memory device pad, and driver circuitry. The CRC receiving circuitry utilizes a CRC equation for the detection of errors in one or more of the received data and the received CRC bits. The CRC creation circuitry utilizes the CRC equation for the creation of CRC bits consistent with data to be transmitted to a separate device bits. The memory device pad is configured for reporting of any errors detected in the received data and the received CRC bits. The driver circuitry is connected to the memory device pad and merged with one or more other driver circuitries resident on one or more other memory devices into an error reporting line.
摘要翻译：一种用于提供具有共享错误反馈引脚的存储器件的系统和方法。该系统包括具有被配置为接收数据比特和CRC比特，CRC接收电路，CRC创建电路，存储器装置垫和驱动器电路的数据接口的存储器装置。 CRC接收电路利用CRC方程来检测一个或多个接收数据和接收的CRC比特中的错误。 CRC创建电路利用CRC方程来创建与要发送到单独设备位的数据一致的CRC位。存储器件焊盘被配置为报告在接收的数据和接收的CRC位中检测到的任何错误。驱动器电路连接到存储器件焊盘并与驻留在一个或多个其它存储器件上的一个或多个其它驱动器电路合并到错误报告行中。

97. 发明授权

US07491067B2 Land grid array (LGA) interposer utilizing metal-on-elastomer hemi-torus and other multiple points of contact geometries 失效
标题翻译：利用金属弹性体半环和其他多点接触几何形式的土地栅格阵列（LGA）插入器
公开(公告)号：US07491067B2
公开(公告)日：2009-02-17
申请号：US11865383
申请日：2007-10-01
申请人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
发明人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
IPC分类号： H01R12/00
CPC分类号： H01R12/714 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H05K3/326 , H05K3/4007 , H05K7/1061 , H05K2201/0133 , H05K2201/0367 , H05K2201/09481 , H05K2201/09745 , H05K2201/10378 , H05K2201/10734 , Y10T29/49002 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49151 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T29/49204 , Y10T29/49208 , Y10T29/49213 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure.
摘要翻译：包括电绝缘载体平面的平面栅格阵列（LGA）插入器结构以及安装在所述载体平面的第一表面上的至少一个插入器。插入件在横截面中具有半环形结构，并由介电弹性体材料构成。多个导电元件围绕至少一个半环形插入器的表面布置并且从其最上端向内和向下自由地延伸至与位于电绝缘载体的相对侧上的至少一个部件的电接触飞机还提供了一种制造焊盘栅格阵列中介层结构的方法。

98. 发明授权

US07488182B2 Land grid array (LGA) interposer structure providing for electrical contacts on opposite sides of a carrier plane 失效
标题翻译：在栅极阵列（LGA）插入器结构中，提供载体平面相对侧上的电接触
公开(公告)号：US07488182B2
公开(公告)日：2009-02-10
申请号：US11865327
申请日：2007-10-01
申请人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
发明人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
IPC分类号： H01R12/00
CPC分类号： H01R12/714 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H05K3/326 , H05K3/4007 , H05K7/1061 , H05K2201/0133 , H05K2201/0367 , H05K2201/09481 , H05K2201/09745 , H05K2201/10378 , H05K2201/10734 , Y10T29/49002 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49151 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T29/49204 , Y10T29/49208 , Y10T29/49213 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure.
摘要翻译：包括电绝缘载体平面的平面栅格阵列（LGA）插入器结构以及安装在所述载体平面的第一表面上的至少一个插入器。插入件在横截面中具有半环形结构，并由介电弹性体材料构成。多个导电元件围绕至少一个半环形插入器的表面布置并且从其最上端向内和向下自由地延伸至与位于电绝缘载体的相对侧上的至少一个部件的电接触飞机还提供了一种制造焊盘栅格阵列中介层结构的方法。

99. 发明授权

US07484966B2 Land grid array (LGA) interposer utilizing metal-on-elastomer hemi-torus and other multiple points of contact geometries 失效
公开(公告)号：US07484966B2
公开(公告)日：2009-02-03
申请号：US11865458
申请日：2007-10-01
申请人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
发明人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
IPC分类号： H01R12/00
CPC分类号： H01R12/714 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H05K3/326 , H05K3/4007 , H05K7/1061 , H05K2201/0133 , H05K2201/0367 , H05K2201/09481 , H05K2201/09745 , H05K2201/10378 , H05K2201/10734 , Y10T29/49002 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49151 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T29/49204 , Y10T29/49208 , Y10T29/49213 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure.

100. 发明申请

US20080215790A1 Memory systems for automated computing machinery 失效
标题翻译：自动计算机的存储系统
公开(公告)号：US20080215790A1
公开(公告)日：2008-09-04
申请号：US12102034
申请日：2008-04-14
申请人： Paul W. Coteus , Kevin C. Gower , Robert B. Tremaine
发明人： Paul W. Coteus , Kevin C. Gower , Robert B. Tremaine
IPC分类号： G06F13/36
CPC分类号： G06F13/1684 , Y02D10/14
摘要： Design structures embodied in machine readable medium are provided. Embodiments of the design structure include a memory system comprising: a memory controller; a memory bus terminator; a high speed memory bus that interconnects the memory controller, the memory bus terminator, and at least one memory module; and the at least one memory module, the memory module comprising at least one memory hub device, high speed random access memory served by the memory hub device, two bus signal ports, and a segment of the high speed memory bus fabricated on the memory module so as to interconnect the bus signal ports and the memory hub device, the high speed memory bus connected to the memory hub device by a negligible electrical stub.
摘要翻译：提供体现在机器可读介质中的设计结构。设计结构的实施例包括存储器系统，包括：存储器控制器; 一个内存总线终端; 将存储器控制器，存储器总线终端器和至少一个存储器模块互连的高速存储器总线; 和所述至少一个存储器模块，所述存储器模块包括至少一个存储器集线器设备，由所述存储器集线器设备服务的高速随机存取存储器，两个总线信号端口以及在所述存储器模块上制造的所述高速存储器总线的段以便将总线信号端口和存储器集线器设备互连，高速存储器总线通过可忽略的电接头连接到存储器集线器设备。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式