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91. 发明授权

US07129169B2 Method for controlling voiding and bridging in silicide formation 有权
标题翻译：控制硅化物形成中孔隙和桥接的方法
公开(公告)号：US07129169B2
公开(公告)日：2006-10-31
申请号：US10709534
申请日：2004-05-12
申请人： Bradley P. Jones , Christian Lavoie , Robert J. Purtell , Yun-Yu Wang , Keith Kwong Hon Wong
发明人： Bradley P. Jones , Christian Lavoie , Robert J. Purtell , Yun-Yu Wang , Keith Kwong Hon Wong
IPC分类号： H01L21/44 , H01L21/3205
CPC分类号： H01L29/665 , H01L21/28518 , H01L29/7833
摘要： A method for forming a metal silicide contact for a semiconductor device includes forming a refractory metal layer over a substrate, including active and non-active area of said substrate, and forming a cap layer over the refractory metal layer. A counter tensile layer is formed over the cap layer, wherein the counter tensile layer is selected from a material such that an opposing directional stress is created between the counter tensile layer and the cap layer, with respect to a directional stress created between the refractory metal layer and the cap layer.
摘要翻译：一种用于形成用于半导体器件的金属硅化物接触的方法包括在衬底上形成难熔金属层，该衬底包括所述衬底的有源区和非有源区，并在难熔金属层上形成覆盖层。反面拉伸层形成在覆盖层上方，其中相对抗拉层选自材料，使得在相对拉伸层和盖层之间产生相对的方向应力，相对于难熔金属之间产生的方向应力层和盖层。

92. 发明授权

US06896784B2 Method for controlling local current to achieve uniform plating thickness 失效
标题翻译：控制局部电流达到均匀电镀厚度的方法
公开(公告)号：US06896784B2
公开(公告)日：2005-05-24
申请号：US10868723
申请日：2004-06-15
申请人： Tien-Jen Cheng , Todd M. Fowler , Ajay P. Giri , Anton Nenadic , Blessen Samuel , Keith Kwong Hon Wong
发明人： Tien-Jen Cheng , Todd M. Fowler , Ajay P. Giri , Anton Nenadic , Blessen Samuel , Keith Kwong Hon Wong
IPC分类号： C25D7/12 , C25D5/00 , C25D5/02 , C25D17/10 , C25D17/12 , C25D21/12 , H01L21/288 , H05K3/24
CPC分类号： H01L21/2885 , C25D5/02 , C25D17/001 , C25D17/007 , C25D17/10 , C25D17/12 , H05K3/241
摘要： A process for electroplating metallic features of different density on a surface of a substrate comprises providing an electroplating bath having an anode, immersing the substrate into the electroplating bath, spaced from the anode, the substrate comprising a cathode. Positioned in the electroplating bath between the substrate and the anode, and adjacent to and separated from the substrate surface is a second cathode that includes a wire mesh screening portion having openings of different sizes conforming to the metallic features to be electroplated. The second cathode screening portion has openings of larger size adjacent areas of higher density of features to be electroplated and openings of smaller size adjacent areas of lower density of features to be electroplated. The process further includes impressing a current through the electroplating bath between the substrate and the anode, and between the second cathode and the anode, and electroplating the metallic features of different density onto the substrate.
摘要翻译：一种用于在基片表面上电镀不同密度的金属特征的方法包括提供具有阳极的电镀浴，将基底浸入与阳极间隔开的电镀浴中，该基底包括阴极。位于基板和阳极之间并且与基板表面相邻并与基板表面分离的电镀槽中的电镀槽是包括具有不同尺寸的开口的金属丝网筛分部分的第二阴极，其符合要电镀的金属特征。第二阴极屏蔽部分具有较大尺寸的具有更高密度特征的相邻区域的开口，以进行电镀，并且要电镀较低密度特征的较小尺寸的相邻区域的开口。该方法进一步包括通过电镀浴在基板和阳极之间以及在第二阴极和阳极之间施加电流，并将不同密度的金属特征电镀到基板上。

93. 发明授权

US06700203B1 Semiconductor structure having in-situ formed unit resistors 有权
标题翻译：具有原位形成单元电阻器的半导体结构
公开(公告)号：US06700203B1
公开(公告)日：2004-03-02
申请号：US09686742
申请日：2000-10-11
申请人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Lu-Chen Hsu , Keith Kwong Hon Wong
发明人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Lu-Chen Hsu , Keith Kwong Hon Wong
IPC分类号： H01L2348
CPC分类号： H01L28/20 , H01L27/0688
摘要： An electronic structure that has in-situ formed unit resistors and a method for fabricating such structure are disclosed. The electronic structure that has in-situ formed unit resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The present invention novel structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The present invention novel structure may further be combined with a capacitor network to form desirable RC circuits.
摘要翻译：公开了一种具有原位形成的单位电阻器的电子结构及其制造方法。具有原位形成的单元电阻器的电子结构由形成在绝缘材料层中的第一多个导电元件组成，多个电阻通孔形成在顶部并与第一多个导电元件中的至少一个电连通以及形成在所述多个电阻通孔中的至少一个上方并与之电气连通的第二多个导电元件。本发明的新颖结构可以进一步形成为多电平配置，使得多电平电阻器可以串联连接以提供更大的电阻值。本发明的新颖结构还可以与电容器网络组合以形成期望的RC电路。

94. 发明授权

US09017486B2 Deposition chamber cleaning method including stressed cleaning layer 有权
公开(公告)号：US09017486B2
公开(公告)日：2015-04-28
申请号：US12878128
申请日：2010-09-09
申请人： Tien-Jen Cheng , Zhengwen Li , Keith Kwong Hon Wong
发明人： Tien-Jen Cheng , Zhengwen Li , Keith Kwong Hon Wong
IPC分类号： B08B7/00 , B08B7/04 , C23C16/44 , C23C14/34
CPC分类号： B08B7/04 , B08B7/0014 , C23C14/34 , C23C16/4404
摘要： A method for cleaning a deposition chamber includes forming a deposited layer over an interior surface of the deposition chamber, wherein the deposited layer has a deposited layer stress and a deposited layer modulus; forming a cleaning layer over the deposited layer, wherein a material comprising the cleaning layer is selected such that the cleaning layer adheres to the deposited layer, and has a cleaning layer stress and a cleaning layer modulus, wherein the cleaning layer stress is higher than the deposited layer stress, and wherein the cleaning layer modulus is higher than the deposited layer modulus; and removing the deposited layer and the cleaning layer from the interior of the deposition chamber.

95. 发明授权

US08916435B2 Self-aligned bottom plate for metal high-K dielectric metal insulator metal (MIM) embedded dynamic random access memory 有权
标题翻译：用于金属高K绝缘子金属（MIM）嵌入式动态随机存取存储器的自对准底板
公开(公告)号：US08916435B2
公开(公告)日：2014-12-23
申请号：US13228767
申请日：2011-09-09
申请人： Zhengwen Li , Damon B. Farmer , Michael P. Chudzik , Keith Kwong Hon Wong , Jian Yu , Zhen Zhang , Chengwen Pei
发明人： Zhengwen Li , Damon B. Farmer , Michael P. Chudzik , Keith Kwong Hon Wong , Jian Yu , Zhen Zhang , Chengwen Pei
IPC分类号： H01L21/8242 , H01L27/12 , H01L27/108 , H01L49/02 , H01L21/84 , H01L29/94
CPC分类号： H01L27/10829 , H01L21/84 , H01L27/10861 , H01L27/1203 , H01L28/91 , H01L29/945
摘要： A memory device, and a method of forming a memory device, is provided that includes a capacitor with a lower electrode of a metal semiconductor alloy. In one embodiment, the memory device includes a trench present in a semiconductor substrate including a semiconductor on insulating (SOI) layer on top of a buried dielectric layer, wherein the buried dielectric layer is on top of a base semiconductor layer. A capacitor is present in the trench, wherein the capacitor includes a lower electrode of a metal semiconductor alloy having an upper edge that is self-aligned to the upper surface of the base semiconductor layer, a high-k dielectric node layer, and an upper electrode of a metal. The memory device further includes a pass transistor in electrical communication with the capacitor.
摘要翻译：提供一种存储器件和形成存储器件的方法，其包括具有金属半导体合金的下电极的电容器。在一个实施例中，存储器件包括存在于半导体衬底中的沟槽，其包括在掩埋介电层顶部上的绝缘（SOI）半导体层，其中所述掩埋介电层位于基底半导体层的顶部。电容器存在于沟槽中，其中电容器包括金属半导体合金的下电极，其具有与基底半导体层的上表面自对准的上边缘，高k电介质节点层和上层金属电极。存储器件还包括与电容器电连通的传输晶体管。

96. 发明申请

US20130328167A1 SELF-ALIGNED METAL-INSULATOR-METAL (MIM) CAPACITOR 审中-公开
标题翻译：自对准金属绝缘子 - 金属（MIM）电容器
公开(公告)号：US20130328167A1
公开(公告)日：2013-12-12
申请号：US13489940
申请日：2012-06-06
申请人： Chih-Chao Yang , Daniel C. Edelstein , Baozhen Li , Keith Kwong Hon Wong
发明人： Chih-Chao Yang , Daniel C. Edelstein , Baozhen Li , Keith Kwong Hon Wong
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/75 , H01L23/5223 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： A metal-insulator-metal (MIM) capacitor structure integrated within a back-end-of-the-line (BEOL) structure is provided. The MIM capacitor structure includes a lower electrode, i.e., a first conductive material, embedded within a dielectric material of the BEOL structure, a dielectric material liner having a dielectric constant of equal to, or greater than, silicon dioxide located atop the lower electrode, and an upper electrode, i.e., a second conductive material, positioned between vertical portions of the dielectric material liner and atop a horizontal connecting portion of the dielectric material liner. In accordance with the present disclosure, the vertical portions of the dielectric material liner do not extend onto an upper surface of the dielectric material that includes the lower electrode.
摘要翻译：提供集成在后端（BEOL）结构中的金属 - 绝缘体 - 金属（MIM）电容器结构。 MIM电容器结构包括嵌入在BEOL结构的电介质材料中的下电极，即第一导电材料，具有等于或大于位于下电极顶部的二氧化硅的介电常数的介电材料衬垫，以及位于电介质材料衬垫的垂直部分之间并且位于介电材料衬里的水平连接部分顶部的上电极，即第二导电材料。根据本公开，电介质材料衬垫的垂直部分不延伸到包括下电极的电介质材料的上表面上。

97. 发明授权

US08546211B2 Replacement gate having work function at valence band edge 有权
公开(公告)号：US08546211B2
公开(公告)日：2013-10-01
申请号：US12948031
申请日：2010-11-17
申请人： Keith Kwong Hon Wong , Michael P. Chudzik , Unoh Kwon
发明人： Keith Kwong Hon Wong , Michael P. Chudzik , Unoh Kwon
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L29/165 , H01L29/4966 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7843 , H01L29/7848
摘要： Replacement gate stacks are provided, which increase the work function of the gate electrode of a p-type field effect transistor (PFET). In one embodiment, the work function metal stack includes a titanium-oxide-nitride layer located between a lower titanium nitride layer and an upper titanium nitride layer. The stack of the lower titanium nitride layer, the titanium-oxide-nitride layer, and the upper titanium nitride layer produces the unexpected result of increasing the work function of the work function metal stack significantly. In another embodiment, the work function metal stack includes an aluminum layer deposited at a temperature not greater than 420° C. The aluminum layer deposited at a temperature not greater than 420° C. produces the unexpected result of increasing the work function of the work function metal stack significantly.

98. 发明授权

US08368070B2 Antifuse structure for in line circuit modification 有权
公开(公告)号：US08368070B2
公开(公告)日：2013-02-05
申请号：US13360277
申请日：2012-01-27
申请人： Terence L. Kane , Michael P. Tenney , Yun-Yu Wang , Keith Kwong Hon Wong
发明人： Terence L. Kane , Michael P. Tenney , Yun-Yu Wang , Keith Kwong Hon Wong
IPC分类号： H01L29/04 , H01L31/036
CPC分类号： H01L23/5252 , H01L21/76823 , H01L21/76843 , H01L2924/0002 , H01L2924/00
摘要： An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material.

99. 发明申请

US20120306015A1 CONTACTS FOR FET DEVICES 审中-公开
标题翻译： FET器件的接触
公开(公告)号：US20120306015A1
公开(公告)日：2012-12-06
申请号：US13562355
申请日：2012-07-31
申请人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong , Ying Zhang
IPC分类号： H01L29/78
CPC分类号： H01L29/41733 , H01L21/28518 , H01L23/485 , H01L29/665 , H01L29/66772 , H01L2924/0002 , H01L2924/00
摘要： A device characterized as being an FET device structure with enlarged contact areas is disclosed. The device has a vertically recessed isolation, thereby having an exposed sidewall surface on both the source and the drain. A silicide layer is covering both the top surface and the sidewall surface of both the source and the drain. Metallic contacts to the device engage the silicide layer on its top surface and on its sidewall surface.
摘要翻译：公开了一种特征在于具有扩大的接触面积的FET器件结构的器件。该装置具有垂直凹入的隔离，从而在源极和漏极两者上具有暴露的侧壁表面。硅化物层覆盖源极和漏极的顶表面和侧壁表面。与设备的金属接触物接合在其顶表面及其侧壁表面上的硅化物层。

100. 发明申请

US20120267685A1 METAL GATE AND HIGH-K DIELECTRIC DEVICES WITH PFET CHANNEL SiGe 有权
标题翻译：具有PFET通道SiGe的金属栅极和高K介质器件
公开(公告)号：US20120267685A1
公开(公告)日：2012-10-25
申请号：US13539700
申请日：2012-07-02
申请人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong
发明人： Kangguo Cheng , Bruce B. Doris , Keith Kwong Hon Wong
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/823842 , H01L21/823857
摘要： In a circuit structure, PFET devices have a gate dielectric including a high-k dielectric, a gatestack with a metal, a p-source/drain and silicide layer formed over the p-source/drain; NFET devices include a gate dielectric including a high-k dielectric, a gatestack with a metal, an n-source/drain and silicide layer formed over the n-source/drain. An epitaxial SiGe is present underneath and in direct contact with the PFET gate dielectric, while the epitaxial SiGe is absent underneath the NFET gate dielectric.
摘要翻译：在电路结构中，PFET器件具有栅极电介质，其包括高k电介质，具有金属的栅格，p源极/漏极和形成在p源极/漏极上的硅化物层; NFET器件包括栅极电介质，其包括高k电介质，具有金属的盖板，在n源极/漏极上形成的n源极/漏极和硅化物层。外延SiGe存在于PFET栅极电介质的下面并与PFET栅极电介质直接接触，而外延SiGe不存在于NFET栅极电介质下方。

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