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91. 发明申请

US20130241031A1 PROGRAMMABLE FUSE STRUCTURE AND METHODS OF FORMING 有权
标题翻译：可编程熔丝结构和形成方法
公开(公告)号：US20130241031A1
公开(公告)日：2013-09-19
申请号：US13419877
申请日：2012-03-14
申请人： Yan Zun Li , Zhengwen Li , Chengwen Pei , Jian Yu
发明人： Yan Zun Li , Zhengwen Li , Chengwen Pei , Jian Yu
IPC分类号： H01L23/525 , H01L21/44
CPC分类号： H01L23/5256 , H01L23/53204 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming an electrically programmable fuse (e-fuse) structure and the e-fuse structure are disclosed. Various embodiments of forming the e-fuse structure include: forming a dummy poly gate structure to contact a surface of a silicon structure, the dummy poly gate structure extending only a part of a length of the silicon structure; and converting an unobstructed portion of the surface of the silicon structure to silicide to form a thinned strip of the silicide between two end regions.
摘要翻译：公开了形成电可编程熔丝（e熔丝）结构和电熔体结构的方法。形成e熔丝结构的各种实施例包括：形成虚拟多晶硅结构以接触硅结构的表面，所述虚设多晶硅结构仅延伸所述硅结构的长度的一部分; 以及将所述硅结构的表面的无障碍部分转化为硅化物以在两个端部区域之间形成所述硅化物的薄化带。

92. 发明授权

US08420476B2 Integrated circuit with finFETs and MIM fin capacitor 有权
标题翻译：集成电路与finFET和MIM鳍电容器
公开(公告)号：US08420476B2
公开(公告)日：2013-04-16
申请号：US12789013
申请日：2010-05-27
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Toshiharu Furukawa , Chengwen Pei
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Toshiharu Furukawa , Chengwen Pei
IPC分类号： H01L21/8238
CPC分类号： H01L27/0629 , H01L21/823821 , H01L21/823842 , H01L21/823857 , H01L21/845 , H01L27/1211 , H01L28/91
摘要： An integrated circuit having finFETs and a metal-insulator-metal (MIM) fin capacitor and methods of manufacture are disclosed. A method includes forming a first finFET comprising a first dielectric and a first conductor; forming a second finFET comprising a second dielectric and a second conductor; and forming a fin capacitor comprising the first conductor, the second dielectric, and the second conductor.
摘要翻译：公开了一种具有finFET和金属 - 绝缘体 - 金属（MIM）鳍片电容器及其制造方法的集成电路。一种方法包括形成包括第一电介质和第一导体的第一finFET; 形成包括第二电介质和第二导体的第二finFET; 以及形成包括所述第一导体，所述第二电介质和所述第二导体的散热片电容器。

93. 发明申请

US20130062677A1 SELF-ALIGNED BOTTOM PLATE FOR METAL HIGH-K DIELECTRIC METAL INSULATOR METAL (MIM) EMBEDDED DYNAMIC RANDOM ACCESS MEMORY 有权
标题翻译：用于金属高K介电金属绝缘体金属（MIM）嵌入式动态随机存取存储器的自对准底板
公开(公告)号：US20130062677A1
公开(公告)日：2013-03-14
申请号：US13228767
申请日：2011-09-09
申请人： Zhengwen Li , Damon B. Farmer , Michael P. Chudzik , Keith Kwong Hon Wong , Jian Yu , Zhen Zhang , Chengwen Pei
发明人： Zhengwen Li , Damon B. Farmer , Michael P. Chudzik , Keith Kwong Hon Wong , Jian Yu , Zhen Zhang , Chengwen Pei
IPC分类号： H01L21/20 , H01L27/06
CPC分类号： H01L27/10829 , H01L21/84 , H01L27/10861 , H01L27/1203 , H01L28/91 , H01L29/945
摘要： A memory device, and a method of forming a memory device, is provided that includes a capacitor with a lower electrode of a metal semiconductor alloy. In one embodiment, the memory device includes a trench present in a semiconductor substrate including a semiconductor on insulating (SOI) layer on top of a buried dielectric layer, wherein the buried dielectric layer is on top of a base semiconductor layer. A capacitor is present in the trench, wherein the capacitor includes a lower electrode of a metal semiconductor alloy having an upper edge that is self-aligned to the upper surface of the base semiconductor layer, a high-k dielectric node layer, and an upper electrode of a metal. The memory device further includes a pass transistor in electrical communication with the capacitor.
摘要翻译：提供一种存储器件和形成存储器件的方法，其包括具有金属半导体合金的下电极的电容器。在一个实施例中，存储器件包括存在于半导体衬底中的沟槽，其包括在掩埋介电层顶部上的绝缘（SOI）半导体层，其中所述掩埋介电层位于基底半导体层的顶部。电容器存在于沟槽中，其中电容器包括金属半导体合金的下电极，其具有与基底半导体层的上表面自对准的上边缘，高k电介质节点层和上层金属电极。存储器件还包括与电容器电连通的传输晶体管。

94. 发明授权

US08384145B2 Non-volatile memory device using hot-carrier injection 有权
标题翻译：使用热载流子注入的非易失性存储器件
公开(公告)号：US08384145B2
公开(公告)日：2013-02-26
申请号：US12692923
申请日：2010-01-25
申请人： Roger Allen Booth, Jr. , Kangguo Cheng , Chandrasekharan Kothandaraman , Chengwen Pei
发明人： Roger Allen Booth, Jr. , Kangguo Cheng , Chandrasekharan Kothandaraman , Chengwen Pei
IPC分类号： H01L29/76
CPC分类号： H01L29/7923 , H01L29/66833
摘要： Each of a hot-carrier non-volatile memory device and a method for fabricating the hot carrier non-volatile memory device is predicated upon a semiconductor structure and related method that includes a metal oxide semiconductor field effect transistor structure. The semiconductor structure and related method include at least one of: (1) a spacer that comprises a dielectric material having a dielectric constant greater than 7 (for enhanced hot carrier derived charge capture and retention); and (2) a drain region that comprises a semiconductor material that has a narrower bandgap than a bandgap of a semiconductor material from which is comprised a channel region (for enhanced impact ionization and charged carrier generation).
摘要翻译：热载体非易失性存储器件和用于制造热载体非易失性存储器件的方法中的每一种都取决于包括金属氧化物半导体场效应晶体管结构的半导体结构和相关方法。半导体结构和相关方法包括以下中的至少一个：（1）包括介电常数大于7的介电材料的间隔物（用于增强热载体导电的电荷捕获和保留）; 和（2）包括半导体材料的漏极区，该半导体材料具有比半导体材料的带隙窄的带隙，其包括沟道区（用于增强的冲击电离和带电载流子的生成）。

95. 发明授权

US07759766B2 Electrical fuse having a thin fuselink 失效
标题翻译：电熔丝具有薄的熔丝
公开(公告)号：US07759766B2
公开(公告)日：2010-07-20
申请号：US11843047
申请日：2007-08-22
申请人： Roger A. Booth, Jr. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
发明人： Roger A. Booth, Jr. , MaryJane Brodsky , Kangguo Cheng , Chengwen Pei
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A thin semiconductor layer is formed and patterned on a semiconductor substrate to form a thin semiconductor fuselink on shallow trench isolation and between an anode semiconductor region and a cathode semiconductor region. During metallization, the semiconductor fuselink is converted to a thin metal semiconductor alloy fuselink as all of the semiconductor material in the semiconductor fuselink reacts with a metal to form a metal semiconductor alloy. The inventive electrical fuse comprises the thin metal semiconductor alloy fuselink, a metal semiconductor alloy anode, and a metal semiconductor alloy cathode. The thin metal semiconductor alloy fuselink has a smaller cross-sectional area compared with prior art electrical fuses. Current density within the fuselink and the divergence of current at the interface between the fuselink and the cathode or anode comparable to prior art electrical fuses are obtained with less programming current than prior art electrical fuses.
摘要翻译：薄半导体层在半导体衬底上形成并图案化以在浅沟槽隔离上以及在阳极半导体区域和阴极半导体区域之间形成薄的半导体熔丝。在金属化期间，由于半导体软管中的所有半导体材料与金属反应而形成金属半导体合金，所以将半导体熔融金属转换为薄金属半导体合金熔丝。本发明的电熔丝包括薄金属半导体合金熔丝，金属半导体合金阳极和金属半导体合金阴极。与现有技术的电熔丝相比，薄金属半导体合金熔体具有较小的横截面积。与现有技术的电熔丝相比，可以获得与现有技术的电熔丝相当的在熔丝中的电流密度和在熔丝与阴极或阳极之间的界面处的电流发散度，而不是现有技术的电熔丝。

96. 发明授权

US08916435B2 Self-aligned bottom plate for metal high-K dielectric metal insulator metal (MIM) embedded dynamic random access memory 有权
标题翻译：用于金属高K绝缘子金属（MIM）嵌入式动态随机存取存储器的自对准底板
公开(公告)号：US08916435B2
公开(公告)日：2014-12-23
申请号：US13228767
申请日：2011-09-09
申请人： Zhengwen Li , Damon B. Farmer , Michael P. Chudzik , Keith Kwong Hon Wong , Jian Yu , Zhen Zhang , Chengwen Pei
发明人： Zhengwen Li , Damon B. Farmer , Michael P. Chudzik , Keith Kwong Hon Wong , Jian Yu , Zhen Zhang , Chengwen Pei
IPC分类号： H01L21/8242 , H01L27/12 , H01L27/108 , H01L49/02 , H01L21/84 , H01L29/94
CPC分类号： H01L27/10829 , H01L21/84 , H01L27/10861 , H01L27/1203 , H01L28/91 , H01L29/945
摘要： A memory device, and a method of forming a memory device, is provided that includes a capacitor with a lower electrode of a metal semiconductor alloy. In one embodiment, the memory device includes a trench present in a semiconductor substrate including a semiconductor on insulating (SOI) layer on top of a buried dielectric layer, wherein the buried dielectric layer is on top of a base semiconductor layer. A capacitor is present in the trench, wherein the capacitor includes a lower electrode of a metal semiconductor alloy having an upper edge that is self-aligned to the upper surface of the base semiconductor layer, a high-k dielectric node layer, and an upper electrode of a metal. The memory device further includes a pass transistor in electrical communication with the capacitor.
摘要翻译：提供一种存储器件和形成存储器件的方法，其包括具有金属半导体合金的下电极的电容器。在一个实施例中，存储器件包括存在于半导体衬底中的沟槽，其包括在掩埋介电层顶部上的绝缘（SOI）半导体层，其中所述掩埋介电层位于基底半导体层的顶部。电容器存在于沟槽中，其中电容器包括金属半导体合金的下电极，其具有与基底半导体层的上表面自对准的上边缘，高k电介质节点层和上层金属电极。存储器件还包括与电容器电连通的传输晶体管。

97. 发明授权

US08896088B2 Reliable electrical fuse with localized programming 有权
标题翻译：可靠的电熔丝与本地编程
公开(公告)号：US08896088B2
公开(公告)日：2014-11-25
申请号：US13095164
申请日：2011-04-27
申请人： Yan Zun Li , Zhengwen Li , Chengwen Pei , Jian Yu
发明人： Yan Zun Li , Zhengwen Li , Chengwen Pei , Jian Yu
IPC分类号： H01L23/52 , H01L21/82 , H01L21/84 , H01L23/525 , H01L27/12 , G11C17/16
CPC分类号： H01L23/62 , G11C17/16 , H01L21/02532 , H01L21/28518 , H01L21/76886 , H01L21/823814 , H01L21/84 , H01L23/5256 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： An electrical fuse has an anode contact on a surface of a semiconductor substrate. The electrical fuse has a cathode contact on the surface of the semiconductor substrate spaced from the anode contact. The electrical fuse has a link within the substrate electrically interconnecting the anode contact and the cathode contact. The link comprises a semiconductor layer and a silicide layer. The silicide layer extends beyond the anode contact. An opposite end of the silicide layer extends beyond the cathode contact. A silicon germanium region is embedded in the semiconductor layer under the silicide layer, between the anode contact and the cathode contact.
摘要翻译：电熔丝在半导体衬底的表面上具有阳极接触。电熔丝在半导体衬底的与阳极接触件间隔开的表面上具有阴极接触。电熔丝在衬底内具有连接阳极接触件和阴极接触件的连接。该连接件包括半导体层和硅化物层。硅化物层延伸超过阳极接触。硅化物层的另一端延伸超过阴极接触。在硅化物层之下的阳极接触和阴极接触之间的半导体层中嵌入硅锗区。

98. 发明授权

US08481397B2 Polysilicon resistor and E-fuse for integration with metal gate and high-k dielectric 有权
标题翻译：用于与金属栅极和高k电介质集成的多晶硅电阻器和电熔丝
公开(公告)号：US08481397B2
公开(公告)日：2013-07-09
申请号：US12719289
申请日：2010-03-08
申请人： Roger A. Booth, Jr. , Kangguo Cheng , Rainer Loesing , Chengwen Pei , Xiaojun Yu
发明人： Roger A. Booth, Jr. , Kangguo Cheng , Rainer Loesing , Chengwen Pei , Xiaojun Yu
IPC分类号： H01L21/20
CPC分类号： H01L21/02 , H01L21/768 , H01L23/525 , H01L29/12 , H01L29/86 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for making a resistive polycrystalline semiconductor device, e.g., a poly resistor of a microelectronic element such as a semiconductor integrated circuit. The method can include: (a) forming a layered stack including a dielectric layer contacting a surface of a monocrystalline semiconductor region of a substrate, a metal gate layer overlying the dielectric layer, a first polycrystalline semiconductor region adjacent the metal gate layer having a predominant dopant type of either n or p, and a second polycrystalline semiconductor region spaced from the metal gate layer by the first polycrystalline semiconductor region and adjoining the first polycrystalline semiconductor region; and (b) forming first and second contacts in conductive communication with the second polycrystalline semiconductor region, the first and second contacts being spaced apart so as to achieve a desired resistance. In a variation thereof, an electrical fuse is formed which includes a continuous silicide region through which a current can be passed to blow the fuse. Some of the steps of fabricating the poly resistor or the electrical fuse can be employed simultaneously in fabricating metal gate field effect transistors (FETs) on the same substrate.
摘要翻译：提供了一种用于制造电阻性多晶半导体器件的方法，例如诸如半导体集成电路的微电子元件的多晶硅电阻器。该方法可以包括：（a）形成层叠堆叠，其包括与衬底的单晶半导体区域的表面接触的电介质层，覆盖在电介质层上的金属栅极层，与金属栅极层相邻的第一多晶半导体区域，掺杂剂类型的n或p，以及第二多晶半导体区域，其与所述第一多晶半导体区域与所述金属栅极层隔开并邻接所述第一多晶半导体区域; 和（b）形成与所述第二多晶半导体区域导电连通的第一和第二触点，所述第一和第二触点间隔开以达到期望的电阻。在其变型中，形成电熔丝，其包括连续的硅化物区域，电流可以通过该硅化物区域通过以熔断熔丝。在同一衬底上制造金属栅极场效应晶体管（FET）的同时可以同时采用制造多晶硅电阻器或电熔丝的步骤。

99. 发明申请

US20130099354A1 CAPACITOR WITH DEEP TRENCH ION IMPLANTATION 失效
标题翻译：电容器与深层离子植入
公开(公告)号：US20130099354A1
公开(公告)日：2013-04-25
申请号：US13279877
申请日：2011-10-24
申请人： Chengwen Pei , Roger Allen Booth, JR. , Herbert Lei Ho , Naoyoshi Kusaba
发明人： Chengwen Pei , Roger Allen Booth, JR. , Herbert Lei Ho , Naoyoshi Kusaba
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L29/945 , H01L29/66181
摘要： An improved semiconductor capacitor and method of fabrication is disclosed. Embodiments utilize a deep trench which is then processed by performing a pre-amorphous implant on the trench interior to transform the interior surface of the trench to amorphous silicon which eliminates the depletion region that can degrade capacitor performance.
摘要翻译：公开了一种改进的半导体电容器和制造方法。实施例利用深沟槽，然后通过在沟槽内部执行预非晶体植入来将沟槽的内表面转变为非晶硅来处理，以消除可能降低电容器性能的耗尽区。

100. 发明申请

US20120184073A1 PROGRAMMABLE HIGH-K/METAL GATE MEMORY DEVICE 有权
标题翻译：可编程高K /金属栅存储器件
公开(公告)号：US20120184073A1
公开(公告)日：2012-07-19
申请号：US13433423
申请日：2012-03-29
申请人： Roger A. Booth, JR. , Kangguo Cheng , Chandrasekharan Kothandaraman , Chengwen Pei
发明人： Roger A. Booth, JR. , Kangguo Cheng , Chandrasekharan Kothandaraman , Chengwen Pei
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L21/28282 , H01L21/823462 , H01L21/823468 , H01L27/1052 , H01L27/11573 , H01L29/4234 , H01L29/4983 , H01L29/517 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A method of fabricating a memory device is provided that may begin with forming a layered gate stack atop a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second metal gate electrode on the semiconductor substrate. In a next process sequence, at least one spacer is formed on the first metal gate electrode atop a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode.
摘要翻译：提供一种制造存储器件的方法，其可以开始于在半导体衬底顶上形成分层栅极堆叠并且图案化停止在层状栅叠层的高k栅极电介质层上的金属电极层，以提供第一金属栅电极和半导体衬底上的第二金属栅电极。在下一个处理顺序中，在第一金属栅电极的高k栅介质层的一部分顶上形成至少一个间隔物，其中高k栅极电介质的剩余部分被暴露。蚀刻高k栅极电介质层的剩余部分以提供具有延伸超过第一金属栅电极的侧壁的部分的第一高k栅极电介质和具有对准边缘的第二高k栅极电介质到第二金属栅电极的侧壁。

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