专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US07061308B2 Voltage divider for integrated circuits 失效
标题翻译：用于集成电路的分压器
公开(公告)号：US07061308B2
公开(公告)日：2006-06-13
申请号：US10605466
申请日：2003-10-01
申请人： Wagdi W. Abadeer , John A. Fifield , William R. Tonti
发明人： Wagdi W. Abadeer , John A. Fifield , William R. Tonti
IPC分类号： G05F3/02
CPC分类号： G11C5/147 , H01L27/0802 , H01L27/088 , H02M3/00
摘要： A voltage divider for integrated circuits that does not include the use of resistors. In one embodiment, voltage node VDD is connected with two n-type transistors, NFET1 and NFET2, which are connected in series. NFET 1 includes a source (12), a drain (14), a gate electrode (16) having a gate area A1 (not shown), and a p-substrate (18). NFET2 includes a source (20), a drain (22), a gate electrode (24) having a gate area A2 (not shown), and a p-substrate (26). Source (12) and drain (14) of NFET1 are coupled with gate electrode (24) of NFET2. The voltage difference between NFET1 and NFET2 has a linear function with VDD. As a result, voltage VDD may be divided between NFET1 and NFET2 by properly choosing the ratio between each of the respective transistor gate electrode areas, (A1) and (A2).
摘要翻译：用于集成电路的分压器，不包括使用电阻器。在一个实施例中，电压节点VDD与串联连接的两个n型晶体管NFET 1和NFET 2连接。 NFET 1包括源极（12），漏极（14），具有栅极区域A 1（未示出）的栅电极（16）和p-衬底（18）。 NFET2包括源极（20），漏极（22），具有栅极区域A 2（未示出）的栅电极（24）和p基板（26）。 NFET 1的源极（12）和漏极（14）与NFET2的栅电极（24）耦合。 NFET 1和NFET 2之间的电压差与VDD具有线性关系。结果，通过适当地选择各个晶体管栅电极区域（A 1）和（A 2）之间的比率，可以在NFET 1和NFET 2之间划分电压VDD。

92. 发明授权

US06697293B2 Localized direct sense architecture 有权
标题翻译：本地化的直觉架构
公开(公告)号：US06697293B2
公开(公告)日：2004-02-24
申请号：US10063329
申请日：2002-04-12
申请人： Ciaran J. Brennan , John A. Fifield
发明人： Ciaran J. Brennan , John A. Fifield
IPC分类号： G11C706
CPC分类号： G11C7/065 , G11C7/06 , G11C7/18
摘要： A localized direct sense architecture circuit includes a large number (e.g. 8) of microcells, each having a primary sense amp PSA, coupled to one global data line which is coupled to one secondary sense amp SSA. Each PSA includes its own bias current device, which supplies bias current to sense devices in the PSA and is also used for precharge, such that the bias current does not flow along the highly capacitive global data line. With this technical approach, the size of each bias current supply device can be substantially reduced, and the number of PSAs on one global data line can be increased for increased layout density.
摘要翻译：本地化直接感知架构电路包括大量（例如8个）微小区，每个微小区具有耦合到一个全局数据线的主感测放大器PSA，耦合到一个次级感测放大器SSA。每个PSA包括其自己的偏置电流器件，其提供偏置电流以感测PSA中的器件，并且还用于预充电，使得偏置电流不沿着高电容全局数据线流动。通过这种技术方法，可以显着减少每个偏置电流供应装置的尺寸，并且可以增加一个全局数据线上的PSA数量以增加布局密度。

93. 发明授权

US06667633B2 Multiple finger off chip driver (OCD) with single level translator 失效
公开(公告)号：US06667633B2
公开(公告)日：2003-12-23
申请号：US10093784
申请日：2002-03-07
申请人： John A. Fifield , Wolfgang Hokenmaier
发明人： John A. Fifield , Wolfgang Hokenmaier
IPC分类号： H03K19003
CPC分类号： H03K19/0005
摘要： A multiple finger off chip driver (OCD) has a single level translator for each of a plurality of PFET fingers and NFET fingers which allow the impedance of the OCD to be varied to match the impedance of a driven load. A plurality of PFET and NFET finger selection devices are used to select various combinations of output FETS and ballast resistor finger combinations to drive an output signal at a desired impedance level. The ballast resistors are scaled in ohmic value to the size of the output finger it is connected to. In this configuration, a constant ratio of FET impedance to ballast resistance is maintained in each drive stage (finger). By selecting various combinations of fingers various driver impedances can be selected.

94. 发明授权

US06538932B2 Timing circuit and method for a compilable DRAM 有权
标题翻译：可编程DRAM的定时电路和方法
公开(公告)号：US06538932B2
公开(公告)日：2003-03-25
申请号：US09880598
申请日：2001-06-13
申请人： Wayne F. Ellis , John A. Fifield , Louis L. Hsu
发明人： Wayne F. Ellis , John A. Fifield , Louis L. Hsu
IPC分类号： G11C700
CPC分类号： G11C11/4096 , G11C7/1051 , G11C7/22 , G11C11/4076 , G11C2207/2281
摘要： A semiconductor memory is disclosed, the memory comprising: a memory cell adapted to store a bit; a wordline and a bitline coupled to the memory cell; a primary sense amplifier coupled to the bitline to receive a signal representing the stored bit when the wordline is active; a wordline driver coupled to activate the wordline; and a primary delay device adapted to produce a first delay selected from a range of selectable delays, the primary delay device adapted to compensate for signal propagation delay along the wordline.
摘要翻译：公开了一种半导体存储器，所述存储器包括：适于存储位的存储器单元; 耦合到存储器单元的字线和位线; 当所述字线有效时，耦合到所述位线的初级读出放大器接收表示存储位的信号; 耦合以激活字线的字线驱动器; 以及适于产生从可选延迟的范围中选择的第一延迟的主延迟装置，所述主延迟装置适于补偿沿着字线的信号传播延迟。

95. 发明授权

US06518827B1 Sense amplifier threshold compensation 有权
标题翻译：感应放大器阈值补偿
公开(公告)号：US06518827B1
公开(公告)日：2003-02-11
申请号：US09917059
申请日：2001-07-27
申请人： John A. Fifield , Robert H. Dennard , Russell J. Houghton , Toshiaki Kirihara , Wing Luk
发明人： John A. Fifield , Robert H. Dennard , Russell J. Houghton , Toshiaki Kirihara , Wing Luk
IPC分类号： H03K301
CPC分类号： G11C7/04 , G11C7/06 , G11C11/4091 , G11C2207/2254
摘要： A method and system are disclosed for adjusting the threshold in MOS devices, in particular for devices used in DRAM sense amplifiers. The effects of process and temperature variations on the threshold are compensated by a back-bias voltage. A comparison of an indicating voltage and a reference voltage is used to generate the back-bias voltage. The direction of back-bias voltage may be either in the backward, or in the forward bias direction.
摘要翻译：公开了用于调整MOS器件中的阈值的方法和系统，特别是用于DRAM读出放大器中的器件。工艺和温度变化对阈值的影响由反向偏置电压补偿。使用指示电压和参考电压的比较来产生反偏压。背向偏置电压的方向可以是向后偏置方向或向前偏置方向。

96. 发明授权

US06452855B1 DRAM array interchangeable between single-cell and twin-cell array operation 失效
标题翻译： DRAM单元与双电池阵列的操作可互换
公开(公告)号：US06452855B1
公开(公告)日：2002-09-17
申请号：US09755868
申请日：2001-01-05
申请人： Louis L. Hsu , Rajiv V. Joshi , John A. Fifield , Wayne F. Ellis
发明人： Louis L. Hsu , Rajiv V. Joshi , John A. Fifield , Wayne F. Ellis
IPC分类号： H01L27118
CPC分类号： G11C7/1045 , G11C7/1006 , G11C11/4091 , G11C11/4096 , G11C11/4097
摘要： A DRAM array is provided capable of being interchanged between single-cell and twin-cell array operation for storing data in a single-cell or a twin-cell array format, respectively. Preferably, the DRAM array is operated in the single-cell array format during one operating mode and the DRAM array is operated in the twin-cell array format during another operating mode. Switching circuitry is included for interchanging between single-cell and twin-cell array operation, and vice versa. Methods are also provided for converting data stored within the DRAM array from the single-cell to the twin-cell array format, and vice versa.
摘要翻译：提供能够在用于以单电池或双电池阵列格式存储数据的单电池和双电池阵列操作之间互换的DRAM阵列。优选地，DRAM阵列在一个操作模式期间以单个单元阵列格式操作，并且DRAM阵列在另一个操作模式期间以双电池阵列格式操作。包括开关电路用于单电池和双电池阵列操作之间的互换，反之亦然。还提供了用于将DRAM阵列中存储的数据从单小区转换为双小区阵列格式的方法，反之亦然。

97. 发明授权

US06445611B1 Method and arrangement for preconditioning in a destructive read memory 失效
标题翻译：在破坏性读取存储器中预处理的方法和装置
公开(公告)号：US06445611B1
公开(公告)日：2002-09-03
申请号：US09966142
申请日：2001-09-28
申请人： John A. Fifield , Chorng-Lii Hwang , Daniel W. Storaska
发明人： John A. Fifield , Chorng-Lii Hwang , Daniel W. Storaska
IPC分类号： G11C1124
CPC分类号： G11C8/08 , G11C11/4076 , G11C11/408 , G11C2207/104
摘要： An arrangement and method is disclosed which works toward shortening the machine cycle of a DRAM. A data value is written to a storage capacitor of a memory cell of the DRAM, the data value being stored in the storage capacitor as one of low state and high state. During a first wordline activation cycle, a storage capacitor is preconditioned to a preconditioned voltage level. In a subsequent wordline activation cycle, a low state or a high state is written to the storage capacitor. In an aspect of the invention, the wordline is activated in a first wordline activation cycle to begin clearing any previously stored state of the storage capacitor. This cycle may include the reading of a stored data value from the storage capacitor. Then, immediately thereafter, while maintaining the wordline activated, the storage capacitor is preconditioned to a preconditioned voltage level, as by clamping the bitline through a bitline restore device. The wordline is then deactivated. Subsequently, the wordline is activated again during a write cycle to write one of a low state and a high state to the storage capacitor to indicate a stored data value.
摘要翻译：公开了用于缩短DRAM的机器周期的布置和方法。将数据值写入到DRAM的存储单元的存储电容器中，将数据值存储在存储电容器中作为低状态和高状态之一。在第一字线激活周期期间，存储电容器被预处理成预处理的电压电平。在随后的字线激活周期中，将低状态或高状态写入存储电容器。在本发明的一个方面，字线在第一字线激活周期中被激活，以开始清除存储电容器的任何先前存储的状态。该周期可以包括从存储电容器读取存储的数据值。然后，紧接其后，在保持字线被激活的同时，将存储电容器预先处理为预处理的电压电平，如通过位线恢复装置夹紧位线。然后禁用字线。随后，在写入周期期间再次激活字线以将低状态和高状态中的一个写入存储电容器以指示存储的数据值。

98. 发明授权

US06243283B1 Impedance control using fuses 有权
标题翻译：使用熔断器进行阻抗控制
公开(公告)号：US06243283B1
公开(公告)日：2001-06-05
申请号：US09589922
申请日：2000-06-07
申请人： Claude Louis Bertin , John A. Fifield , Erik Leigh Hedberg , Russell J. Houghton , Timothy Dooling Sullivan , Steven William Tomashot , William Robert Tonti
发明人： Claude Louis Bertin , John A. Fifield , Erik Leigh Hedberg , Russell J. Houghton , Timothy Dooling Sullivan , Steven William Tomashot , William Robert Tonti
IPC分类号： G11C506
CPC分类号： H01L23/481 , G11C17/16 , H01L25/0657 , H01L2224/06181 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/48227 , H01L2224/4826 , H01L2225/06517 , H01L2225/06541 , H01L2225/06555 , H01L2225/06562 , H01L2225/06589 , H01L2225/06596 , H01L2924/01012 , H01L2924/01019 , H01L2924/01046 , H01L2924/10253 , H01L2924/13091 , H01L2924/15192 , H01L2924/181 , H01L2924/3011 , H01L2924/00 , H01L2924/00012
摘要： A system and method for reducing impedance loading of semiconductor integrated circuit devices implementing protective device structures that contributes to impedance loading at an I/O pad connection. The method comprises providing a fuse device between the I/O pad connection and the protective device; connecting a current source device associated with each fuse device in the integrated circuit, the current source device connected to one end of the fuse device; providing fuse selection circuit for activating current flow through a selected fuse device between the current source and the I/O connection, the current flow being of an amount sufficient for blowing the fuse and disconnecting the protective device from the circuit structure, thereby reducing impedance loading at the I/O connection. Such a system and method is employed in a memory system comprising integrated circuit chips disposed in a stacked relation, with each chip including: a layer of active circuitry formed at a first layer of each chip; a plurality of through conducting structures disposed substantially vertically through each chip for enabling electronic connection with active circuitry at the first layer; second conducting device disposed at an end of the through conducting structure at an opposite side of a chip for connection with a corresponding through conductive structure of an adjacent stacked chip, the stacked chip structure formed by aligning one or more through conducting structures and second conducting devices of adjacent chips, whereby a chip of the stack is electronically connected to active circuitry formed on other chips of the stack. The stacked chip structure is ideal for reducing data access latency in memory systems employing memory chips such as DRAM.
摘要翻译：一种用于减少半导体集成电路器件的阻抗负载的系统和方法，其实现了有助于I / O焊盘连接处的阻抗加载的保护器件结构。该方法包括在I / O焊盘连接和保护装置之间设置熔丝装置; 连接与所述集成电路中的每个熔丝装置相关联的电流源装置，所述电流源装置连接到所述熔丝装置的一端; 提供保险丝选择电路，用于在电流源和I / O连接之间激活通过选定的保险丝装置的电流流动，电流量足以吹入保险丝并将保护装置与电路结构断开，从而减少阻抗负载在I / O连接。这种系统和方法被用在包括以堆叠关系布置的集成电路芯片的存储器系统中，每个芯片包括：形成在每个芯片的第一层的有源电路层; 多个通过导电结构，其基本垂直设置穿过每个芯片，以使得能够与第一层处的有源电路电连接; 第二导电装置，其设置在通孔导电结构的与芯片相对侧的端部处，与相邻的堆叠芯片的相应的贯穿导电结构相连接，所述堆叠的芯片结构通过将一个或多个穿过导电结构和第二导电装置的相邻芯片，由此堆叠的芯片电连接到形成在堆叠的其他芯片上的有源电路。堆叠式芯片结构非常适用于采用诸如DRAM之类的存储器芯片的存储器系统中的数据访问延迟。

99. 发明授权

US6141245A Impedance control using fuses 有权
标题翻译：使用熔断器进行阻抗控制
公开(公告)号：US6141245A
公开(公告)日：2000-10-31
申请号：US302902
申请日：1999-04-30
申请人： Claude Louis Bertin , John A. Fifield , Erik Leigh Hedberg , Russell J. Houghton , Timothy Dooling Sullivan , Steven William Tomashot , William Robert Tonti
发明人： Claude Louis Bertin , John A. Fifield , Erik Leigh Hedberg , Russell J. Houghton , Timothy Dooling Sullivan , Steven William Tomashot , William Robert Tonti
IPC分类号： H01L27/02 , G11C17/16 , H01L25/065 , G11C16/04
CPC分类号： H01L23/481 , G11C17/16 , H01L25/0657 , H01L2224/06181 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/48227 , H01L2224/4826 , H01L2225/06517 , H01L2225/06541 , H01L2225/06555 , H01L2225/06562 , H01L2225/06589 , H01L2225/06596 , H01L2924/01012 , H01L2924/01019 , H01L2924/01046 , H01L2924/10253 , H01L2924/13091 , H01L2924/15192 , H01L2924/181 , H01L2924/3011
摘要： A system and method for reducing impedance loading of semiconductor integrated circuit devices implementing protective device structures that contributes to impedance loading at an I/O pad connection. The method comprises providing a fuse device between the I/O pad connection and the protective device; connecting a current source device associated with each fuse device in the integrated circuit, the current source device connected to one end of the fuse device; providing fuse selection circuit for activating current flow through a selected fuse device between the current source and the I/O connection, the current flow being of an amount sufficient for blowing the fuse and disconnecting the protective device from the circuit structure, thereby reducing impedance loading at the I/O connection. Such a system and method is employed in a memory system comprising integrated circuit chips disposed in a stacked relation, with each chip including: a layer of active circuitry formed at a first layer of each chip; a plurality of through conducting structures disposed substantially vertically through each chip for enabling electronic connection with active circuitry at the first layer; second conducting device disposed at an end of the through conducting structure at an opposite side of a chip for connection with a corresponding through conductive structure of an adjacent stacked chip, the stacked chip structure formed by aligning one or more through conducting structures and second conducting devices of adjacent chips, whereby a chip of the stack is electronically connected to active circuitry formed on other chips of the stack. The stacked chip structure is ideal for reducing data access latency in memory systems employing memory chips such as DRAM.
摘要翻译：一种用于减少半导体集成电路器件的阻抗负载的系统和方法，其实现了有助于I / O焊盘连接处的阻抗加载的保护器件结构。该方法包括在I / O焊盘连接和保护装置之间设置熔丝装置; 连接与所述集成电路中的每个熔丝装置相关联的电流源装置，所述电流源装置连接到所述熔丝装置的一端; 提供保险丝选择电路，用于在电流源和I / O连接之间激活通过选定的保险丝装置的电流流动，电流量足以吹入保险丝并将保护装置与电路结构断开，从而减少阻抗负载在I / O连接。这种系统和方法被用在包括以堆叠关系布置的集成电路芯片的存储器系统中，每个芯片包括：形成在每个芯片的第一层的有源电路层; 多个通过导电结构，其基本垂直设置穿过每个芯片，以使得能够与第一层处的有源电路电连接; 第二导电装置，其设置在通孔导电结构的与芯片相对侧的端部处，与相邻的堆叠芯片的相应的贯穿导电结构相连接，所述堆叠的芯片结构通过将一个或多个穿过导电结构和第二导电装置的相邻芯片，由此堆叠的芯片电连接到形成在堆叠的其他芯片上的有源电路。堆叠式芯片结构非常适用于采用诸如DRAM之类的存储器芯片的存储器系统中的数据访问延迟。

100. 发明授权

US5604755A Memory system reset circuit 失效
标题翻译：存储器系统复位电路
公开(公告)号：US5604755A
公开(公告)日：1997-02-18
申请号：US565627
申请日：1995-11-20
申请人： Claude L. Bertin , Charles E. Drake , John A. Fifield , Erik Hedberg
发明人： Claude L. Bertin , Charles E. Drake , John A. Fifield , Erik Hedberg
IPC分类号： G06F11/00 , G06F11/07 , G06F11/10 , G11C5/00
CPC分类号： G06F11/1024 , G06F11/073 , G06F11/0793 , G11C5/005 , G06F11/0796
摘要： A reset circuit for resetting a memory system following a radiation event includes an error detect circuit for producing an error signal in response to detection of an uncorrectable error in the systems memory arrays, and includes a control circuit for selectively resetting at least select portions of the memory system in response to the error detect signal. All or portions of the memory arrays can be reset by the control circuit, and complete or selective latch reset, or selective power recycling are provided. In one embodiment, the control circuit provides latch reset in response to the error detect signal so as to reset the memory latches without recycling power, and in another embodiment, the control circuit selectively cycles power to independent memory zones of the system to reset only those zones whose memory array is identified as having an uncorrectable error. Preferably, the control circuit, and perhaps the detect circuit, are radiation hardened to further ensure dependable operation of the reset circuit following a radiation event.
摘要翻译：用于在辐射事件之后复位存储器系统的复位电路包括：误差检测电路，用于响应于系统存储器阵列中的不可校正误差的检测而产生误差信号，并且包括控制电路，用于至少选择性地复位存储器系统响应于错误检测信号。存储器阵列的全部或部分可由控制电路复位，并提供完整的或选择性的锁存复位或选择性的电力回收。在一个实施例中，控制电路响应于错误检测信号提供锁存器复位，以便在不再循环功率的情况下复位存储器锁存器，并且在另一实施例中，控制电路选择性地将电力循环到系统的独立存储器区域，以仅复位那些存储器阵列被识别为具有不可校正错误的区域。优选地，控制电路以及可能的检测电路被辐射硬化，以进一步确保在辐射事件之后复位电路的可靠操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式