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91. 发明授权

US06795326B2 Flash array implementation with local and global bit lines 有权
标题翻译： Flash阵列实现与本地和全局位线
公开(公告)号：US06795326B2
公开(公告)日：2004-09-21
申请号：US10017664
申请日：2001-12-12
申请人： Christophe Chevallier
发明人： Christophe Chevallier
IPC分类号： G11C700
CPC分类号： G11C29/025 , G11C7/18 , G11C29/02 , H01L27/115
摘要： A flash memory device that has a global and local bit line design that enables an alternate bit line stress mode as well as a way to detect short circuits in local and global bit lines with a single alternate bit line program. The flash memory device has a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a control gate and is coupled between one of the local bit lines in each set of local bit lines and one of the global bit lines. Thus, each local bit line in each set of local bit lines is coupled to a different global bit line. Multiple select lines are used to activate the control gates on the select transistors. Each select line is coupled to the control gates on associated select transistors. The associated select transistors are select transistors that are coupled to the local bit lines in an associated set of local bit lines.
摘要翻译：具有全局和局部位线设计的闪速存储器件，能够实现备用位线应力模式，以及通过单个备用位线程序检测局部和全局位线中的短路的方法。闪速存储器件具有多组相邻的局部位线，多个全局位线和多个选择晶体管。每个选择晶体管具有控制栅极，并且耦合在每组局部位线中的局部位线之一和全局位线之一中。因此，每组局部位线中的每个局部位线被耦合到不同的全局位线。多个选择线用于激活选择晶体管上的控制栅极。每个选择线耦合到相关选择晶体管上的控制栅极。相关联的选择晶体管是选择晶体管，其耦合到相关联的局部位线集合中的局部位线。

92. 发明授权

US06769103B2 Line width check in layout database 失效
公开(公告)号：US06769103B2
公开(公告)日：2004-07-27
申请号：US10199727
申请日：2002-07-19
申请人： Christophe Chevallier , Adriana Ababei
发明人： Christophe Chevallier , Adriana Ababei
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： A method for checking the accuracy of non-standard line widths in a layout includes marking lines with a line width marker, and associating the line width markers with the lines throughout a design process to ensure that the lines remain at the desired widths.

93. 发明授权

US5387014A Clamping plate for a motor vehicle air conditioning installation 失效
标题翻译：夹紧板用于机动车空调安装
公开(公告)号：US5387014A
公开(公告)日：1995-02-07
申请号：US135229
申请日：1993-10-12
申请人： Christophe Chevallier
发明人： Christophe Chevallier
IPC分类号： B60H1/32 , B60H1/00 , F16L3/223 , F16L39/00 , F25B41/00 , F16L41/12
CPC分类号： B60H1/00571 , F16L3/223 , F16L39/00 , F25B41/003
摘要： A motor vehicle air conditioning installation includes a pair of parallel tubes with annular beads at their free ends, for assembly to a component of the fluid circuit of the installation, and a clamping plate or strut connecting the two tubes together. The strut is an elongated plate having two through apertures. One of these is a notch open at one end of the plate. Each aperture has a substantially semicircular region matching the circumference of the associated tubular element fitting within it. The second aperture is surrounded by the material of the plate over its whole periphery, and includes a widened region through which the associated bead of the corresponding tubular element can pass, this widened region being joined directly to the substantially semicircular region. The strut cannot be separated from the tubes without resilient deformation of the latter, which avoids the danger of its becoming lost during disassembly.
摘要翻译：机动车空调装置包括一对平行管，其自由端具有环形小珠，用于组装到装置的流体回路的部件，以及将两个管连接在一起的夹板或支柱。支柱是具有两个通孔的细长板。其中一个是在板的一端开口的开口。每个孔具有与其内的相关联的管状元件配件的圆周匹配的大致半圆形区域。第二孔被其整个周边的板的材料包围，并且包括加宽的区域，相应管状元件的相关联的珠可以穿过该加宽区域，该加宽区域直接连接到大致半圆形区域。支柱不能与管分离而没有弹性变形，这避免了在拆卸过程中其损失的危险。

94. 发明授权

US08208287B2 Contemporaneous margin verification and memory access for memory cells in cross-point memory arrays 有权
标题翻译：交叉点存储器阵列中的存储单元的同期保证金验证和存储器访问
公开(公告)号：US08208287B2
公开(公告)日：2012-06-26
申请号：US13181438
申请日：2011-07-12
申请人： Christophe Chevallier , Chang Hua Siau
发明人： Christophe Chevallier , Chang Hua Siau
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/5685 , G11C13/0007 , G11C13/0033 , G11C13/004 , G11C13/0061 , G11C16/3418 , G11C16/3431 , G11C2013/0054 , G11C2211/5634 , G11C2211/5646 , G11C2213/71 , G11C2213/77
摘要： Circuitry for restoring data values in re-writable non-volatile memory is disclosed. An integrated circuit includes a memory access circuit and a sensing circuit configured to sense a data signal during a read operation to at least one two-terminal non-volatile cross-point memory array. Each memory array includes a plurality of two-terminal memory elements. A plurality of the memory arrays can be fabricated over the substrate and vertically stacked on one another. Further, the integrated circuit can include a margin manager circuit configured to manage a read margin for the two-terminal memory elements substantially during the read operation, thereby providing for contemporaneous read and margin determination operations. Stored data read from the two-terminal memory elements may have a value of the stored data restored (e.g., re-written to the same cell or another cell) if the value is not associated with a read margin (e.g., a hard programmed or hard erased state).
摘要翻译：公开了用于恢复可重写非易失性存储器中的数据值的电路。集成电路包括存储器访问电路和被配置为在至少一个两端非易失性交叉点存储器阵列的读取操作期间感测数据信号的感测电路。每个存储器阵列包括多个两端存储元件。可以在衬底上制造多个存储器阵列并且彼此垂直地堆叠。此外，集成电路可以包括边缘管理器电路，其被配置为基本上在读取操作期间管理两端存储元件的读取余量，由此提供同时的读取和余量确定操作。从两端存储元件读取的存储数据可以具有恢复的存储数据的值（例如，重新写入同一单元或另一单元），如果该值不与读取余量相关联（例如，硬编程或硬擦除状态）。

95. 发明授权

US08120945B2 Preservation circuit and methods to maintain values representing data in one or more layers of memory 失效
标题翻译：保存电路和保持在一层或多层存储器中表示数据的值的方法
公开(公告)号：US08120945B2
公开(公告)日：2012-02-21
申请号：US12932637
申请日：2011-03-01
申请人： Christophe Chevallier , Robert Norman
发明人： Christophe Chevallier , Robert Norman
IPC分类号： G11C11/00
CPC分类号： G11C13/0035 , G11C5/005 , G11C5/02 , G11C11/16 , G11C13/0002 , G11C13/0033 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2213/71 , G11C2213/77
摘要： Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.
摘要翻译：公开了用于恢复存储器中的数据的电路和方法。存储器可以包括非易失性两端交叉点阵列的至少一层，其包括将数据存储为多个电导率分布并且在没有电力的情况下保存存储的数据的多个两端存储器元件。在一段时间内，指示存储的数据的逻辑值可能漂移，使得如果逻辑值不被恢复，则所存储的数据可能被破坏。每个存储器的至少一部分可以具有与存储器电耦合的电路重写或恢复的数据。可以使用其他电路来确定用于对存储器执行恢复操作的调度，并且恢复操作可以由内部或外部信号或事件来触发。电路可以定位在逻辑层中，并且存储器可以在逻辑层上制造。

96. 发明申请

US20100157670A1 High voltage switching circuitry for a cross-point array 有权
标题翻译：用于交叉点阵列的高压开关电路
公开(公告)号：US20100157670A1
公开(公告)日：2010-06-24
申请号：US12653899
申请日：2009-12-18
申请人： Christophe Chevallier , Chang Hua Siau
发明人： Christophe Chevallier , Chang Hua Siau
IPC分类号： G11C16/06 , G11C7/00 , G11C16/04
CPC分类号： G11C13/0023 , G11C8/08 , G11C8/10 , G11C13/0007 , G11C13/0028 , G11C2213/31 , G11C2213/71 , G11C2213/77 , H03K3/356104 , H03K19/018521
摘要： Circuitry for generating voltage levels operative to perform data operations on non-volatile re-writeable memory arrays are disclosed. In some embodiments an integrated circuit includes a substrate and a base layer formed on the substrate to include active devices configured to operate within a first voltage range. Further, the integrated circuit can include a cross-point memory array formed above the base layer and including re-writable two-terminal memory cells that are configured to operate, for example, within a second voltage range that is greater than the first voltage range. Conductive array lines in the cross-point memory array are electrically coupled with the active devices in the base layer. The integrated circuit also can include X-line decoders and Y-line decoders that include devices that operate in the first voltage range. The active devices can include other active circuitry such as sense amps for reading data from the memory cells, for example.
摘要翻译：公开了用于产生用于对非易失性可重写存储器阵列执行数据操作的电压电平的电路。在一些实施例中，集成电路包括衬底和形成在衬底上的基底层，以包括被配置为在第一电压范围内操作的有源器件。此外，集成电路可以包括形成在基极层上方的交叉点存储器阵列，并且包括可重写的两端存储器单元，其被配置为例如在大于第一电压范围的第二电压范围内操作。交叉点存储器阵列中的导电阵列线与基极层中的有源器件电耦合。集成电路还可以包括X线解码器和Y线解码器，其中包括在第一电压范围内工作的器件。有源器件可以包括其他有源电路，例如用于从存储器单元读取数据的感测放大器。

97. 发明授权

US07107554B2 Line width check in layout database 有权
标题翻译：线宽检查布局数据库
公开(公告)号：US07107554B2
公开(公告)日：2006-09-12
申请号：US10782252
申请日：2004-02-19
申请人： Christophe Chevallier , Adriana Ababei
发明人： Christophe Chevallier , Adriana Ababei
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A machine-readable medium has a set of machine-readable instructions for causing a computer to perform a method. The method includes checking a layout having a layout line width for at least one line versus a schematic having a schematic line width for the at least one line. Extracting a line width property from the schematic and transferring the line width property to the layout are included in the method, as is checking a design for the at least one line versus the schematic.
摘要翻译：机器可读介质具有用于使计算机执行方法的一组机器可读指令。该方法包括检查具有用于至少一行的布局线宽度的布局相对于具有至少一行的示意线宽度的示意图。从原理图中提取线宽属性并将线宽属性传递到布局包含在方法中，正如检查至少一行与原理图的设计一样。

98. 发明授权

US07055115B2 Line width check in layout database 失效
标题翻译：线宽检查布局数据库
公开(公告)号：US07055115B2
公开(公告)日：2006-05-30
申请号：US10782701
申请日：2004-02-19
申请人： Christophe Chevallier , Adriana Ababei
发明人： Christophe Chevallier , Adriana Ababei
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method of performing a design rule check on an integrated circuit includes tagging at least one line in a schematic with a width marker and an associated width parameter, extracting the line width marker and the associated line width parameter, comparing the extracted line width parameter with an actual design width for a design line, and generating an error condition when the actual design line width is less than the line width parameter.
摘要翻译：在集成电路上执行设计规则检查的方法包括使用宽度标记和相关联的宽度参数标记示意图中的至少一条线，提取线宽标记和相关线宽参数，将提取的线宽参数与设计线的实际设计宽度，并且当实际设计线宽小于线宽参数时产生错误条件。

99. 发明授权

US07042778B2 Flash array implementation with local and global bit lines 有权
公开(公告)号：US07042778B2
公开(公告)日：2006-05-09
申请号：US11085855
申请日：2005-03-22
申请人： Christophe Chevallier
发明人： Christophe Chevallier
IPC分类号： G11C29/00
CPC分类号： G11C29/025 , G11C7/18 , G11C29/02 , H01L27/115
摘要： A flash memory device that can detect short circuits in local and global bit lines. The flash memory device has a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a control gate and is coupled between one of the local bit lines in each set of local bit lines and one of the global bit lines. Thus, each local bit line in each set of local bit lines is coupled to a different global bit line. Multiple select lines are used to activate the control gates on the select transistors. Each select line is coupled to the control gates on associated select transistors. The associated select transistors are select transistors that are coupled to the local bit lines in an associated set of local bit lines.

100. 发明授权

US07024643B2 Identifying line width errors in integrated circuit designs 失效
标题翻译：识别集成电路设计中的线宽误差
公开(公告)号：US07024643B2
公开(公告)日：2006-04-04
申请号：US10782450
申请日：2004-02-19
申请人： Christophe Chevallier , Adriana Ababei
发明人： Christophe Chevallier , Adriana Ababei
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method of identifying line width errors in an integrated circuit design includes adding a line width marker for each of a plurality of lines on a schematic, each line having a schematic line width, creating a layout from the schematic, the layout containing the line width markers and a plurality of layout widths, checking the layout line widths versus the schematic line widths for the plurality of line width marked lines, creating a design representing the layout, the design having a plurality of design line widths, and checking the design line widths versus the layout line widths for the plurality of line width marked lines.
摘要翻译：在集成电路设计中识别线宽误差的方法包括在原理图上为多个线中的每一行添加线宽标记，每行具有示意线宽度，从原理图创建布局，包含线宽度标记和多个布局宽度，检查布局线宽度与多条线宽标记线的示意线宽度，创建表示布局的设计，设计具有多个设计线宽度，以及检查设计线宽度相对于多个线宽标记线的布局线宽度。

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