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91. 发明授权

US5835406A Apparatus and method for selecting data bits read from a multistate memory 失效
公开(公告)号：US5835406A
公开(公告)日：1998-11-10
申请号：US736380
申请日：1996-10-24
申请人： Christophe J. Chevallier , Vinod C. Lakhani
发明人： Christophe J. Chevallier , Vinod C. Lakhani
IPC分类号： G11C11/56 , G11C11/34 , G11C11/22
CPC分类号： G11C11/5628 , G11C11/56 , G11C11/5621 , G11C11/5635 , G11C11/5642 , G11C2211/5641 , G11C7/1006
摘要： An apparatus and method which sequentially selects subsets of data bits read in parallel from an array of memory cells (each cell being operated as a multistate memory device) and sequentially asserts the selected subsets to a data bus. Preferably, the cells are flash memory cells. Preferably, the apparatus includes a sense amplifier circuit, a multiplexer, and circuitry operable to read a number (N) of the cells in parallel, whether the cells are operated as binary or multistate devices. The sense amplifier has N input lines and MN output lines, where M is the number of binary bits in a binary representation of the data read from each cell operated as a multistate device. The multiplexer has MN inputs (each connected to one of the output lines of the sense amplifier circuit), N outputs connected to a data bus having N-bit width, and is controllable to output selected N-bit subsets of the MN bits received at its MN inputs. Another aspect of the invention is a memory system including such a multiplexer and read/write circuitry operable in a mode in which it writes data to selected cells of the array (leaving each cell in an erased or programmed state) or reads a binary data bit from each of N selected cells, where the read/write circuitry is also operable in another mode in which it writes data to selected cells of the array (leaving each cell in an erased state or a selected one of two or more possible programmed states) or reads data (indicative of an ordered set of at least two binary data bits) from each of N selected cells.

92. 发明授权

US5815458A System and method for writing data to memory cells so as to enable faster reads of the data using dual wordline drivers 失效
公开(公告)号：US5815458A
公开(公告)日：1998-09-29
申请号：US709555
申请日：1996-09-06
申请人： Christophe J. Chevallier , Vinod C. Lakhani , Robert D. Norman , Darrell D. Rinerson
发明人： Christophe J. Chevallier , Vinod C. Lakhani , Robert D. Norman , Darrell D. Rinerson
IPC分类号： G11C8/08 , G11C16/08 , G11C7/00
CPC分类号： G11C16/08 , G11C8/08
摘要： A memory system including an array of memory cells (e.g., flash memory cells) connected along wordlines and bitlines, two physically separated sets of wordline drivers (each for driving a different subset of the wordlines), and circuitry for writing data to selected cells connected along a selected wordline, where the cells are selected to be near the wordline driver for the wordline, to reduce the time needed for subsequent reads of the data, and a method implemented by such system. To write a sector of data (consisting of packets of the data) to cells connected along a wordline, the system preferably writes the first packet (or the first N bits of the first packet) to the cells which are physically nearest to the wordline driver which drives the wordline. In some embodiments, one set of wordline drivers (positioned along one side of the array) drives the even-numbered wordlines, another set of wordline drivers (positioned along the opposite side of the array) drives the odd-numbered wordlines, and the system exchanges the bitline addresses of the first packet and last packet (or the first N bytes of the first packet and the last N bytes of the last packet) of each sector to be written to cells along an even-numbered wordline (or inverts the bitline addresses for the entire sector), but the system does not modify the bitline address of any of data bit to be written to cells connected along an odd-numbered wordline. Preferably, the system is operable in either a first mode in which it modifies the addresses to which data is to be written to a cell array (to reduce the time needed to read the data after it has been written) or a second mode in which it does not modify the addresses to which the data is to be written to the array.

93. 发明授权

US5801985A Memory system having programmable control parameters 失效
标题翻译：具有可编程控制参数的存储系统
公开(公告)号：US5801985A
公开(公告)日：1998-09-01
申请号：US508828
申请日：1995-07-28
申请人： Frankie F. Roohparvar , Darrell D. Rinerson , Christophe J. Chevallier , Michael S. Briner
发明人： Frankie F. Roohparvar , Darrell D. Rinerson , Christophe J. Chevallier , Michael S. Briner
IPC分类号： G11C16/02 , G11C5/00 , G11C11/407 , G11C16/06 , G11C8/00
CPC分类号： G11C16/12 , G11C16/20 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/46 , G11C5/04 , G11C7/1045 , G11C16/04 , G11C2029/4402
摘要： A memory system capable of being configured for optimum performance after fabrication using control parameters stored in non-volatile data storage units. The system includes an array of memory cells, separate from the data storage units, arranged in a multiplicity of rows and a multiplicity of columns, with each cell located in one of the rows being coupled to a common word line and with each cell located in one of the columns being coupled to a common bit line. Control circuitry for controlling memory operations such as programming the memory cells and reading the memory cells when the memory system is in a normal mode of operation. The non-volatile data storage units store control parameter data used by the control means for controlling the memory operations, with the control parameters being modifiable when the memory system is placed in an alternative mode of operation as opposed the normal mode of operation. Once the memory has been fabricated and characterized, the control parameters can be selected for optimum memory performance and loaded into the data storage units.
摘要翻译：一种存储器系统，其能够被配置为在使用存储在非易失性数据存储单元中的控制参数在制造之后实现最佳性能。该系统包括与数据存储单元分离的多个行和多个列的存储器单元阵列，其中位于一行中的每个单元被耦合到公共字线，并且每个单元位于其中一列被耦合到公共位线。用于控制存储器操作的控制电路，例如当存储器系统处于正常操作模式时对存储器单元进行编程和读取存储器单元。非易失性数据存储单元存储由用于控制存储器操作的控制装置使用的控制参数数据，当与正常操作模式相反时，当存储器系统处于替代操作模式时，控制参数是可修改的。一旦存储器被制造和表征，可以选择控制参数以获得最佳的存储器性能并加载到数据存储单元中。

94. 发明授权

US5793087A Segmented non-volatile memory array having multiple sources 失效
公开(公告)号：US5793087A
公开(公告)日：1998-08-11
申请号：US814326
申请日：1997-03-11
申请人： Christophe J. Chevallier
发明人： Christophe J. Chevallier
IPC分类号： G11C16/04 , H01L27/115 , H01L29/78
CPC分类号： H01L27/11519 , G11C16/0416 , H01L27/115
摘要： An arrangement of non-volatile memory cells, such as flash memory cells which includes erase blocks which can be separately erased and which require a reduced amount of circuit area. The erase blocks each include an array of the cells arranged in rows and columns. Each cell in a row has its control gate connected to a common word line and its drain connected to a common bit line. All of the sources of one of the erase blocks are connected together by a source line structure which includes non-metallic source lines, such as doped semiconductor lines, which run generally parallel with respect to the word line and interconnect the sources of cell located in a row. The source line structure further includes at least one metallic source line which functions to interconnect the source regions of cells located in one of the erase block cell columns. The metallic source line of one of the erase blocks extends over, but is not connected to, the adjacent erase block, with the source lines of the erase blocks preferably being connected to a common source line decoder used to control the status of a selected one of the source lines so that a selected one of the erase blocks can be erased.

95. 发明授权

US5781477A Flash memory system having fast erase operation 失效
公开(公告)号：US5781477A
公开(公告)日：1998-07-14
申请号：US604815
申请日：1996-02-23
申请人： Darrell D. Rinerson , Roger R. Lee , Christophe J. Chevallier
发明人： Darrell D. Rinerson , Roger R. Lee , Christophe J. Chevallier
IPC分类号： G11C5/14 , G11C16/16 , G11C16/30 , G11C7/00
CPC分类号： G11C16/16 , G11C16/30 , G11C5/145
摘要： A flash memory system powered by an external primary voltage source, with the system including an array of flash memory cells arranged in rows and columns, with each of the cells including a source region, a drain region, a channel region intermediate the drain and source region, a floating gate disposed over the channel region and a control gate disposed over the floating gate, with the cells located in one of the array columns having their drains connected to a common bit line and with the cells in one of the rows having their control gates connected to a common word line. The memory system includes a control circuit carrying out read, programming and erase operations. The erase operation is performed by applying a negative voltage to control gate of the cell being erased and a positive voltage to the source of the cells being erased. The positive voltage is greater in magnitude than the external primary voltage source and is preferably produced utilizing a charge pump circuit powered by the primary voltage source. The relatively large source voltage enables the cell to be erased rapidly and with a reduced tendency to produce positive charges which can be trapped in the gate oxide intermediate the floating gate and the channel/source of the cell.

96. 发明授权

US5771346A Apparatus and method for detecting over-programming condition in multistate memory device 失效
公开(公告)号：US5771346A
公开(公告)日：1998-06-23
申请号：US736195
申请日：1996-10-24
申请人： Robert D. Norman , Christophe J. Chevallier
发明人： Robert D. Norman , Christophe J. Chevallier
IPC分类号： G06F11/10 , G11C11/56 , G11C29/00 , G11C29/52 , G11C11/34
CPC分类号： G11C29/765 , G06F11/1072 , G11C11/5621 , G11C11/5628 , G11C16/3413 , G11C16/3418 , G11C16/3463 , G11C29/52 , G11C29/76 , G11C29/82 , G11C7/1039 , G11C16/04 , G11C2029/0409 , G11C2211/5643 , G11C29/00
摘要： An apparatus and method for detecting an over-programming condition in a multistate memory cell. The invention is also directed to identifying the over-programmed cells and providing an alternate location at which to write the data intended for the over-programmed cell. An over-programmed state detection circuit generates an error signal when the data contained in a multistate memory cell is found to be over-programmed relative to its intended programming (threshold voltage level) state. Upon detection of an over-programmed cell, the programming operation of the memory system is modified to discontinue further programming attempts on the cell. The over-programmed state detection circuit is also used to assist in correcting for the over-programming state, permitting the programming error to be compensated for by the memory system.

97. 发明授权

US5764568A Method for performing analog over-program and under-program detection for a multistate memory cell 失效
公开(公告)号：US5764568A
公开(公告)日：1998-06-09
申请号：US736568
申请日：1996-10-24
申请人： Christophe J. Chevallier
发明人： Christophe J. Chevallier
IPC分类号： G11C11/56 , G11C16/34 , G11C7/00
CPC分类号： G11C16/3463 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5642 , G11C2211/5644 , G11C29/00
摘要： A method for detecting an under-programming or over-programming condition in a multistate memory cell. The method uses three sense amplifiers, each with an associated reference cell which produces a reference voltage for input to each of the sense amplifiers. Control circuitry is used which allows the reference cell currents to be varied to produce the reference voltages or pairs of reference voltages needed to accurately determine the threshold voltage and hence state of a programmed or erased memory cell. This information is used by a controller to determine if a memory cell has been over-programmed, under-programmed, or properly programmed. If the cell has not been properly programmed, then additional programming pulses are applied (in the case of under-programming) or an error flag is set and the programming algorithm is terminated (in the case of an over-programmed cell).

98. 发明授权

US5751944A Non-volatile memory system having automatic cycling test function 失效
标题翻译：具有自动循环测试功能的非易失性存储器系统
公开(公告)号：US5751944A
公开(公告)日：1998-05-12
申请号：US508797
申请日：1995-07-28
申请人： Frankie F. Roohparvar , Christophe J. Chevallier
发明人： Frankie F. Roohparvar , Christophe J. Chevallier
IPC分类号： G11C29/46 , G11C29/52 , G01R31/28
CPC分类号： G11C29/52 , G11C29/46
摘要： A flash memory system having the capability of automatically executing consecutive program-erase cycles for the purpose of measuring the endurance of the memory. The memory system may be switched to a test mode which triggers the autocycling by applying a high voltage to two of the package pins of the system which normally are coupled to low voltage sources. The system includes an internal state machine which, in normal operation, is implemented to perform flash cell programming, erasing and reading, with the erasing sequence including a preprogram step where, prior to the erase, all cells are programmed. When placed in the autocycle mode by application of the high voltages to the pins, the state machine is caused to enter the erase sequence, including the preprogram step. Once the first erase sequence is concluded, circuitry is provided that causes the state machine to automatically initiate a further erase sequence. The erase sequences will continue until interrupted, with each sequence constituting a single program-erase cycle.
摘要翻译：具有能够自动执行连续编程擦除周期以便测量存储器的耐久性的闪速存储器系统。存储器系统可以切换到测试模式，其通过对通常耦合到低电压源的系统的两个封装引脚施加高电压来触发自动循环。该系统包括内部状态机，其在正常操作中被实现以执行闪存单元编程，擦除和读取，其中擦除顺序包括预编程步骤，其中在擦除之前，所有单元被编程。当通过对引脚施加高电压而置于自动循环模式时，使状态机进入擦除顺序，包括预编程步骤。一旦完成了第一个擦除顺序，就提供了使状态机自动启动进一步擦除顺序的电路。擦除序列将继续直到中断，每个序列构成单个编程擦除周期。

99. 发明申请

US20120099011A1 CMOS IMAGER WITH INTEGRATED CIRCUITRY 有权
标题翻译：具有集成电路的CMOS图像
公开(公告)号：US20120099011A1
公开(公告)日：2012-04-26
申请号：US13341512
申请日：2011-12-30
申请人： Christophe J. Chevallier
发明人： Christophe J. Chevallier
IPC分类号： H04N5/335
CPC分类号： H04N5/772 , H04N5/335 , H04N5/907 , H04N9/8047 , Y10S438/945
摘要： A CMOS imager is integrated on a single substrate along with logic and support circuitry for decoding and processing optical information received by the CMOS imager. Integrating a CMOS imager and peripheral circuitry allows for a single chip image sensing device.
摘要翻译： CMOS成像器与逻辑和支持电路集成在单个基板上，用于解码和处理由CMOS成像器接收的光学信息。集成CMOS成像器和外围电路允许单片图像感测设备。

100. 发明申请

US20110228153A1 CMOS IMAGER WITH INTEGRATED CIRCUITRY 有权
标题翻译：具有集成电路的CMOS图像
公开(公告)号：US20110228153A1
公开(公告)日：2011-09-22
申请号：US13118066
申请日：2011-05-27
申请人： Christophe J. Chevallier
发明人： Christophe J. Chevallier
IPC分类号： H04N5/335
CPC分类号： H04N5/772 , H04N5/335 , H04N5/907 , H04N9/8047 , Y10S438/945
摘要： A CMOS imager is integrated on a single substrate along with logic and support circuitry for decoding and processing optical information received by the CMOS imager. Integrating a CMOS imager and peripheral circuitry allows for a single chip image sensing device.
摘要翻译： CMOS成像器与逻辑和支持电路集成在单个基板上，用于解码和处理由CMOS成像器接收的光学信息。集成CMOS成像器和外围电路允许单片图像感测设备。

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