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91. 发明授权

US06707399B1 Data realignment techniques for serial-to-parallel conversion 有权
标题翻译：用于串行到并行转换的数据重新对准技术
公开(公告)号：US06707399B1
公开(公告)日：2004-03-16
申请号：US10269370
申请日：2002-10-10
申请人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Gopi Rangan , Nitin Prasad
发明人： Bonnie Wang , Chiakang Sung , Khai Nguyen , Joseph Huang , Gopi Rangan , Nitin Prasad
IPC分类号： H03M900
CPC分类号： H03M9/00
摘要： Techniques for adjusting the boundary between bytes of data in a serial-to-parallel converter are provided. Bits of serial data are shifted into a first register. Data bytes are then shifted out of the first register along parallel signal lines into a second register. The timing of the parallel load of data from the first register to the second register determines the parallel data byte boundary. The boundary between the parallel data bytes can be shifted using a load enable signal. The phase of the load enable signal can be changed to shift the boundary between data bytes by one or more bits. The parallel data can then be loaded from the second register into a third register. The data output signal of the third register is synchronized to a core clock signal to ensure enough set up and hold time for signals output by the third register.
摘要翻译：提供了用于调整串并转换器中的数据字节之间边界的技术。串行数据的位被移入第一寄存器。然后，数据字节沿并行信号线移出第一寄存器，进入第二寄存器。从第一寄存器到第二寄存器的并行加载数据的时序确定并行数据字节边界。可以使用负载使能信号来移位并行数据字节之间的边界。可以改变负载使能信号的相位，以将数据字节之间的边界移位一个或多个位。然后可以将并行数据从第二寄存器加载到第三寄存器中。第三寄存器的数据输出信号与核心时钟信号同步，以确保第三寄存器输出的信号的足够的建立和保持时间。

92. 发明授权

US06437650B1 Phase-locked loop or delay-locked loop circuitry for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的锁相环或延迟锁定环电路
公开(公告)号：US06437650B1
公开(公告)日：2002-08-20
申请号：US09855865
申请日：2001-05-15
申请人： Chiakang Sung , Joseph Huang , Bonnie I. Wang , Robert R. N. Bielby
发明人： Chiakang Sung , Joseph Huang , Bonnie I. Wang , Robert R. N. Bielby
IPC分类号： H03L706
CPC分类号： G06F1/10 , H03L7/0812 , H03L7/0996 , H03L7/0997
摘要： A programmable logic device is provided with phase-locked loop (“PLL”) or delay-locked loop (“DLL”) circuitry in which the feedback loop circuitry substantially parallels and duplicates a portion of the clock signal distribution network on the device that receives the main PLL/DLL output signal. In this way the distributed feedback loop circuit more readily provides a substantially exact match for the distributed delay experienced by the signal propagating through the clock signal distribution network that the PLL/DLL circuitry serves.
摘要翻译：可编程逻辑器件提供有锁相环（“PLL”）或延迟锁定环（“DLL”）电路，其中反馈回路电路在接收的设备上基本平行并复制时钟信号分配网络的一部分主PLL / DLL输出信号。以这种方式，分布式反馈环路更容易地提供对通过PLL / DLL电路服务的时钟信号分配网络传播的信号经历的分布延迟的基本精确的匹配。

93. 发明授权

US5963051A Segmented localized conductors for programmable logic devices 失效
标题翻译：用于可编程逻辑器件的分段局部导体
公开(公告)号：US5963051A
公开(公告)日：1999-10-05
申请号：US837117
申请日：1997-04-14
申请人： Richard G. Cliff , Chiakang Sung
发明人： Richard G. Cliff , Chiakang Sung
IPC分类号： H03K19/177
CPC分类号： H03K19/1778 , H03K19/17704 , H03K19/17796
摘要： A programmable logic array integrated circuit device having a two-dimensional array of logic array blocks is provided in which the localized conductors serving each logic array block are segmented. The localized conductors are logic array block conductors that convey signals from associated interblock conductors to logic elements in the logic array blocks and local conductors that convey signals between the logic elements. The localized conductor segments are connected to each other by programmable logic connectors.
摘要翻译：提供具有逻辑阵列块的二维阵列的可编程逻辑阵列集成电路器件，其中为每个逻辑阵列块服务的局部导体被分段。局部导体是将信号从相关联的块间导体传送到逻辑阵列块中的逻辑元件和在逻辑元件之间传送信号的局部导体的逻辑阵列块导体。局部导体段通过可编程逻辑连接器相互连接。

94. 发明授权

US5828229A Programmable logic array integrated circuits 失效
标题翻译：可编程逻辑阵列集成电路
公开(公告)号：US5828229A
公开(公告)日：1998-10-27
申请号：US847004
申请日：1997-05-01
申请人： Richard G. Cliff , L. Todd Cope , Cameron McClintock , William Leong , James Allen Watson , Joseph Huang , Bahram Ahanin , Chiakang Sung , Wanli Chang
发明人： Richard G. Cliff , L. Todd Cope , Cameron McClintock , William Leong , James Allen Watson , Joseph Huang , Bahram Ahanin , Chiakang Sung , Wanli Chang
IPC分类号： G01R31/3185 , G11C8/12 , G11C8/16 , G11C29/32 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , G11C29/32 , G11C8/12 , G11C8/16 , H03K19/17704 , H03K19/17728 , H03K19/1776 , H03K19/17764 , G01R31/318516
摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors. A relatively large block of random access memory ("RAM") may be provided on the device for use as read-only memory ("ROM") or RAM during operation of the device to perform logic. The RAM block is connected in the circuitry of the device so that it can be programmed and verified compatibly with other memory on the device. Thereafter the circuitry of the RAM block allows it to be switched over to operation as RAM or ROM during logic operation of the device.
摘要翻译：可编程逻辑阵列集成电路具有多个可编程逻辑模块，它们被组合在多个逻辑阵列块（“LAB”）中。 LAB以二维阵列布置在电路上。提供一个导线网络，用于将任何逻辑模块与任何其他逻辑模块相互连接。此外，相邻或附近的逻辑模块可以彼此连接，用于在逻辑模块之间提供进位链和/或用于将两个或多个模块连接在一起以提供更复杂的逻辑功能而不必利用一般互连的特殊目的网络。提供了所谓的快速或通用导体的另一网络，用于在整个电路中分布广泛使用的逻辑信号，例如时钟和清除信号。多路复用器可以以各种方式用于减少信号导体之间所需的可编程互连数量。随机存取存储器（“RAM”）相对较大的块可以在设备的操作期间被提供在设备上用作只读存储器（“ROM”）或RAM，以执行逻辑。 RAM块连接在设备的电路中，使其可以与设备上的其他存储器进行编程和验证。此后，RAM块的电路允许在设备的逻辑运行期间将其切换到作为RAM或ROM的操作。

95. 发明授权

US5633830A Random access memory block circuitry for programmable logic array integrated circuit devices 失效
标题翻译：用于可编程逻辑阵列集成电路器件的随机存取存储器块电路
公开(公告)号：US5633830A
公开(公告)日：1997-05-27
申请号：US555106
申请日：1995-11-08
申请人： Chiakang Sung , Wanli Chang , Joseph Huang , Richard G. Cliff
发明人： Chiakang Sung , Wanli Chang , Joseph Huang , Richard G. Cliff
IPC分类号： G01R31/3185 , G11C8/12 , G11C8/16 , G11C29/32 , H03K19/173 , H03K19/177 , G11C7/00
CPC分类号： H03K19/1737 , G11C29/32 , G11C8/12 , G11C8/16 , H03K19/17704 , H03K19/17728 , H03K19/1776 , H03K19/17764 , G01R31/318516
摘要： A relatively large block of random access memory ("RAM") may be provided on a programmable logic array integrated circuit device for use as read-only memory ("ROM") or RAM during operation of the device to perform logic. The RAM block is connected in the circuitry of the device so that it can be programmed and verified compatibly with other memory on the device. Thereafter the circuitry of the RAM block allows it to be switched over to operation as RAM or ROM during logic operation of the device.
摘要翻译：可以在可编程逻辑阵列集成电路装置上提供相对较大的随机存取存储器块（“RAM”），用于在设备操作期间用作只读存储器（“ROM”）或RAM以执行逻辑。 RAM块连接在设备的电路中，使其可以与设备上的其他存储器进行编程和验证。此后，RAM块的电路允许在设备的逻辑运行期间将其切换到作为RAM或ROM的操作。

96. 发明授权

US5555214A Apparatus for serial reading and writing of random access memory arrays 失效
标题翻译：用于串行读取和写入随机存取存储器阵列的装置
公开(公告)号：US5555214A
公开(公告)日：1996-09-10
申请号：US555110
申请日：1995-11-08
申请人： Chiakang Sung , Wanli Chang , Joseph Huang
发明人： Chiakang Sung , Wanli Chang , Joseph Huang
IPC分类号： G11C7/10 , G11C7/22 , G11C7/00
CPC分类号： G11C7/103 , G11C7/22
摘要： A method of serially reading and writing random access memory arrays is provided. Although the read/write inputs continually change as programming data are clocked into the input buffers, a read/write control circuit prevents the constantly changing read/write inputs from causing undesired reading and writing.
摘要翻译：提供了串行读取和写入随机存取存储器阵列的方法。尽管读/写输入随着编程数据被输入到输入缓冲器而不断变化，但读/写控制电路可以防止不断变化的读/写输入引起不期望的读和写。

97. 发明授权

US09558131B1 Integrated circuit with bonding circuits for bonding memory controllers 有权
标题翻译：具有用于连接存储器控制器的接合电路的集成电路
公开(公告)号：US09558131B1
公开(公告)日：2017-01-31
申请号：US13164426
申请日：2011-06-20
申请人： Jeffrey Schulz , Chiakang Sung , Michael H. M. Chu
发明人： Jeffrey Schulz , Chiakang Sung , Michael H. M. Chu
IPC分类号： G06F13/00
CPC分类号： G06F13/00 , G06F13/1678 , G06F13/1684 , G06F13/4022
摘要： An IC that includes a first memory controller, a second memory controller, and a first bonding circuit coupled to the first memory controller, where the first bonding circuit is a hard logic bonding circuit and is operable to coordinate memory control functions of the first memory controller and the second memory controller. In one implementation, the first memory controller is an N bits wide memory controller, the second memory controller is an M bits wide memory controller, and the first bonding circuit is operable to coordinate the memory control functions of the first memory controller and the second memory controller such that the first and second memory controllers together function as an N+M bits wide memory controller, where N and M are positive integers.
摘要翻译：一种IC，包括第一存储器控制器，第二存储器控制器和耦合到第一存储器控制器的第一接合电路，其中第一接合电路是硬逻辑接合电路，并且可操作以协调第一存储器控制器的存储器控制功能和第二存储器控制器。在一个实现中，第一存储器控制器是N位宽存储器控制器，第二存储器控制器是M位宽存储器控制器，并且第一接合电路可操作以协调第一存储器控制器和第二存储器的存储器控制功能控制器，使得第一和第二存储器控制器一起用作N + M位宽存储器控制器，其中N和M是正整数。

98. 发明授权

US09504156B1 Distribution of return paths for improved impedance control and reduced crosstalk 有权
标题翻译：返回路径的分布，用于改进阻抗控制和减少串扰
公开(公告)号：US09504156B1
公开(公告)日：2016-11-22
申请号：US11784540
申请日：2007-04-06
申请人： Gopinath Rangan , Khai Nguyen , Chiakang Sung
发明人： Gopinath Rangan , Khai Nguyen , Chiakang Sung
IPC分类号： H05K1/14 , H05K1/11 , H05K3/42
CPC分类号： H05K1/14 , H01L23/48 , H01L23/49838 , H01L23/50 , H01L24/00 , H01L24/13 , H01L24/14 , H01L2224/13101 , H05K1/0296 , H05K1/111 , H05K1/114 , H05K3/429 , H05K2201/10674 , Y02P70/611 , H01L2924/014 , H01L2924/00014
摘要： To achieve an even distribution of different types of connections, sets of connection cells have been devised having different ratios of signal, power and ground connections in which the signal connections are all within a maximum distance of a power and/or a ground connection. In addition, the shapes of the cells are such that the cells fit together in a repeatable array that fully covers the plane of the interface, i.e., an array that tiles the plane. Accordingly, to distribute the connections substantially uniformly across the interface, the ratio of the number of signal connections, power connections and ground connections is determined; a cell is selected from the set of cells that has approximately the same ratio of the number of signal connections, power connections and ground connections; and the selected cell is repeatedly used to allocate the signal, power and ground connections in accordance with the distribution of connections in the selected cell until all the connections are distributed.
摘要翻译：为了实现不同类型的连接的均匀分配，已经设计了具有信号，功率和接地连接的不同比率的连接单元组，其中信号连接都在功率和/或接地连接的最大距离内。此外，单元的形状使得这些单元以可完全覆盖界面的平面的可重复阵列（即平铺该平面的阵列）配合在一起。因此，为了将连接基本均匀地分布在接口上，确定信号连接数量，电源连接和接地连接的数量比; 从具有大致相同的信号连接数，电源连接和接地连接的比例的单元组中选择一个单元; 并且所选择的小区被重复地用于根据所选小区中的连接的分布来分配信号，电源和接地连接，直到所有连接都分发为止。

99. 发明授权

US09032162B1 Systems and methods for providing memory controllers with memory access request merging capabilities 有权
标题翻译：为存储器控制器提供存储器访问请求合并功能的系统和方法
公开(公告)号：US09032162B1
公开(公告)日：2015-05-12
申请号：US13209137
申请日：2011-08-12
申请人： Ching-Chi Chang , Ravish Kapasi , Jeffrey Schulz , Michael H. M. Chu , Caroline Ssu-Min Chen , Chiakang Sung
发明人： Ching-Chi Chang , Ravish Kapasi , Jeffrey Schulz , Michael H. M. Chu , Caroline Ssu-Min Chen , Chiakang Sung
IPC分类号： G11C7/10
CPC分类号： G11C7/1075 , G06F13/161
摘要： An integrated circuit may include a memory controller serving as an interface between master processing modules and system memory. The master processing modules may provide memory access requests to the memory controller along with respective tag identifications. The memory controller may place the memory access requests in a queue for fulfillment. The memory controller may include a merging module that generates a memory access request to replace two or more memory access requests previously received from the master processing modules. The merging module may store information associated with the memory access requests that were merged and use the stored information to assign appropriate tag identifications to portions of data obtained from system memory when fulfilling the generated memory access request. The memory controller may include a verification module that can be used with test equipment to optimize the design of the master processing modules for improved memory access performance.
摘要翻译：集成电路可以包括用作主处理模块和系统存储器之间的接口的存储器控制器。主处理模块可以向存储器控制器提供存储器访问请求以及相应的标签标识。存储器控制器可以将存储器访问请求放置在队列中以实现。存储器控制器可以包括合并模块，其生成存储器访问请求以替换先前从主处理模块接收的两个或多个存储器访问请求。合并模块可以存储与被合并的存储器访问请求相关联的信息，并使用所存储的信息，以在满足生成的存储器访问请求时从系统存储器获得的数据部分分配适当的标签标识。存储器控制器可以包括可与测试设备一起使用的验证模块，以优化主处理模块的设计以改善存储器访问性能。

100. 发明授权

US08779754B2 Method and apparatus for minimizing skew between signals 有权
标题翻译：用于最小化信号之间的偏差的方法和装置
公开(公告)号：US08779754B2
公开(公告)日：2014-07-15
申请号：US13019277
申请日：2011-02-01
申请人： Yan Chong , Joseph Huang , Chiakang Sung , Eric Choong-Yin Chang , Peter Boyle , Adam J. Wright
发明人： Yan Chong , Joseph Huang , Chiakang Sung , Eric Choong-Yin Chang , Peter Boyle , Adam J. Wright
IPC分类号： H03K5/14 , H03K5/13 , H03K5/15
CPC分类号： H03K5/135 , G01R31/3016 , G01R31/31725 , G01R31/318516 , H03K5/14 , H03K5/1504
摘要： Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.
摘要翻译：使用延迟测量电路精确测量与各传输路径中的两个信号中的每一个相关的延迟，该延迟测量电路在实际设备上制造，其中制造用于传播两个信号的电路。因此，与两个信号中的每一个相关联的测量的延迟受到影响在设备操作期间两个信号将被传播的实际电路的相同制造相关属性。两个信号之间的偏差被量化为测量延迟的差。在两个信号中的每一个的传输路径内定义粗略和精细的延迟模块。基于两个信号之间的测量偏差，粗调和精细延迟模块被适当地设置以补偿偏斜。粗略和精细延迟模块的适当设置可以存储在非易失性存储器元件中。

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