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91. 发明申请

US20110153994A1 Multiplication Instruction for Which Execution Completes Without Writing a Carry Flag 有权
标题翻译：执行完成的乘法指令不写入进位标志
公开(公告)号：US20110153994A1
公开(公告)日：2011-06-23
申请号：US12645383
申请日：2009-12-22
申请人： Vinodh Gopal , James D. Guilford , Wajdi K. Feghali , Erdinc Ozturk , Gilbert M. Wolrich , Martin G. Dixon , Mark C. Davis , Sean P. Mirkes , Alexandre Farcy , Bret L. Toll , Maxim Loktyukhin
发明人： Vinodh Gopal , James D. Guilford , Wajdi K. Feghali , Erdinc Ozturk , Gilbert M. Wolrich , Martin G. Dixon , Mark C. Davis , Sean P. Mirkes , Alexandre Farcy , Bret L. Toll , Maxim Loktyukhin
IPC分类号： G06F9/302
CPC分类号： G06F9/30094 , G06F9/30014
摘要： A method in one aspect may include receiving a multiply instruction. The multiply instruction may indicate a first source operand and a second source operand. A product of the first and second source operands may be stored in one or more destination operands indicated by the multiply instruction. Execution of the multiply instruction may complete without writing a carry flag. Other methods are also disclosed, as are apparatus, systems, and instructions on machine-readable medium.
摘要翻译：一方面的方法可以包括接收乘法指令。乘法指令可以指示第一源操作数和第二源操作数。第一和第二源操作数的乘积可以存储在由乘法指令指示的一个或多个目的地操作数中。乘法指令的执行可以在不写进位标志的情况下完成。还公开了其它方法，以及机器可读介质上的装置，系统和指令。

92. 发明申请

US20110145683A1 Instruction-set architecture for programmable cyclic redundancy check (CRC) computations 有权
标题翻译：用于可编程循环冗余校验（CRC）计算的指令集架构
公开(公告)号：US20110145683A1
公开(公告)日：2011-06-16
申请号：US12653249
申请日：2009-12-10
申请人： Vinodh Gopal , Shay Gueron , Gilbert M. Wolrich , Wajdi K. Feghali , Kirk S. Yap , Bradley A. Burres
发明人： Vinodh Gopal , Shay Gueron , Gilbert M. Wolrich , Wajdi K. Feghali , Kirk S. Yap , Bradley A. Burres
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： G06F9/30145 , G06F9/30018 , G06F11/1004 , H03M13/09 , H03M13/091
摘要： A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction by storing the n-bit polynomial in one of two operands.
摘要翻译：提供了使用多个不同的n位多项式对数据块执行循环冗余校验（CRC）操作的方法和装置。灵活的CRC指令使用可编程的n位多项式来执行CRC操作。通过将n位多项式存储在两个操作数之一中，将n位多项式提供给CRC指令。

93. 发明授权

US07925011B2 Method for simultaneous modular exponentiations 有权
标题翻译：同时采用模幂分析的方法
公开(公告)号：US07925011B2
公开(公告)日：2011-04-12
申请号：US11610919
申请日：2006-12-14
申请人： Vinodh Gopal , Erdinc Ozturk , Kaan Yuksel , Gunnar Gaubatz , Wajdi Feghali , Gilbert M. Wolrich
发明人： Vinodh Gopal , Erdinc Ozturk , Kaan Yuksel , Gunnar Gaubatz , Wajdi Feghali , Gilbert M. Wolrich
IPC分类号： H04L9/00
CPC分类号： G06F7/723 , H04L9/302
摘要： The present disclosure provides a method for performing modular exponentiation. The method may include generating a first remainder (xp) based on an encrypted message (X) modulo a first prime number (p) and generating a second remainder (xq) based on the encrypted message (X) modulo a second prime number (q). The method may further include generating a third remainder (v1) based on the first remainder (xp) raised to a first private key number (d1) modulo the first prime number (p) and simultaneously generating a fourth remainder (v2) based on the second remainder (xq) raised to a second private key number (d2) modulo the second prime number (q). The method may also include subtracting the fourth remainder (v2) from the third remainder (v1) to yield a result (v1−v2) and multiplying the result (v1−v2) by a constant (c) to produce a second result. The method may additionally include generating a sixth remainder (h) by taking the second result modulo the first prime number (p) and multiplying the sixth remainder (h) by the second prime number (q) to produce a third result. The method may further include adding the third result and the fourth remainder (v2) to yield a final result (Y) and generating, at least in part, a public key based on the final result (Y). Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于执行模幂运算的方法。该方法可以包括基于第一素数（p）模数的加密消息（X）生成第一余数（xp），并且基于加密消息（X）生成第二余数（xq），第二素数（q））。该方法还可以包括：基于第一余数（xp）产生第三余数（v1），所述第一余数（xp）基于所述第一余数（xp）生成第一素数（p）的第一私钥数（d1）并同时生成第四余数第二余数（xq）升至第二素数（q）的第二私钥号（d2）。该方法还可以包括从第三余数（v1）中减去第四余数（v2）以产生结果（v1-v2）并将结果（v1-v2）乘以常数（c）以产生第二结果。该方法可以另外包括通过将第二结果以第一素数（p）取模并将第六余数（h）乘以第二素数（q）产生第三结果来产生第六余数（h）。该方法还可以包括添加第三结果和第四余数（v2）以产生最终结果（Y），并且至少部分地基于最终结果（Y）生成公钥。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

94. 发明授权

US07912886B2 Configurable exponent FIFO 有权
标题翻译：可配置指数FIFO
公开(公告)号：US07912886B2
公开(公告)日：2011-03-22
申请号：US11610841
申请日：2006-12-14
申请人： Vinodh Gopal , Wajdi Feghali , Gilbert M. Wolrich , Daniel Cutter , Robert P. Ottavi
发明人： Vinodh Gopal , Wajdi Feghali , Gilbert M. Wolrich , Daniel Cutter , Robert P. Ottavi
IPC分类号： G06F7/38 , H04K1/00 , H04L9/00 , H04L9/30
CPC分类号： G06F7/723
摘要： The present disclosure provides a system and method for performing modular exponentiation. The method includes loading a first word of a vector from memory into a first register and subsequently loading the first word from the first register to a second register. The method may also include loading a second word into the first register and loading at least one bit from the second register into an arithmetic logic unit. The method may further include performing modular exponentiation on the at least one bit to generate a result and generating a public key based upon, at least in part, the result. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于执行模幂运算的系统和方法。该方法包括将来自存储器的向量的第一字加载到第一寄存器中，并随后将第一个字从第一寄存器加载到第二寄存器。该方法还可以包括将第二字加载到第一寄存器中并将至少一个比特从第二寄存器加载到算术逻辑单元中。该方法还可以包括在至少一个比特上执行模幂运算以产生结果，并且至少部分地基于结果生成公开密钥。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

95. 发明授权

US07797612B2 Storage accelerator 有权
标题翻译：存储加速器
公开(公告)号：US07797612B2
公开(公告)日：2010-09-14
申请号：US11617966
申请日：2006-12-29
申请人： Vinodh Gopal , Yogesh Bansal , Gilbert M. Wolrich , Wajdi Feghali , Kirk Yap
发明人： Vinodh Gopal , Yogesh Bansal , Gilbert M. Wolrich , Wajdi Feghali , Kirk Yap
IPC分类号： G11C29/00
CPC分类号： G06F11/1076 , G06F2211/1057
摘要： The present disclosure provides a method for generating RAID syndromes. In one embodiment the method may include loading a first data byte of a first disk block and a first data byte of a second disk block from a storage device to an arithmetic logic unit. The method may further include XORing the first data byte of the first disk block and the first data byte of the second disk block to generate a first result and storing the first result in a results buffer. The method may also include iteratively repeating, loading intermediate data bytes corresponding to the first disk block and intermediate data bytes corresponding to the second disk block from the storage device to the arithmetic logic unit. The method may additionally include XORing the intermediate data bytes corresponding to the first disk block and the intermediate data bytes corresponding to the second disk block to generate intermediate results and generating a RAID syndrome based on, at least in part, the intermediate results. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于生成RAID综合征的方法。在一个实施例中，该方法可以包括将第一磁盘块的第一数据字节和第二磁盘块的第一数据字节从存储设备加载到算术逻辑单元。该方法还可以包括将第一磁盘块的第一数据字节和第二磁盘块的第一数据字节进行异或，以产生第一结果并将第一结果存储在结果缓冲器中。该方法还可以包括将对应于第一磁盘块的中间数据字节和对应于第二磁盘块的中间数据字节从存储设备反复重复加载到算术逻辑单元。该方法还可以包括对与第一磁盘块相对应的中间数据字节和对应于第二磁盘块的中间数据字节进行异或，以产生中间结果，并至少部分地基于中间结果生成RAID综合征。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

96. 发明授权

US07738657B2 System and method for multi-precision division 失效
标题翻译：多精度分割系统和方法
公开(公告)号：US07738657B2
公开(公告)日：2010-06-15
申请号：US11469243
申请日：2006-08-31
申请人： Vinodh Gopal , Matt Bace , Gunnar Gaubatz , Gilbert M. Wolrich
发明人： Vinodh Gopal , Matt Bace , Gunnar Gaubatz , Gilbert M. Wolrich
IPC分类号： H04L9/00
CPC分类号： G06F7/535 , G06F2207/3896
摘要： The present disclosure provides a system and method for performing multi-precision division. A method according to one embodiment may include generating a first product by multiplying a modulus having a most significant bit and/or a least significant bit equal to one and a quotient approximation of the modulus. The method may also include generating the 1's complement of the first product, generating a second product by multiplying the 1's complement and the quotient approximation, normalizing and truncating the second product to obtain a quotient, and storing the quotient in memory. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于执行多精度分割的系统和方法。根据一个实施例的方法可以包括通过将具有最高有效位和/或最低有效位的模数乘以等于1的模数和模量的商近似来生成第一乘积。该方法还可以包括生成第一产品的1的补码，通过乘以1的补码和商近似来生成第二乘积，归一化和截断第二乘积以获得商，并将商存储在存储器中。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

97. 发明授权

US07475229B2 Executing instruction for processing by ALU accessing different scope of variables using scope index automatically changed upon procedure call and exit 失效
标题翻译：通过ALU访问使用范围索引访问不同范围的变量的执行指令在过程调用和退出时自动更改
公开(公告)号：US07475229B2
公开(公告)日：2009-01-06
申请号：US11354670
申请日：2006-02-14
申请人： Wajdi K. Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel F. Cutter , Vinodh Gopal , Gunnar Gaubatz
发明人： Wajdi K. Feghali , William C. Hasenplaugh , Gilbert M. Wolrich , Daniel F. Cutter , Vinodh Gopal , Gunnar Gaubatz
IPC分类号： G06F9/302
CPC分类号： G06F21/602
摘要： In general, in one aspect, the disclosure describes a processing unit that includes a memory, an arithmetic logic unit, and control logic having access to program instructions of a control store. The control logic includes logic to access multiple sets of variables, variables in the different sets of variables being identically referenced by instructions, associate a one of the sets of variables as the current set of variables to be used in instructions that are executed by the arithmetic logic unit, change the set of variables associated with the current set of variables in response to a procedure call or exit, and alter the value of a variable of a set of the variables other than the set of variables associated with the current set of variables in response to an instruction.
摘要翻译：通常，在一个方面，本公开描述了一种处理单元，其包括存储器，算术逻辑单元和具有访问控制存储器的程序指令的控制逻辑。控制逻辑包括访问多组变量的逻辑，不同变量集合中的变量由指令相同地引用，将变量集合中的一个与当前由算术执行的指令中使用的变量集合相关联逻辑单元，响应于过程调用或退出而改变与当前变量集相关联的变量集合，并且改变一组变量的值，而不是与当前变量集合相关联的变量集合响应一个指令。

98. 发明授权

US08041945B2 Method and apparatus for performing an authentication after cipher operation in a network processor 有权
标题翻译：在网络处理器中进行密码操作之后进行认证的方法和装置
公开(公告)号：US08041945B2
公开(公告)日：2011-10-18
申请号：US12455038
申请日：2009-05-27
申请人： Jaroslaw J. Sydir , Kamal J. Koshy , Wajdi Feghali , Bradley A. Burres , Gilbert M. Wolrich
发明人： Jaroslaw J. Sydir , Kamal J. Koshy , Wajdi Feghali , Bradley A. Burres , Gilbert M. Wolrich
IPC分类号： H04L29/06
CPC分类号： H04L63/0485 , H04L9/0643 , H04L63/12 , H04L2209/125
摘要： A method and apparatus is described for processing of network data packets by a network processor having cipher processing cores and authentication processing cores which operate on data within the network data packets, in order to provide a one-pass ciphering and authentication processing of the network data packets.
摘要翻译：描述了一种方法和装置，用于通过具有对网络数据分组内的数据进行操作的密码处理核和认证处理核的网络处理器来处理网络数据分组，以便提供网络数据的一次通过加密和认证处理数据包

99. 发明授权

US07434221B2 Multi-threaded sequenced receive for fast network port stream of packets 有权
标题翻译：多线程排序接收快速网络端口流数据包
公开(公告)号：US07434221B2
公开(公告)日：2008-10-07
申请号：US11239547
申请日：2005-09-28
申请人： Donald F. Hooper , Matthew J. Adiletta , Gilbert M. Wolrich
发明人： Donald F. Hooper , Matthew J. Adiletta , Gilbert M. Wolrich
IPC分类号： G06F9/46
CPC分类号： G06F9/546 , G06F9/3851 , G06F9/3885 , G06F9/485 , G06F9/4881 , G06F9/544
摘要： A method of processing network data in a network processor includes using three or more threads to process a beginning portion, a middle portion, and an end portion of data packet is presented. The first thread processes the beginning portion; one or more middle threads process the middle portion, and a last thread processes the end portion. First information is indirectly passed from the first thread to the last thread via a first buffer with the middle threads progressively updating the first information. Second information is directly passed from the first thread to the last thread via a second buffer.
摘要翻译：一种在网络处理器中处理网络数据的方法包括使用三个或更多个线程来处理数据分组的开始部分，中间部分和结束部分。第一个线程处理起始部分; 一个或多个中间线程处理中间部分，最后一个线程处理端部。第一个信息通过第一个缓冲区从第一个线程间接传递到最后一个线程，中间线程逐渐更新第一个信息。第二个信息通过第二个缓冲区从第一个线程直接传递到最后一个线程。

100. 发明申请

US20080159528A1 Method for Processing Multiple Operations 有权
标题翻译：多操作处理方法
公开(公告)号：US20080159528A1
公开(公告)日：2008-07-03
申请号：US11617418
申请日：2006-12-28
申请人： Wajdi Feghali , Stephanie Hirnak , Makaram Raghunandan , Yogesh Bansal , Kirk Yap , Gilbert M. Wolrich
发明人： Wajdi Feghali , Stephanie Hirnak , Makaram Raghunandan , Yogesh Bansal , Kirk Yap , Gilbert M. Wolrich
IPC分类号： H04L9/30 , H04L9/28
CPC分类号： H04L63/0485 , G06F9/30181 , G06F9/3879 , H04L63/08
摘要： In one embodiment, the present disclosure provides a method capable of processing a variety of different operations. A method according to one embodiment may include loading configuration data from a shared memory unit into a hardware configuration register, the hardware configuration register located within circuitry included within a hardware accelerator unit. The method may also include issuing a command set from a microengine to the hardware accelerator unit having the circuitry. The method may additionally include receiving the command set at the circuitry from the microengine, the command set configured to allow for the processing of a variety of different operations. The method may further include processing an appropriate operation based upon the configuration data loaded into the hardware configuration register. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：在一个实施例中，本公开提供了一种能够处理各种不同操作的方法。根据一个实施例的方法可以包括将配置数据从共享存储器单元加载到硬件配置寄存器中，硬件配置寄存器位于包括在硬件加速器单元内的电路内。该方法还可以包括从微引擎向具有该电路的硬件加速器单元发出命令集。该方法可以另外包括接收来自微引擎的电路处的命令集，该命令集被配置为允许处理各种不同的操作。该方法还可以包括基于加载到硬件配置寄存器中的配置数据来处理适当的操作。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

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