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91. 发明授权

US06465364B2 Method for fabrication of a contact plug in an embedded memory 有权
标题翻译：在嵌入式存储器中制造接触插塞的方法
公开(公告)号：US06465364B2
公开(公告)日：2002-10-15
申请号：US09764328
申请日：2001-01-19
申请人： Sun-Chieh Chien , Chien-Li Kuo
发明人： Sun-Chieh Chien , Chien-Li Kuo
IPC分类号： H01L2100
CPC分类号： H01L27/11526 , H01L21/28518 , H01L21/76895 , H01L27/105 , H01L27/10873 , H01L27/10894 , H01L27/11546
摘要： The present invention provides a method for the formation of contact plugs of an embedded memory. The method first forms a plurality of MOS transistors on a defined memory array region and periphery circuit region of the semiconductor wafer. Then, a first dielectric layer is formed on the memory array region, and plurality of landing pads is formed in the first dielectric layer. Next, both a stop layer and a second dielectric layer are formed, respectively, on the surface of semiconductor wafer. A PEP process is then used to form a plurality of contact plug holes in the second dielectric layer in both the memory array region and the periphery circuit region. Finally, a conductive layer is filled into each hole to form in-situ each contact plug in both the memory array region and the periphery circuit region.
摘要翻译：本发明提供一种用于形成嵌入式存储器的接触塞的方法。该方法首先在半导体晶片的限定的存储器阵列区域和外围电路区域上形成多个MOS晶体管。然后，在存储器阵列区域上形成第一电介质层，并且在第一介电层中形成多个着陆焊盘。接下来，在半导体晶片的表面上分别形成停止层和第二电介质层。然后使用PEP工艺在存储器阵列区域和外围电路区域中的第二介电层中形成多个接触插塞孔。最后，将导电层填充到每个孔中，以在存储器阵列区域和外围电路区域中的原位形成每个接触插塞。

92. 发明授权

US06406968B1 Method of forming dynamic random access memory 失效
标题翻译：形成动态随机存取存储器的方法
公开(公告)号：US06406968B1
公开(公告)日：2002-06-18
申请号：US09767499
申请日：2001-01-23
申请人： Sun-Chieh Chien , Chien-Li Kuo
发明人： Sun-Chieh Chien , Chien-Li Kuo
IPC分类号： H01L2120
CPC分类号： H01L27/10894 , H01L21/76895 , H01L27/10855 , H01L28/60 , H01L28/90
摘要： A method of forming a dynamic random access memory. A substrate having a memory cell region and a logic circuit region is provided. The substrate also has a first dielectric layer thereon. The first dielectric layer in the memory cell region has a bit line and a node contact while the first dielectric layer in the logic circuit region has a first metallic interconnect. An intermediate dielectric layer is formed over the first dielectric layer such that the intermediate dielectric layer in the logic circuit region has a second metallic interconnect that connects electrically with the first metallic interconnect. A capacitor is formed in the intermediate dielectric layer within the memory cell region. A second dielectric layer is formed over the substrate. A third metallic interconnect is formed in the second dielectric layer such that the third metallic interconnect and the second metallic interconnect are electrically connected.
摘要翻译：一种形成动态随机存取存储器的方法。提供具有存储单元区域和逻辑电路区域的衬底。衬底上也具有第一介电层。存储单元区域中的第一介电层具有位线和节点接触，而逻辑电路区域中的第一介电层具有第一金属互连。中间电介质层形成在第一电介质层上，使得逻辑电路区域中的中间介电层具有与第一金属互连电连接的第二金属互连。在存储单元区域内的中间介质层中形成电容器。第二介质层形成在衬底上。在第二电介质层中形成第三金属互连，使得第三金属互连和第二金属互连电连接。

93. 发明授权

US06329283B1 Method of fabricating self-align-contact 有权
标题翻译：制造自对准接触的方法
公开(公告)号：US06329283B1
公开(公告)日：2001-12-11
申请号：US09522868
申请日：2000-03-09
申请人： Chien-Li Kuo
发明人： Chien-Li Kuo
IPC分类号： H01L214763
CPC分类号： H01L21/76897
摘要： A method of fabricating a self-align-contact is provided. A first gate and a second gate are formed on a semiconductor substrate. A spacer is formed on the sidewalls of the first gate and the second gate, and a source/drain region is formed between the first gate and the second gate. A dielectric layer is formed on the first gate, the second gate, the source/drain region, the spacer, and the semiconductor substrate. A self-align-contact opening is formed in the dielectric layer to expose the source/drain region. A metal silicide layer is formed on the source/drain region. A first conductive layer, such as doped polysilicon, is formed on the metal silicide layer and in the self-align-contact opening. A second conductive layer is formed on the first conductive layer, and the first conductive layer and the second conductive layer are patterned.
摘要翻译：提供了制造自对准接触的方法。第一栅极和第二栅极形成在半导体衬底上。在第一栅极和第二栅极的侧壁上形成间隔物，并且在第一栅极和第二栅极之间形成源极/漏极区域。在第一栅极，第二栅极，源极/漏极区域，间隔物和半导体衬底上形成介电层。在电介质层中形成自对准接触开口以暴露源极/漏极区域。在源极/漏极区域上形成金属硅化物层。在金属硅化物层和自对准接触开口中形成第一导电层，例如掺杂多晶硅。在第一导电层上形成第二导电层，并且对第一导电层和第二导电层进行图案化。

94. 发明授权

US06277727B1 Method of forming a landing pad on a semiconductor wafer 有权
标题翻译：在半导体晶片上形成着陆焊盘的方法
公开(公告)号：US06277727B1
公开(公告)日：2001-08-21
申请号：US09421247
申请日：1999-10-20
申请人： Chien-Li Kuo , Jung-Chao Chiou
发明人： Chien-Li Kuo , Jung-Chao Chiou
IPC分类号： H01L214763
CPC分类号： H01L21/76804 , H01L21/76895
摘要： This invention relates to a method of forming a landing pad on a semiconductor wafer comprising a silicon substrate, a dielectric layer, a passivation layer and a photo-resist layer. The photo-resist layer comprises a hole penetrating to the surface of the passivation layer which defines the position of the landing pad. An anisotropic etching through the hole is performed to vertically remove the passivation layer and a predetermined thickness of the dielectric layer under the hole to form a recess, and then the photo-resist layer is removed. A filling layer is deposited on the passivation layer and the recess. An etch-back process is performed to remove the filling layer on the bottom portion of the recess and form a circular spacer on the surrounding portion of the recess. Another anisotropic etching is performed to vertically remove the dielectric layer under the recess and down to the surface of the silicon substrate which forms a plug hole, over which the circular spacer is used as a hard mask. Lastly, a conductive layer is deposited to completely fill the recess and the plug hole which forms the landing pad.
摘要翻译：本发明涉及一种在包括硅衬底，电介质层，钝化层和光致抗蚀剂层的半导体晶片上形成着陆焊盘的方法。光致抗蚀剂层包括穿透钝化层的表面的孔，其限定着陆垫的位置。进行通过孔的各向异性蚀刻，以垂直去除钝化层和孔下面的介电层的预定厚度以形成凹部，然后除去光致抗蚀剂层。填充层沉积在钝化层和凹部上。执行回蚀处理以去除凹部的底部上的填充层，并在凹部的周围部分上形成圆形间隔物。进行另一种各向异性蚀刻以垂直移除凹陷下方的电介质层，并向下移动到形成插塞孔的硅衬底的表面，使用圆形间隔物作为硬掩模。最后，沉积导电层以完全填充形成着陆垫的凹部和插塞孔。

95. 发明授权

US06268256B1 Method for reducing short channel effect 失效
标题翻译：减少短信道效应的方法
公开(公告)号：US06268256B1
公开(公告)日：2001-07-31
申请号：US09484788
申请日：2000-01-18
申请人： Chien-Li Kuo
发明人： Chien-Li Kuo
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/26533 , H01L29/1083
摘要： A method for reducing the short channel effect of a metal-oxide-semiconductor device by forming a pocket region in a substrate is disclosed, in which the substrate has a channel region under the gate of the device, the channel region has an anti-punch-through region formed thereunder, and a lightly-doped drain region is under the edge portion of the gate. The method includes implanting silicon at a region between the anti-punch-through region and a pre-defined source/drain region to form a point defect region under the lightly-doped drain region, and annealing the substrate such that the dopant in the anti-punch-through region diffuses into the point defect region.
摘要翻译：公开了一种通过在衬底中形成凹穴区域来减小金属氧化物半导体器件的短沟道效应的方法，其中衬底在器件的栅极下方具有沟道区域，沟道区域具有抗冲击贯通区域，并且轻掺杂漏极区域在栅极的边缘部分的下方。该方法包括在抗穿通区域和预定义的源极/漏极区域之间的区域处注入硅以在轻掺杂漏极区域下形成点缺陷区域，并且退火衬底，使得反型穿透区域扩散到点缺陷区域。

96. 发明授权

US06248623B1 Method for manufacturing embedded memory with different spacer widths 有权
标题翻译：制造具有不同间隔宽度的嵌入式存储器的方法
公开(公告)号：US06248623B1
公开(公告)日：2001-06-19
申请号：US09439170
申请日：1999-11-12
申请人： Sun-Chieh Chien , Chien-Li Kuo
发明人： Sun-Chieh Chien , Chien-Li Kuo
IPC分类号： H01L28242
CPC分类号： H01L27/10894 , H01L21/823425 , H01L21/823468 , H01L27/10855 , H01L27/10873 , H01L27/10888
摘要： A method of manufacturing an embedded memory. A substrate has a memory cell region and a logic circuit region. A plurality of first gate structures and a plurality of second gate structures are respectively formed on the substrate in the memory cell region and the logic circuit region. Every space between the first gate structures is smaller than those between the second gate structures. A first spacer is formed over a sidewall of each first gate structure and over a sidewall of each second gate structure. Several lightly doped drain regions are formed in the substrate exposed by the first spacers and the second gate structures in the logic circuit region. A second spacer is formed on each first spacer in the logic circuit region and a silicide block is simultaneously formed to fill space between the first gate structures in the memory cell region. A source/drain region is formed in the substrate exposed by the second spacers, the first spacers and the second gate structures in the logic circuit region. A silicide layer is formed on the substrate exposed by the second spacers, the first spacers and the second gate structures in the logic circuit region.
摘要翻译：一种制造嵌入式存储器的方法。衬底具有存储单元区域和逻辑电路区域。多个第一栅极结构和多个第二栅极结构分别形成在存储单元区域和逻辑电路区域中的衬底上。第一栅极结构之间的每个空间都小于第二栅极结构之间的间隔。在每个第一栅极结构的侧壁上并且在每个第二栅极结构的侧壁之上形成第一间隔物。在由第一间隔物和逻辑电路区域中的第二栅极结构暴露的衬底中形成几个轻掺杂漏极区。在逻辑电路区域中的每个第一间隔物上形成第二间隔物，同时形成硅化物块以填充存储单元区域中的第一栅极结构之间的空间。源极/漏极区域形成在由第二间隔物暴露的衬底中，第一间隔物和第二栅极结构在逻辑电路区域中。在由第二间隔物暴露的衬底上形成硅化物层，在逻辑电路区域中形成第一间隔物和第二栅极结构。

97. 发明授权

US06159850A Method for reducing resistance of contact window 有权
标题翻译：降低接触窗电阻的方法
公开(公告)号：US06159850A
公开(公告)日：2000-12-12
申请号：US130944
申请日：1998-08-07
申请人： Tzung-Han Lee , Chien-Li Kuo
发明人： Tzung-Han Lee , Chien-Li Kuo
IPC分类号： H01L21/285 , H01L21/60 , H01L21/44
CPC分类号： H01L21/76897 , H01L21/28512
摘要： A method of reducing resistance of a contact. A semiconductor substrate having at least a conductive lines formed thereon is provided. A self-aligned contact window is formed to expose a part of the substrate. A recess with a ragged surface is formed on the exposed part of substrate within the contact window.
摘要翻译：降低接触电阻的方法。提供了至少形成有导线的半导体基板。形成自对准的接触窗以露出基底的一部分。在接触窗内的基板的暴露部分上形成具有不规则表面的凹部。

98. 发明授权

US6083847A Method for manufacturing local interconnect 失效
标题翻译：本地互连方法
公开(公告)号：US6083847A
公开(公告)日：2000-07-04
申请号：US998771
申请日：1997-12-29
申请人： Chien-Li Kuo
发明人： Chien-Li Kuo
IPC分类号： H01L21/768 , H01L21/28
CPC分类号： H01L21/76895
摘要： A method for manufacturing local interconnects includes providing a substrate with a gate oxide layer thereover, a first gate electrode and a second gate electrode above the gate oxide layer, spacers on the sidewalls of the gate electrodes, including a first spacer on one sidewall of the first gate electrode and a second spacer on the other sidewall of the first gate electrode. Then, a photoresist layer is applied while keeping the first spacer exposed. Subsequently, the first spacer is removed to expose the sidewall of the first gate electrode. Then, a metal silicide layer is formed over the first gate electrode, the second gate electrode, the one sidewall of the first gate electrode and the substrate. Wet etching is used to remove the first spacer so that local interconnects are automatically formed after the self-aligned silicide processing operation.
摘要翻译：一种用于制造局部互连的方法包括在其上提供栅极氧化物层的衬底，栅极氧化物层上方的第一栅极电极和第二栅极电极，栅电极的侧壁上的间隔物，包括位于栅电极的一个侧壁上的第一间隔物第一栅电极和在第一栅电极的另一侧壁上的第二间隔物。然后，在保持第一间隔物暴露的同时施加光致抗蚀剂层。随后，去除第一间隔物以露出第一栅电极的侧壁。然后，在第一栅电极，第二栅极电极，第一栅电极的一个侧壁和基板上形成金属硅化物层。使用湿蚀刻来去除第一间隔物，使得在自对准硅化物处理操作之后自动形成局部互连。

99. 发明授权

US6043116A Method of fabricating self-align-contact 失效
标题翻译：制造自对准接触的方法
公开(公告)号：US6043116A
公开(公告)日：2000-03-28
申请号：US93984
申请日：1998-06-09
申请人： Chien-Li Kuo
发明人： Chien-Li Kuo
IPC分类号： H01L21/60 , H01L21/8234 , H01L21/8238 , H01L21/336
CPC分类号： H01L21/76897 , H01L21/823425
摘要： A method of fabricating a self-align-contact is provided. Two gates are formed on a semiconductor substrate. A first spacer is formed on the sidewalls of the two gates, and a source/drain region is formed between the two gates. A first dielectric layer and a second dielectric layer are formed on the semiconductor substrate. The second dielectric layer is patterned. A self-align-contact opening is formed between the two gates by removing the first dielectric layer and the first spacer using the second dielectric layer as a mask. A second spacer is formed on the exposed sidewalls of the gate. The method of forming the second spacer includes forming an insulating layer that is about 200-100 .ANG. thick and anisotropically etching the insulating layer. The width of the second spacer is narrower than the width of the first spacer. A conductor layer is formed in the self-align-contact opening.
摘要翻译：提供了制造自对准接触的方法。在半导体衬底上形成两个栅极。在两个栅极的侧壁上形成第一间隔物，并且在两个栅极之间形成源极/漏极区域。第一电介质层和第二电介质层形成在半导体衬底上。图案化第二电介质层。通过使用第二介电层作为掩模去除第一介电层和第一间隔物，在两个栅极之间形成自对准接触开口。在栅极的暴露的侧壁上形成第二间隔物。形成第二间隔物的方法包括形成约200-100厚的绝缘层，并各向异性地蚀刻绝缘层。第二间隔物的宽度比第一间隔物的宽度窄。在自对准接触开口中形成导体层。

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