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91. 发明授权

US6037018A Shallow trench isolation filled by high density plasma chemical vapor deposition 失效
标题翻译：通过高密度等离子体化学气相沉积填充的浅沟槽隔离
公开(公告)号：US6037018A
公开(公告)日：2000-03-14
申请号：US108866
申请日：1998-07-01
申请人： Syun-Ming Jang , Chu-Yun Fu , Chen-Hua Douglas Yu
发明人： Syun-Ming Jang , Chu-Yun Fu , Chen-Hua Douglas Yu
IPC分类号： C23C16/40 , H01L21/762 , B05D3/06 , H01L21/76
CPC分类号： H01L21/76232 , C23C16/402
摘要： A method for filling shallow trenches 28 with a HDPCVD oxide 50. The invention has two liners: (a) a thermal oxide liner 36 and (b) an overlying conformal O.sub.3 -TEOS protective liner 40. The O.sub.3 -TEOS protective liner 40 prevents the HDPCVD oxide 50 from sputter damaging the trench sidewalls and the masking layer 24. The O.sub.3 -TEOS layer has novel process temperature (400 to 560.degree. C.) and low pressure (40 to 80 torr) that allows the O.sub.3 -TEOS layer to deposit uniformly over thermal oxide liner 36. The method begins by forming pad oxide layer 20 and a barrier layer 24 over a substrate. A trench 28 is formed in the substrate 10 through the pad oxide layer 20 and the barrier layer 24. A thermal oxide liner 36 and a protective O.sub.3 -TEOS liner layer 40 are formed over the walls of the trench 28 and over the barrier layer 24. Lastly, a high density plasma chemical vapor deposition (HDPCVD) oxide layer 50 is formed over the protective liner layer 40 filling the trench 28.
摘要翻译：用HDPCVD氧化物50填充浅沟槽28的方法。本发明具有两个衬垫：（a）热氧化物衬垫36和（b）上覆的共形O3-TEOS保护衬垫40.O3-TEOS保护衬垫40防止 HDPCVD氧化物50从溅射破坏沟槽侧壁和掩模层24.O3-TEOS层具有新的工艺温度（400至560℃）和低压（40至80托），允许O 3 -TEOS层沉积该方法开始于在衬底上形成衬垫氧化物层20和阻挡层24。沟槽28通过衬垫氧化物层20和阻挡层24形成在衬底10中。热氧化物衬里36和保护性O 3 -TEOS衬里层40形成在沟槽28的壁上并且在阻挡层24上方最后，在填充沟槽28的保护衬垫层40之上形成高密度等离子体化学气相沉积（HDPCVD）氧化物层50。

92. 发明授权

US6010948A Shallow trench isolation process employing a BPSG trench fill 有权
标题翻译：采用BPSG沟槽填充的浅沟槽隔离工艺
公开(公告)号：US6010948A
公开(公告)日：2000-01-04
申请号：US244879
申请日：1999-02-05
申请人： Chen-Hua Yu , Syun-Ming Jang
发明人： Chen-Hua Yu , Syun-Ming Jang
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： A process for creating BPSG filled, shallow trench isolation regions, in a semiconductor substrate, has been developed. The process features the use of a BPSG layer with about 4 to 4.5 weight percent B.sub.2 O.sub.3, and about 4 to 4.5 weight percent P.sub.2 O.sub.5, in silicon oxide. This BPSG composition, when subjected to a high temperature anneal procedure, results in softening, or reflowing, of the BPSG layer, eliminating seams or voids, in the BPSG layer, that may have been present after BPSG deposition. The removal rate of BPSG, is lower than the removal rate of silicon oxide layer, in buffered HF solutions, thus allowing several buffered HF procedures to be performed without recessing of BPSG in the shallow trench. In addition this composition of BPSG performs as a gettering material for mobile ions, thus contributing to yield and reliability improvements, when used at the isolation region for MOSFET devices.
摘要翻译：已经开发了用于在半导体衬底中产生BPSG填充的浅沟槽隔离区的工艺。该方法的特征在于在氧化硅中使用具有约4至4.5重量％的B 2 O 3和约4至4.5重量％的P 2 O 5的BPSG层。当经过高温退火过程时，该BPSG组合物导致BPSG层的软化或回流，消除了在BPSG沉积后可能存在的BPSG层中的接缝或空隙。 BPSG的去除率低于缓冲HF溶液中氧化硅层的去除率，从而允许在浅沟槽中不进行BPSG的凹陷而执行几个缓冲的HF程序。此外，BPSG的这种组合作为移动离子的吸气材料，当在MOSFET器件的隔离区域使用时，有助于提高产量和可靠性。

93. 发明授权

US5968687A Mask for recovering alignment marks after chemical mechanical polishing 有权
标题翻译：化学机械抛光后恢复对准标记的面膜
公开(公告)号：US5968687A
公开(公告)日：1999-10-19
申请号：US196601
申请日：1998-11-20
申请人： Jui-Yu Chang , Chunshing Chen , Syun-Ming Jang , Ying-Ho Chen
发明人： Jui-Yu Chang , Chunshing Chen , Syun-Ming Jang , Ying-Ho Chen
IPC分类号： H01L23/544 , G03F9/00
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2223/54493 , H01L2924/0002
摘要： A mask pattern and method are described for the recovery of alignment marks on an integrated circuit wafer without the use of additional masks. The mask pattern and method provide means to recover the alignment marks after forming a metal layer on a planarized inter-level dielectric layer. The pattern which conventional methods have placed on a separate mask is formed in the end regions of a mask used for forming a pattern on the active region of the wafer. In order to fit the pattern in the end regions of the mask the pattern is divided into two parts. When the pattern is used to expose a layer of photoresist two exposure steps are used.
摘要翻译：描述了用于在集成电路晶片上恢复对准标记的掩模图案和方法，而不使用附加掩模。掩模图案和方法提供了在平坦化的层间电介质层上形成金属层之后恢复对准标记的装置。在用于在晶片的有源区上形成图案的掩模的端部区域中形成常规方法已经放置在单独的掩模上的图案。为了将图案装配在掩模的端部区域中，图案被分为两部分。当使用图案曝光一层光致抗蚀剂时，使用两个曝光步骤。

94. 发明授权

US5955787A Method for forming intermetal dielectric with SOG etchback and CMP 失效
标题翻译：用SOG回蚀和CMP形成金属间电介质的方法
公开(公告)号：US5955787A
公开(公告)日：1999-09-21
申请号：US892220
申请日：1997-07-14
申请人： Chen-Hua Douglas Yu , Syun-Ming Jang
发明人： Chen-Hua Douglas Yu , Syun-Ming Jang
IPC分类号： H01L21/768 , H01L23/532 , H01L21/441
CPC分类号： H01L21/76801 , H01L21/76832 , H01L21/76834 , H01L21/76837 , H01L23/5329 , H01L2924/0002
摘要： A defect free intermetal dielectric, IMD, and method of forming the defect free IMD are described. The IMD uses spacers formed by means of etchback of a layer of spin-on-glass, SOG. In order to use an oxide layer formed by means of plasma enhanced tetra-ethyl-ortho-silicate, PE-TEOS, as part of the IMD an oxide cap layer formed using plasma enhanced chemical vapor deposition, PE-CVD, is used to isolate the SOG spacers from the PE-TEOS formed oxide layer. By isolating the PE-TEOS formed oxide layer from the SOG spacers a reliable and defect free IMD is achieved.
摘要翻译：描述了无缺陷的金属间电介质，IMD和形成无缺陷IMD的方法。 IMD使用通过回转一层旋涂玻璃（SOG）形成的间隔物。为了使用通过等离子体增强的四乙基原硅酸盐形成的氧化物层，PE-TEOS作为IMD的一部分，使用等离子体增强化学气相沉积形成的氧化物覆盖层PE-CVD用于分离来自PE-TEOS形成的氧化物层的SOG间隔物。通过从SOG间隔隔离PE-TEOS形成的氧化物层，实现可靠且无缺陷的IMD。

95. 发明授权

US08962484B2 Method of forming pattern for semiconductor device 有权
标题翻译：半导体器件形成方法
公开(公告)号：US08962484B2
公开(公告)日：2015-02-24
申请号：US13328680
申请日：2011-12-16
申请人： Chia Ying Lee , Chih-Yuan Ting , Jyu-Horng Shieh , Minghsing Tsai , Syun-Ming Jang
发明人： Chia Ying Lee , Chih-Yuan Ting , Jyu-Horng Shieh , Minghsing Tsai , Syun-Ming Jang
IPC分类号： H01L21/32 , H01L21/311 , H01L21/033 , H01L21/308
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/32
摘要： The present disclosure provides a method including providing a semiconductor substrate and forming a first layer and a second layer on the semiconductor substrate. The first layer is patterned to provide a first element, a second element, and a space interposing the first and second elements. Spacer elements are then formed on the sidewalls on the first and second elements of the first layer. Subsequently, the second layer is etched using the spacer elements and the first and second elements as a masking element.
摘要翻译：本公开提供了一种方法，包括提供半导体衬底并在半导体衬底上形成第一层和第二层。图案化第一层以提供第一元件，第二元件和插入第一元件和第二元件的空间。然后在第一层的第一和第二元件的侧壁上形成间隔元件。随后，使用间隔元件和第一和第二元素作为掩模元件来蚀刻第二层。

96. 发明申请

US20130330906A1 METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION 有权
标题翻译：半导体集成电路制造方法
公开(公告)号：US20130330906A1
公开(公告)日：2013-12-12
申请号：US13490635
申请日：2012-06-07
申请人： Weibo Yu , Ming-His Yeh , Chih-Tang Peng , Hao-Ming Lien , Chao-Cheng Chen , Syun-Ming Jang
发明人： Weibo Yu , Ming-His Yeh , Chih-Tang Peng , Hao-Ming Lien , Chao-Cheng Chen , Syun-Ming Jang
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L29/66795
摘要： A method of fabricating a semiconductor IC is disclosed. The method includes receiving a device. The device includes a semiconductor substrate, a plurality of fins and trenches between fins in the semiconductor substrate. The method also includes filling the trenches with a dielectric material to form shallow trench isolations (STI), applying a low-thermal-budget annealing to the dielectric material, and applying a wet-treatment to the dielectric material.
摘要翻译：公开了制造半导体IC的方法。该方法包括接收设备。该器件包括半导体衬底，半导体衬底中的翅片之间的多个散热片和沟槽。该方法还包括用介电材料填充沟槽以形成浅沟槽隔离（STI），对介电材料施加低热预算退火，以及对电介质材料进行湿法处理。

97. 发明申请

US20130078809A1 SILICON NITRIDE ETCHING IN A SINGLE WAFER APPARATUS 有权
标题翻译：硅酸盐蚀刻在一个单一的WAFER装置
公开(公告)号：US20130078809A1
公开(公告)日：2013-03-28
申请号：US13244337
申请日：2011-09-24
申请人： Weibo Yu , Hsueh-Chin Lu , Han-Guan Chew , Kuo Bin Huang , Chao-Cheng Chen , Syun-Ming Jang
发明人： Weibo Yu , Hsueh-Chin Lu , Han-Guan Chew , Kuo Bin Huang , Chao-Cheng Chen , Syun-Ming Jang
IPC分类号： H01L21/306
CPC分类号： H01L21/6708 , H01L21/31111
摘要： A single wafer etching apparatus and various methods implemented in the single wafer etching apparatus are disclosed. In an example, etching a silicon nitride layer in a single wafer etching apparatus includes: heating a phosphoric acid to a first temperature; heating a sulfuric acid to a second temperature; mixing the heated phosphoric acid and the heated sulfuric acid; heating the phosphoric acid/sulfuric acid mixture to a third temperature; and etching the silicon nitride layer with the heated phosphoric acid/sulfuric acid mixture.
摘要翻译：公开了在单晶片蚀刻装置中实现的单晶片蚀刻装置和各种方法。在一个实施例中，在单晶片蚀刻装置中蚀刻氮化硅层包括：将磷酸加热到第一温度; 将硫酸加热至第二温度; 混合加热的磷酸和加热的硫酸; 将磷酸/硫酸混合物加热至第三温度; 并用加热的磷酸/硫酸混合物蚀刻氮化硅层。

98. 发明授权

US08368220B2 Anchored damascene structures 有权
标题翻译：锚定镶嵌结构
公开(公告)号：US08368220B2
公开(公告)日：2013-02-05
申请号：US11252498
申请日：2005-10-18
申请人： David Lu , Horng-Huei Tseng , Syun-Ming Jang
发明人： David Lu , Horng-Huei Tseng , Syun-Ming Jang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76802 , H01L21/76807 , H01L21/76816 , H01L21/76831 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An anchored conductive damascene buried in a multi-density dielectric layer and method for forming the same, the anchored conductive damascene including a dielectric layer with an opening extending through a thickness of the dielectric layer; wherein the dielectric layer comprises at least one relatively higher density portion and a relatively lower density portion, the relatively lower density portion forming a contiguous major portion of the dielectric layer; and, wherein the opening in the relatively lower density portion has a lateral dimension relatively larger compared to the relatively higher density portion to form anchoring steps.
摘要翻译：埋置在多密度电介质层中的锚定导电镶嵌体及其形成方法，所述锚定导电镶嵌体包括具有延伸穿过介电层厚度的开口的介电层; 其中所述电介质层包括至少一个相对较高密度的部分和相对较低的密度部分，所述较低密度部分形成所述电介质层的连续主要部分; 并且其中相对较低密度部分中的开口具有与相对较高密度部分相比较大的横向尺寸以形成锚固步骤。

99. 发明申请

US20120319278A1 GAP FILLING METHOD FOR DUAL DAMASCENE PROCESS 有权
标题翻译： GAP填充方法双重DAMASCENE过程
公开(公告)号：US20120319278A1
公开(公告)日：2012-12-20
申请号：US13161701
申请日：2011-06-16
申请人： Chun-Chieh Lin , Hung-Wen Su , Minghsing Tsai , Syun-Ming Jang
发明人： Chun-Chieh Lin , Hung-Wen Su , Minghsing Tsai , Syun-Ming Jang
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76877 , H01L21/76807 , H01L21/7681 , H01L21/76831 , H01L21/76834 , H01L21/76846 , H01L21/76885 , H01L23/5226 , H01L23/528 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L29/511 , H01L2221/1031 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括形成具有多个第一开口的图案化电介质层。该方法包括在图案化的介电层上形成导电衬垫层，导电衬垫层部分填充第一开口。该方法包括在第一开口之外的导电衬垫层的部分上形成沟槽掩模层，从而形成多个第二开口，其中一部分形成在第一开口上。该方法包括在第一开口中沉积导电材料以形成多个通孔，并且在第二开口中形成多个金属线。该方法包括去除沟槽掩模层。

100. 发明授权

US08264046B2 Synergy effect of alloying materials in interconnect structures 有权
标题翻译：合金材料在互连结构中的协同作用
公开(公告)号：US08264046B2
公开(公告)日：2012-09-11
申请号：US12619484
申请日：2009-11-16
申请人： Hui-Lin Chang , Yung-Cheng Lu , Syun-Ming Jang
发明人： Hui-Lin Chang , Yung-Cheng Lu , Syun-Ming Jang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/119
CPC分类号： H01L21/76843 , H01L21/76849 , H01L21/76867 , H01L21/76873 , H01L21/76883 , H01L21/76886 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit structure, the method includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; forming a seed layer in the opening; forming a copper line on the seed layer, wherein at least one of the seed layer and the copper line includes an alloying material; and forming an etch stop layer on the copper line.
摘要翻译：一种形成集成电路结构的方法，所述方法包括提供半导体衬底; 在所述半导体衬底上形成介电层; 在介电层中形成开口; 在开口中形成种子层; 在种子层上形成铜线，其中籽晶层和铜线中的至少一个包括合金材料; 并在铜线上形成蚀刻停止层。

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