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91. 发明申请

US20100285644A1 Methods of Forming Semiconductor Devices Having Recessed Channels 失效
标题翻译：形成具有嵌入通道的半导体器件的方法
公开(公告)号：US20100285644A1
公开(公告)日：2010-11-11
申请号：US12770942
申请日：2010-04-30
申请人： Joo-Young Lee , Dong-Gun Park
发明人： Joo-Young Lee , Dong-Gun Park
IPC分类号： H01L21/336 , H01L21/8242
CPC分类号： H01L27/10823 , H01L27/10814 , H01L27/10852 , H01L27/10876
摘要： A semiconductor device includes a substrate, a gate insulation layer, a gate structure, a gate spacer, and first and second impurity regions. The substrate has an active region defined by an isolation layer. The active region has a gate trench thereon. The gate insulation layer is formed on an inner wall of the gate trench. The gate structure is formed on the gate insulation layer to fill the gate trench. The gate structure has a width smaller than that of the gate trench, and has a recess at a first portion thereof. The gate spacer is formed on sidewalls of the gate structure. The first and second impurity regions are formed at upper portions of the active region adjacent to the gate structure. The first impurity region is closer to the recess than the second impurity region. Related methods are also provided.
摘要翻译：半导体器件包括衬底，栅极绝缘层，栅极结构，栅极间隔物以及第一和第二杂质区域。衬底具有由隔离层限定的有源区。有源区在其上具有栅极沟槽。栅极绝缘层形成在栅极沟槽的内壁上。栅极结构形成在栅极绝缘层上以填充栅极沟槽。栅极结构的宽度小于栅极沟槽的宽度，并且在其第一部分处具有凹部。栅极间隔件形成在栅极结构的侧壁上。第一和第二杂质区域形成在与栅极结构相邻的有源区的上部。第一杂质区比第二杂质区更靠近凹部。还提供了相关方法。

92. 发明授权

US07807517B2 Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions 有权
标题翻译：制造具有对应于一对鳍型沟道区的单个栅电极的半导体器件的方法
公开(公告)号：US07807517B2
公开(公告)日：2010-10-05
申请号：US12219737
申请日：2008-07-28
申请人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
发明人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/785 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/10873 , H01L27/10879 , H01L27/1159 , H01L27/2436 , H01L29/66795
摘要： Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.
摘要翻译：提供了制造具有提供体偏置控制的鳍式FET结构的半导体器件的方法，显示出与SOI结构相关的一些特征优点，提供增加的工作电流和/或降低的接触电阻。制造半导体器件的方法包括在第一绝缘膜的突出部分的侧壁上形成绝缘间隔物; 通过使用绝缘间隔物作为蚀刻掩模去除半导体衬底的暴露区域，从而形成与第一绝缘膜接触并由第一绝缘膜支撑的鳍形成第二沟槽。在形成翅片之后，形成第三绝缘膜以填充第二沟槽并支撑翅片。然后去除第一绝缘膜的一部分以打开翅片之间的空间，其中可以形成包括栅极电介质，栅电极和附加接触，绝缘和存储节点结构的附加结构。

93. 发明授权

US07615429B2 Methods of fabricating field effect transistors having multiple stacked channels 有权
标题翻译：制造具有多个堆叠通道的场效应晶体管的方法
公开(公告)号：US07615429B2
公开(公告)日：2009-11-10
申请号：US11948175
申请日：2007-11-30
申请人： Sung-Min Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Shin-Ae Lee , Seong-Ho Kim
发明人： Sung-Min Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Shin-Ae Lee , Seong-Ho Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/823412 , H01L29/42356 , H01L29/42384 , H01L29/42392 , H01L29/66477 , H01L29/66545 , H01L29/66636 , H01L29/66772 , H01L29/66787 , H01L29/78 , H01L29/78642 , H01L29/78654 , H01L29/78696
摘要： Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.
摘要翻译：集成电路场效应晶体管器件包括在表面上具有表面和有源沟道图案的衬底。活动通道图案包括彼此堆叠并且彼此间隔开以限定相邻通道之间的至少一个通道的通道。栅电极围绕通道并延伸穿过至少一个通道。还提供了一对源极/漏极区域。通过在衬底的表面上形成预活性图案来制造集成电路场效应晶体管。预激活图案包括彼此交替堆叠的一系列通道间层和沟道层。在预活化图案的相对端处，在衬底上形成源极/漏极区域。选择性地去除通道间层以形成隧道。在隧道中形成栅电极并围绕通道。

94. 发明授权

US07566619B2 Methods of forming integrated circuit devices having field effect transistors of different types in different device regions 有权
标题翻译：在不同的器件区域形成具有不同类型的场效应晶体管的集成电路器件的方法
公开(公告)号：US07566619B2
公开(公告)日：2009-07-28
申请号：US11110167
申请日：2005-04-20
申请人： Young-Joon Ahn , Dong-Gun Park , Choong-Ho Lee , Hee-Soo Kang
发明人： Young-Joon Ahn , Dong-Gun Park , Choong-Ho Lee , Hee-Soo Kang
IPC分类号： H01L21/336
CPC分类号： H01L21/823412 , H01L21/823437 , H01L21/823456 , H01L21/823462 , H01L27/1052 , H01L29/66621 , H01L29/66795 , H01L29/7851
摘要： A method of forming an integrated circuit device includes forming a non-planar field-effect transistor in a cell array portion of a semiconductor substrate and forming a planar field-effect transistor in a peripheral circuit portion of the semiconductor substrate. The non-planar field-effect transistor may be selected from the group of a FinFET and a recessed gate FET. Dopants may be implanted into a channel region of the non-planar field-effect transistor, and a cell protection layer may be formed on the non-planar field-effect transistor. Then, dopants may be selectively implanted into a channel region of the planar field-effect transistor using the cell protection layer as a mask to block implanting of the dopants into the channel region of the non-planar field-effect transistor.
摘要翻译：形成集成电路器件的方法包括在半导体衬底的单元阵列部分中形成非平面场效应晶体管，并在半导体衬底的外围电路部分中形成平面场效应晶体管。非平面场效应晶体管可以选自FinFET和凹入栅极FET。可以将掺杂剂注入到非平面场效应晶体管的沟道区域中，并且可以在非平面场效应晶体管上形成电池保护层。然后，可以使用电池保护层作为掩模将掺杂剂选择性地注入到平面场效应晶体管的沟道区域中，以阻止掺杂剂注入到非平面场效应晶体管的沟道区域中。

95. 发明授权

US07560759B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07560759B2
公开(公告)日：2009-07-14
申请号：US11637793
申请日：2006-12-13
申请人： Hee-Soo Kang , Jae-Man Yoon , Dong-Gun Park , Sang-Yeon Han , Young-Joon Ahn , Choong-Ho Lee
发明人： Hee-Soo Kang , Jae-Man Yoon , Dong-Gun Park , Sang-Yeon Han , Young-Joon Ahn , Choong-Ho Lee
IPC分类号： H01L29/06
CPC分类号： H01L29/7851 , H01L29/66818 , Y10S257/90
摘要： A fin type MOSFET and a method of manufacturing the fin type MOSFET are disclosed. Gate structures in the fin type MOSFET are formed by a damascene process without a photolithography process. Impurities used to form a channel region are selectively implanted into portions of a semiconductor substrate adjacent to the gate structures.
摘要翻译：公开了一种翅片式MOSFET及其制造方法。鳍型MOSFET中的栅极结构通过未经光刻工艺的镶嵌工艺形成。用于形成沟道区域的杂质被选择性地注入到与栅极结构相邻的半导体衬底的部分中。

96. 发明授权

US07397131B2 Self-aligned semiconductor contact structures 失效
标题翻译：自对准半导体接触结构
公开(公告)号：US07397131B2
公开(公告)日：2008-07-08
申请号：US11396819
申请日：2006-04-03
申请人： Seong-Ho Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Sung-Min Kim , Shin-Ae Lee
发明人： Seong-Ho Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Sung-Min Kim , Shin-Ae Lee
IPC分类号： H01L29/772
CPC分类号： H01L21/76831 , H01L21/28114 , H01L21/76897 , H01L21/823425 , H01L21/823475 , H01L27/10888 , H01L27/10894 , H01L29/42376 , H01L2924/0002 , H01L2924/00
摘要： A self-aligned contact structure and a method of forming the same include selected neighboring gate electrodes with adjacent sidewalls that are configured to angle toward each other. The angled surfaces of the gate electrodes can be protected using a liner layer that can extend the length of the contact window to define the sidewalls of the contact window.
摘要翻译：自对准接触结构及其形成方法包括具有相邻侧壁的选定的相邻栅电极，其被配置为朝向彼此成角度。可以使用能够延长接触窗口的长度以限定接触窗的侧壁的衬里层来保护栅电极的成角度的表面。

97. 发明申请

US20080090362A1 METHODS OF FABRICATING FIELD EFFECT TRANSISTORS HAVING MULTIPLE STACKED CHANNELS 有权
标题翻译：制作具有多个堆叠通道的场效应晶体管的方法
公开(公告)号：US20080090362A1
公开(公告)日：2008-04-17
申请号：US11948175
申请日：2007-11-30
申请人： Sung-Min Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Shin-Ae Lee , Seong-Ho Kim
发明人： Sung-Min Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Shin-Ae Lee , Seong-Ho Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/823412 , H01L29/42356 , H01L29/42384 , H01L29/42392 , H01L29/66477 , H01L29/66545 , H01L29/66636 , H01L29/66772 , H01L29/66787 , H01L29/78 , H01L29/78642 , H01L29/78654 , H01L29/78696
摘要： Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.
摘要翻译：集成电路场效应晶体管器件包括在表面上具有表面和有源沟道图案的衬底。活动通道图案包括彼此堆叠并且彼此间隔开以限定相邻通道之间的至少一个通道的通道。栅电极围绕通道并延伸穿过至少一个通道。还提供了一对源极/漏极区域。通过在衬底的表面上形成预活性图案来制造集成电路场效应晶体管。预激活图案包括彼此交替堆叠的一系列通道间层和沟道层。在预活化图案的相对端处，在衬底上形成源极/漏极区域。选择性地去除通道间层以形成隧道。在隧道中形成栅电极并围绕通道。

98. 发明授权

US07323375B2 Fin field effect transistor device and method of fabricating the same 失效
标题翻译： Fin场效应晶体管器件及其制造方法
公开(公告)号：US07323375B2
公开(公告)日：2008-01-29
申请号：US11091457
申请日：2005-03-28
申请人： Jae-Man Yoon , Dong-Gun Park , Choong-Ho Lee , Chul Lee
发明人： Jae-Man Yoon , Dong-Gun Park , Choong-Ho Lee , Chul Lee
IPC分类号： H01L21/00
CPC分类号： H01L29/7851 , H01L21/84 , H01L29/66795
摘要： Methods of forming field effect transistors (FETs) having fin-shaped active regions include patterning a semiconductor substrate to define a fin-shaped semiconductor active region therein, which is surrounded by a trench. At least an upper portion of the fin-shaped semiconductor active region is covered with a sacrificial layer. This sacrificial layer is selectively etched-back to define sacrificial spacers on sidewalls of the fin-shaped semiconductor active region. The electrically insulating region is formed on the sacrificial spacers. The sacrificial spacers are then removed by selectively etching the sacrificial spacers using the electrically insulating region as an etching mask. An insulated gate electrode is then formed on the sidewalls of the fin-shaped semiconductor active region.
摘要翻译：形成具有鳍状有源区的场效应晶体管（FET）的方法包括图案化半导体衬底以在其中限定由沟槽包围的鳍状半导体有源区。鳍形半导体有源区域的至少上部被牺牲层覆盖。该牺牲层被有选择地回蚀刻以在鳍状半导体有源区域的侧壁上限定牺牲隔离物。电绝缘区域形成在牺牲间隔物上。然后通过使用电绝缘区域作为蚀刻掩模选择性地蚀刻牺牲隔离物来去除牺牲间隔物。然后在鳍状半导体有源区的侧壁上形成绝缘栅电极。

99. 发明申请

US20070170494A1 Nonvolatile memory device and method for fabricating the same 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20070170494A1
公开(公告)日：2007-07-26
申请号：US11584965
申请日：2006-10-23
申请人： Dong-Gun Park , Sung-Min Kim
发明人： Dong-Gun Park , Sung-Min Kim
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7885 , H01L27/115 , H01L27/11521 , H01L29/512 , H01L29/513 , H01L29/7887
摘要： In a nonvolatile memory device, and a method for fabricating the nonvolatile memory device, two floating gates are formed so as to be isolated from each other in a single memory cell field. The method is comprised of forming a first conductive layer pattern to have pattern portions that are separated from each other, removing a central part of the first conductive layer pattern portions, and forming first and second floating gates that are separated from each other, A second conductive layer is formed on the first and second floating gates, and a dielectric layer is interposed between the first and second floating gates and the second conductive layer. The operational reliability of the nonvolatile memory device is thereby improved.
摘要翻译：在非易失性存储器件和非易失性存储器件的制造方法中，形成两个浮置栅极，以在单个存储器单元区域彼此隔离。该方法包括形成第一导电层图案以具有彼此分离的图案部分，去除第一导电层图案部分的中心部分，以及形成彼此分离的第一和第二浮动栅极; A秒导电层形成在第一和第二浮栅上，并且电介质层介于第一和第二浮置栅极与第二导电层之间。从而提高了非易失性存储装置的操作可靠性。

100. 发明授权

US07177192B2 Method of operating a flash memory device 失效
标题翻译：操作闪存设备的方法
公开(公告)号：US07177192B2
公开(公告)日：2007-02-13
申请号：US11274310
申请日：2005-11-16
申请人： Jae-Man Yoon , Eun-Suk Cho , Dong-Gun Park , Choong-Ho Lee
发明人： Jae-Man Yoon , Eun-Suk Cho , Dong-Gun Park , Choong-Ho Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： A method of operating a NAND flash memory device that comprising a unit string comprising a string selection transistor connected to a bit line, a cell transistor connected to the string selection transistor, and a ground selection transistor connected to the cell transistor is provided. The method comprises applying a negative bias voltage to the string selection transistor and the ground selection transistor in a stand-by mode of the NAND flash memory device.
摘要翻译：提供一种操作NAND闪速存储器件的方法，该NAND闪速存储器件包括连接到位线的串选择晶体管，连接到串选择晶体管的单元晶体管和连接到单元晶体管的接地选择晶体管的单元串。该方法包括在NAND闪速存储器件的待机模式中向串选择晶体管和接地选择晶体管施加负偏置电压。

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