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91. 发明授权

US08623714B2 Spacer protection and electrical connection for array device 失效
标题翻译：阵列器件的间隔保护和电气连接
公开(公告)号：US08623714B2
公开(公告)日：2014-01-07
申请号：US12728488
申请日：2010-03-22
申请人： Jae-Eun Park , Weipeng Li , Deleep R. Nair , M. Dean Sciacca , Voon-Yew Thean , Ava Wan , Dong-Hun Lee , Yong-Meng Lee
发明人： Jae-Eun Park , Weipeng Li , Deleep R. Nair , M. Dean Sciacca , Voon-Yew Thean , Ava Wan , Dong-Hun Lee , Yong-Meng Lee
IPC分类号： H01L21/00
CPC分类号： H01L29/7833 , H01L21/28518 , H01L21/76895 , H01L29/665 , H01L29/6659
摘要： The present disclosure provides a method of forming an electrical device. The method may begin with forming a gate structure on a substrate, in which a spacer is present in direct contact with a sidewall of the gate structure. A source region and a drain region is formed in the substrate. A metal semiconductor alloy is formed on the gate structure, an outer sidewall of the spacer and one of the source region and the drain region. An interlevel dielectric layer is formed over the metal semiconductor alloy. A via is formed through the interlevel dielectric stopping on the metal semiconductor alloy. An interconnect is formed to the metal semiconductor alloy in the via. The present disclosure also includes the structure produced by the method described above.
摘要翻译：本公开提供了形成电气装置的方法。该方法可以从衬底上形成栅极结构开始，其中间隔物直接与栅极结构的侧壁接触。源极区和漏极区形成在衬底中。在栅极结构上形成金属半导体合金，间隔物的外侧壁和源极区域和漏极区域中的一个。在金属半导体合金上形成层间电介质层。通过金属半导体合金上的层间电介质停止形成通孔。在通孔中的金属半导体合金形成互连。本公开还包括通过上述方法制造的结构。

92. 发明授权

US08587039B2 Method of forming a semiconductor device featuring a gate stressor and semiconductor device 有权
标题翻译：形成具有栅极应力和半导体器件的半导体器件的方法
公开(公告)号：US08587039B2
公开(公告)日：2013-11-19
申请号：US13112077
申请日：2011-05-20
申请人： Brian A. Winstead , Konstantin V. Loiko , Voon-Yew Thean
发明人： Brian A. Winstead , Konstantin V. Loiko , Voon-Yew Thean
IPC分类号： H01L29/76
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823828 , H01L29/7833 , H01L29/7845
摘要： A semiconductor device is formed in a semiconductor layer. A gate stack is formed over the semiconductor layer and comprises a first conductive layer and a second layer over the first layer. The first layer is more conductive and provides more stopping power to an implant than the second layer. A species is implanted into the second layer. Source/drain regions are formed in the semiconductor layer on opposing sides of the gate stack. The gate stack is heated after the step of implanting to cause the gate stack to exert stress in the semiconductor layer in a region under the gate stack.
摘要翻译：在半导体层中形成半导体器件。栅叠层形成在半导体层之上，并且包括第一导电层和第一层上的第二层。第一层比第二层更具导电性并且为植入物提供更多的停止力。一种种植于第二层。源极/漏极区域形成在栅极堆叠的相对侧上的半导体层中。栅极堆叠在注入步骤之后被加热，以使栅极堆叠在栅叠层下方的区域中的半导体层中施加应力。

93. 发明申请

US20120256268A1 INTEGRATED CIRCUIT STRUCTURE HAVING SUBSTANTIALLY PLANAR N-P STEP HEIGHT AND METHODS OF FORMING 失效
标题翻译：具有大面积平面N-P步高的集成电路结构及其形成方法
公开(公告)号：US20120256268A1
公开(公告)日：2012-10-11
申请号：US13083631
申请日：2011-04-11
申请人： Weipeng Li , Deleep R. Nair , Jae-Eun Park , Voon-Yew Thean , Young Way Teh
发明人： Weipeng Li , Deleep R. Nair , Jae-Eun Park , Voon-Yew Thean , Young Way Teh
IPC分类号： H01L27/092 , H01L21/304 , H01L21/20
CPC分类号： H01L21/823878 , H01L21/76232 , H01L21/823807
摘要： Solutions for forming an integrated circuit structure having a substantially planar N-P step height are disclosed. In one embodiment, a method includes: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region; forming a mask over the PFET region to leave the NFET region exposed; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region; and forming a silicon germanium (SiGE) channel in the PFET region after the performing of the DHF.
摘要翻译：公开了用于形成具有基本平坦的N-P台阶高度的集成电路结构的解决方案。在一个实施例中，一种方法包括：提供具有n型场效应晶体管（NFET）区和p型场效应晶体管（PFET）区的结构; 在PFET区域上形成掩模以使NFET区域露出; 在暴露的NFET区域上进行稀释的氟化氢（DHF）清洁以显着降低NFET区域的STI分布; 以及在执行DHF之后在PFET区域中形成硅锗（SiGE）通道。

94. 发明申请

US20110220975A1 METHOD OF FORMING A SEMICONDUCTOR DEVICE FEATURING A GATE STRESSOR AND SEMICONDUCTOR DEVICE 有权
标题翻译：形成栅极压电器和半导体器件的半导体器件特征的方法
公开(公告)号：US20110220975A1
公开(公告)日：2011-09-15
申请号：US13112077
申请日：2011-05-20
申请人： Brian A. Winstead , Konstantin V. Loiko , Voon-Yew Thean
发明人： Brian A. Winstead , Konstantin V. Loiko , Voon-Yew Thean
IPC分类号： H01L29/772
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823828 , H01L29/7833 , H01L29/7845
摘要： A semiconductor device is formed in a semiconductor layer. A gate stack is formed over the semiconductor layer and comprises a first conductive layer and a second layer over the first layer. The first layer is more conductive and provides more stopping power to an implant than the second layer. A species is implanted into the second layer. Source/drain regions are formed in the semiconductor layer on opposing sides of the gate stack. The gate stack is heated after the step of implanting to cause the gate stack to exert stress in the semiconductor layer in a region under the gate stack.
摘要翻译：在半导体层中形成半导体器件。栅叠层形成在半导体层之上，并且包括第一导电层和第一层上的第二层。第一层比第二层更具导电性并且为植入物提供更多的停止力。一种种植于第二层。源极/漏极区域形成在栅极堆叠的相对侧上的半导体层中。栅极堆叠在注入步骤之后被加热，以使栅极堆叠在栅叠层下方的区域中的半导体层中施加应力。

95. 发明授权

US07736957B2 Method of making a semiconductor device with embedded stressor 失效
标题翻译：制造具有嵌入式应力源的半导体器件的方法
公开(公告)号：US07736957B2
公开(公告)日：2010-06-15
申请号：US11756095
申请日：2007-05-31
申请人： Paul A. Grudowski , Veeraraghavan Dhandapani , Darren V. Goedeke , Voon-Yew Thean , Stefan Zollner
发明人： Paul A. Grudowski , Veeraraghavan Dhandapani , Darren V. Goedeke , Voon-Yew Thean , Stefan Zollner
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A method for forming a semiconductor device includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode over the gate dielectric; forming an insulating layer over a sidewall of the gate electrode; defining source and drain regions in the semiconductor substrate adjacent to the insulating layer; implanting a dopant in the source and drain regions of the semiconductor substrate to form doped source and drain regions; forming a sidewall spacer adjacent to the insulating layer; forming a recess in the semiconductor substrate in the source and drain regions, wherein the recess extends directly underneath the spacer a predetermined distance from a channel regions; and forming a stressor material in the recess. The method allows the stressor material to be formed closer to a channel region, thus improving carrier mobility in the channel while not degrading short channel effects.
摘要翻译：一种形成半导体器件的方法包括提供半导体衬底; 在所述半导体衬底上形成栅极电介质; 在所述栅极电介质上形成栅电极; 在所述栅电极的侧壁上形成绝缘层; 限定与绝缘层相邻的半导体衬底中的源区和漏区; 在所述半导体衬底的源区和漏区中注入掺杂剂以形成掺杂源极和漏极区; 形成邻近所述绝缘层的侧壁间隔物; 在所述源极和漏极区域中的所述半导体衬底中形成凹部，其中所述凹部直接在所述间隔物的下方延伸距离沟道区域预定的距离; 以及在所述凹部中形成应力源材料。该方法允许应力源材料形成得更靠近沟道区，从而改善通道中的载流子迁移率，同时不会降低短沟道效应。

96. 发明申请

US20100013021A1 METHOD TO REDUCE THRESHOLD VOLTAGE (Vt) IN SILICON GERMANIUM (SIGE), HIGH-K DIELECTRIC-METAL GATE, P-TYPE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS 有权
标题翻译：降低硅锗（SIGE），高K介电金属栅，P型金属氧化物半导体场效应晶体管的阈值电压（Vt）的方法
公开(公告)号：US20100013021A1
公开(公告)日：2010-01-21
申请号：US12176634
申请日：2008-07-21
申请人： Xiangdong Chen , Jong Ho Lee , Weipeng Li , Dae-Gyu Park , Kenneth J. Stein , Voon-Yew Thean
发明人： Xiangdong Chen , Jong Ho Lee , Weipeng Li , Dae-Gyu Park , Kenneth J. Stein , Voon-Yew Thean
IPC分类号： H01L29/78 , H01L27/092 , H01L21/336 , H01L21/8238
CPC分类号： H01L21/823857 , H01L21/2652 , H01L21/823807 , H01L29/1054
摘要： Disclosed are embodiments of a p-type, silicon germanium (SiGe), high-k dielectric-metal gate, metal oxide semiconductor field effect transistor (PFET) having an optimal threshold voltage (Vt), a complementary metal oxide semiconductor (CMOS) device that includes the PFET and methods of forming both the PFET alone and the CMOS device. The embodiments incorporate negatively charged ions (e.g., fluorine (F), chlorine (Cl), bromine (Br), iodine (I), etc.) into the high-k gate dielectric material of the PFET only so as to selectively adjust the negative Vt of the PFET (i.e., so as to reduce the negative Vt of the PFET).
摘要翻译：公开了具有最佳阈值电压（Vt）的p型硅锗（SiGe），高k电介质金属栅极，金属氧化物半导体场效应晶体管（PFET），互补金属氧化物半导体（CMOS）器件其包括PFET和形成PFET单独和CMOS器件的方法。实施例将带负电荷的离子（例如，氟（F），氯（Cl），溴（Br），碘（I）等）并入PFET的高k栅介质材料中，以便选择性地调节 PFET的负Vt（即，以减小PFET的负Vt）。

97. 发明申请

US20080299717A1 METHOD OF FORMING A SEMICONDUCTOR DEVICE FEATURING A GATE STRESSOR AND SEMICONDUCTOR DEVICE 有权
标题翻译：形成栅极压电器和半导体器件的半导体器件特征的方法
公开(公告)号：US20080299717A1
公开(公告)日：2008-12-04
申请号：US11756231
申请日：2007-05-31
申请人： Brian A. Winstead , Konstantin V. Loiko , Voon-Yew Thean
发明人： Brian A. Winstead , Konstantin V. Loiko , Voon-Yew Thean
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823828 , H01L29/7833 , H01L29/7845
摘要： A semiconductor device (10) is formed in a semiconductor layer (12). A gate stack (16,18) is formed over the semiconductor layer and comprises a first conductive layer (22) and a second layer (24) over the first layer. The first layer is more conductive and provides more stopping power to an implant than the second layer. A species (46) is implanted into the second layer. Source/drain regions (52) are formed in the semiconductor layer on opposing sides of the gate stack. The gate stack is heated after the step of implanting to cause the gate stack to exert stress in the semiconductor layer in a region under the gate stack.
摘要翻译：半导体器件（10）形成在半导体层（12）中。在半导体层之上形成栅堆叠（16,18），并且包括第一层上的第一导电层（22）和第二层（24）。第一层比第二层更具导电性并且为植入物提供更多的停止力。物种（46）被植入第二层。源极/漏极区域（52）形成在栅极堆叠的相对侧上的半导体层中。栅极堆叠在注入步骤之后被加热，以使栅极堆叠在栅叠层下方的区域中的半导体层中施加应力。

98. 发明申请

US20080188067A1 PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING FORMING A GATE ELECTRODE LAYER AND FORMING A PATTERNED MASKING LAYER 有权
标题翻译：形成电子装置的方法，包括形成门电极层和形成图案掩蔽层
公开(公告)号：US20080188067A1
公开(公告)日：2008-08-07
申请号：US11671748
申请日：2007-02-06
申请人： Leo Mathew , Voon-Yew Thean , Vishal P. Trivedi
发明人： Leo Mathew , Voon-Yew Thean , Vishal P. Trivedi
IPC分类号： H01L21/3205
CPC分类号： H01L21/28123 , H01L21/2652 , H01L21/32139 , H01L29/4966
摘要： A process of forming an electronic device can include forming a gate electrode layer and forming a patterned masking layer. In a first aspect, a process operation is performed before removing substantially all of a lower portion of the gate electrode layer. In a second aspect, a gate dielectric layer is formed prior to forming the gate electrode layer, and a portion of the gate dielectric layer is exposed after removing the patterned masking layer and prior to forming another masking layer. A portion of the gate electrode layer remains covered during a process where some or all of the portion would be otherwise removed or consumed. By forming the electronic device using such a process, damage to the gate electrode structure while performing subsequent processing can be significantly reduced.
摘要翻译：形成电子器件的工艺可以包括形成栅极电极层并形成图案化掩模层。在第一方面，在去除栅极电极层的基本上所有下部之前进行处理操作。在第二方面，在形成栅极电极层之前形成栅极电介质层，并且在去除图案化掩模层之后并且在形成另一个掩模层之前，一部分栅极电介质层被曝光。在其中将部分或全部部分将被去除或消耗的过程中，栅电极层的一部分保持覆盖。通过使用这种处理形成电子器件，可以显着地减少执行后续处理时对栅电极结构的损坏。

99. 发明授权

US07235502B2 Transitional dielectric layer to improve reliability and performance of high dielectric constant transistors 有权
标题翻译：过渡介电层提高高介电常数晶体管的可靠性和性能
公开(公告)号：US07235502B2
公开(公告)日：2007-06-26
申请号：US11096515
申请日：2005-03-31
申请人： Sriram S. Kalpat , Voon-Yew Thean , Hsing H. Tseng , Olubunmi O. Adetutu
发明人： Sriram S. Kalpat , Voon-Yew Thean , Hsing H. Tseng , Olubunmi O. Adetutu
IPC分类号： H01L21/31
CPC分类号： H01L21/022 , H01L21/02175 , H01L21/0228 , H01L21/28194 , H01L21/3141 , H01L29/513 , H01L29/517
摘要： A gate dielectric structure (201) fabrication process includes forming a transitional dielectric film (205) overlying a silicon oxide film (204). A high dielectric constant film (206) is then formed overlying an upper surface of the transitional dielectric film (205). The composition of the transitional dielectric film (205) at the silicon oxide film (204) interface primarily comprises silicon and oxygen. The high K dielectric (206) and the composition of the transitional dielectric film (205) near the upper surface primarily comprise a metal element and oxygen. Forming the transitional dielectric film (205) may include forming a plurality of transitional dielectric layers (207) where the composition of each successive transitional dielectric layer (207) has a higher concentration of the metal element and a lower concentration of silicon. Forming the transitional dielectric layer (205) may include performing multiple cycles of an atomic layer deposition process (500) where a precursor concentration for each cycle differs from the precursor concentration of the preceding cycle.
摘要翻译：栅极电介质结构（201）制造工艺包括形成覆盖氧化硅膜（204）的过渡电介质膜（205）。然后形成覆盖在过渡介电膜（205）的上表面上的高介电常数膜（206）。氧化硅膜（204）界面处的过渡电介质膜（205）的组成主要包括硅和氧。高K电介质（206）和上表面附近的过渡电介质膜（205）的组成主要包括金属元素和氧。形成过渡电介质膜（205）可以包括形成多个过渡介电层（207），其中每个连续的过渡介电层（207）的组成具有较高的金属元素浓度和较低的硅浓度。形成过渡电介质层（205）可以包括执行原子层沉积工艺（500）的多个循环，其中每个循环的前体浓度与先前循环的前体浓度不同。

100. 发明授权

US08563394B2 Integrated circuit structure having substantially planar N-P step height and methods of forming 失效
标题翻译：具有基本上平面的N-P台阶高度的集成电路结构和形成方法
公开(公告)号：US08563394B2
公开(公告)日：2013-10-22
申请号：US13083631
申请日：2011-04-11
申请人： Weipeng Li , Deleep R. Nair , Jae-Eun Park , Voon-Yew Thean , Young Way Teh
发明人： Weipeng Li , Deleep R. Nair , Jae-Eun Park , Voon-Yew Thean , Young Way Teh
IPC分类号： H01L21/76
CPC分类号： H01L21/823878 , H01L21/76232 , H01L21/823807
摘要： Solutions for forming an integrated circuit structure having a substantially planar N-P step height are disclosed. In one embodiment, a method includes: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region; forming a mask over the PFET region to leave the NFET region exposed; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region; and forming a silicon germanium (SiGE) channel in the PFET region after the performing of the DHF.
摘要翻译：公开了用于形成具有基本平坦的N-P台阶高度的集成电路结构的解决方案。在一个实施例中，一种方法包括：提供具有n型场效应晶体管（NFET）区域和p型场效应晶体管（PFET）区域的结构; 在PFET区域上形成掩模以使NFET区域露出; 在暴露的NFET区域上进行稀释的氟化氢（DHF）清洁以显着降低NFET区域的STI分布; 以及在执行DHF之后在PFET区域中形成硅锗（SiGE）通道。

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