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91. 发明申请

US20120309269A1 LOW-TEMPERATURE METHODS FOR SPONTANEOUS MATERIAL SPALLING 审中-公开
标题翻译：用于自发材料膨胀的低温方法
公开(公告)号：US20120309269A1
公开(公告)日：2012-12-06
申请号：US13150813
申请日：2011-06-01
申请人： Maha M. Khayyat , Norma E. Sosa Cortes , Katherine L. Saenger , Stephen W. Bedell , Devendra K. Sadana
发明人： Maha M. Khayyat , Norma E. Sosa Cortes , Katherine L. Saenger , Stephen W. Bedell , Devendra K. Sadana
IPC分类号： B24B1/00
CPC分类号： H01L21/187
摘要： Method to (i) introduce additional control into a material spalling process, thus improving both the crack initiation and propagation, and (ii) increase the range of selectable spalling depths are provided. In one embodiment, the method includes providing a stressor layer on a surface of a base substrate at a first temperature which is room temperature. Next, the base substrate including the stressor layer is brought to a second temperature which is less than room temperature. The base substrate is spalled at the second temperature to form a spalled material layer. Thereafter, the spalled material layer is returned to room temperature, i.e., the first temperature.
摘要翻译：方法：（i）对材料剥落过程引入额外的控制，从而改善裂纹的产生和传播，并提供（ii）提高选择性剥落深度的范围。在一个实施例中，该方法包括在室温下的第一温度下在基底基板的表面上提供应力层。接下来，包括应力层的基底衬底达到小于室温的第二温度。基底基板在第二温度下剥离以形成剥离的材料层。此后，剥离的材料层返回到室温，即第一温度。

92. 发明申请

US20120286235A1 NANOSCALE CHEMICAL TEMPLATING WITH OXYGEN REACTIVE MATERIALS 有权
标题翻译：用氧化物反应材料进行纳米化学化学分析
公开(公告)号：US20120286235A1
公开(公告)日：2012-11-15
申请号：US13555242
申请日：2012-07-23
申请人： Maha M. Khayyat , Devendra K. Sadana , Brent A. Wacaser
发明人： Maha M. Khayyat , Devendra K. Sadana , Brent A. Wacaser
IPC分类号： H01L21/20 , H01L29/66 , H01L21/306 , B82Y40/00
CPC分类号： H01L29/0676 , H01L21/20 , H01L21/30 , H01L29/02 , H01L29/20 , H01L29/66
摘要： A method of fabricating templated semiconductor nanowires on a surface of a semiconductor substrate for use in semiconductor device applications is provided. The method includes controlling the spatial placement of the semiconductor nanowires by using an oxygen reactive seed material. The present invention also provides semiconductor structures including semiconductor nanowires. In yet another embodiment, patterning of a compound semiconductor substrate or other like substrate which is capable of forming a compound semiconductor alloy with an oxygen reactive element during a subsequent annealing step is provided. This embodiment provides a patterned substrate that can be used in various applications including, for example, in semiconductor device manufacturing, optoelectronic device manufacturing and solar cell device manufacturing.
摘要翻译：提供了一种在用于半导体器件应用的半导体衬底的表面上制造模板化半导体纳米线的方法。该方法包括通过使用氧反应种子材料来控制半导体纳米线的空间位置。本发明还提供包括半导体纳米线的半导体结构。在又一个实施例中，提供了在随后的退火步骤期间能够与氧反应元件形成化合物半导体合金的化合物半导体衬底或其它类似衬底的图案化。该实施例提供可用于各种应用的图案化衬底，包括例如半导体器件制造，光电器件制造和太阳能电池器件制造。

93. 发明申请

US20120273925A1 PATTERNED DOPING OF SEMICONDUCTOR SUBSTRATES USING PHOTOSENSITIVE MONOLAYERS 失效
标题翻译：使用光敏单体的半导体基板的图案化
公开(公告)号：US20120273925A1
公开(公告)日：2012-11-01
申请号：US13541857
申请日：2012-07-05
申请人： Ali Afzali-Ardakani , Devendra K. Sadana , Lidija Sekaric
发明人： Ali Afzali-Ardakani , Devendra K. Sadana , Lidija Sekaric
IPC分类号： H01L29/06
CPC分类号： H01L21/228 , H01L21/22 , H01L29/06
摘要： A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.
摘要翻译：公开了半导体器件和制造半导体器件的方法。本发明的实施方案使用光敏自组装单层将基材的表面图案化成亲水和疏水区域，并且掺杂剂化合物的水溶液（或醇）沉积在基材表面上。掺杂剂仅粘附在亲水区上。在沉积之后，用非常薄的氧化层涂覆衬底以封盖化合物，并且衬底在高温下退火以将掺杂剂原子扩散到硅中并激活掺杂剂。在一个实施例中，该方法包括提供包括氧化物表面的半导体衬底，将所述表面图案化成疏水和亲水区域，在衬底上沉积包括掺杂剂的化合物，其中掺杂剂粘附到亲水区域，并将掺杂剂扩散到氧化物表面。

94. 发明申请

US20120190177A1 N-type carrier enhancement in semiconductors 失效
标题翻译：半导体中的N型载流子增强
公开(公告)号：US20120190177A1
公开(公告)日：2012-07-26
申请号：US13436850
申请日：2012-03-31
申请人： Jee Hwan Kim , Stephen W. Bedell , Siegfried Maurer , Devendra K. Sadana
发明人： Jee Hwan Kim , Stephen W. Bedell , Siegfried Maurer , Devendra K. Sadana
IPC分类号： H01L21/265 , H01L21/20
CPC分类号： H01L21/26513 , H01L29/165 , H01L29/167 , H01L29/66636 , Y10S438/919
摘要： A method includes epitaxially growing a germanium (Ge) layer onto a Ge substrate and incorporating a compensating species with a compensating atomic radius into the Ge layer. The method includes implanting an n-type dopant species with a dopant atomic radius into the Ge layer. The method includes selecting the n-type dopant species and the compensating species in such manner that the size of the Ge atomic radius is inbetween the n-type dopant atomic radius and the compensating atomic radius.
摘要翻译：一种方法包括将锗（Ge）层外延生长到Ge衬底上并将具有补偿原子半径的补偿物质结合到Ge层中。该方法包括将具有掺杂剂原子半径的n型掺杂物种类植入到Ge层中。该方法包括选择n型掺杂剂物质和补偿物质，使得Ge原子半径的大小在n型掺杂剂原子半径和补偿原子半径之间。

95. 发明申请

US20120135587A1 N-type carrier enhancement in semiconductors 有权
标题翻译：半导体中的N型载流子增强
公开(公告)号：US20120135587A1
公开(公告)日：2012-05-31
申请号：US13357656
申请日：2012-01-25
申请人： Jee Hwan Kim , Stephen W. Bedell , Siegfried Maurer , Devendra K. Sadana
发明人： Jee Hwan Kim , Stephen W. Bedell , Siegfried Maurer , Devendra K. Sadana
IPC分类号： H01L21/265
CPC分类号： H01L21/26513 , H01L29/165 , H01L29/167 , H01L29/66636 , Y10S438/919
摘要： A method for generating n-type carriers in a semiconductor is disclosed. The method includes supplying a semiconductor having an atomic radius. Implanting an n-type dopant species into the semiconductor, which n-type dopant species has a dopant atomic radius. Implanting a compensating species into the semiconductor, which compensating species has a compensating atomic radius. Selecting the n-type dopant species and the compensating species in such manner that the size of the semiconductor atomic radius is inbetween the dopant atomic radius and the compensating atomic radius. A further method is disclosed for generating n-type carriers in germanium (Ge). The method includes setting a target concentration for the carriers, implanting a dose of an n-type dopant species into the Ge, and selecting the dose to correspond to a fraction of the target carrier concentration. Thermal annealing the Ge in such manner as to activate the n-type dopant species and to repair a least a portion of the implantation damage. Repeating the implantation and the thermal annealing until the target n-type carrier concentration has been reached.
摘要翻译：公开了一种在半导体中产生n型载流子的方法。该方法包括提供具有原子半径的半导体。将n型掺杂物种植入半导体，其中n型掺杂剂物质具有掺杂剂原子半径。将补偿物种植入到半导体中，补偿物质具有补偿原子半径。以使得半导体原子半径的尺寸在掺杂剂原子半径和补偿原子半径之间的方式选择n型掺杂物种类和补偿种类。公开了用于在锗（Ge）中生成n型载流子的另一种方法。该方法包括设定载体的目标浓度，将一定剂量的n型掺杂剂物质注入到Ge中，并选择与目标载体浓度分数相对应的剂量。对Ge进行热退火，以激活n型掺杂物种类并修复至少一部分注入损伤。重复注入和热退火直到目标n型载流子浓度达到。

96. 发明申请

US20120118383A1 Autonomous Integrated Circuit 审中-公开
标题翻译：自主集成电路
公开(公告)号：US20120118383A1
公开(公告)日：2012-05-17
申请号：US12946216
申请日：2010-11-15
申请人： Stephen W. Bedell , Norma E. Sosa Cortes , Wilfried E. Haensch , Steven J. Koester , Devendra K. Sadana , Katherine L. Saenger , Ghavam Shahidi , Davood Shahrjerdi
发明人： Stephen W. Bedell , Norma E. Sosa Cortes , Wilfried E. Haensch , Steven J. Koester , Devendra K. Sadana , Katherine L. Saenger , Ghavam Shahidi , Davood Shahrjerdi
IPC分类号： H01L31/0264 , H01L31/18
CPC分类号： H01L27/142 , H01L31/02008 , H01L31/0747 , H01L31/075 , H01L31/076 , H01L31/078 , H01L31/1804 , H01L31/202 , Y02E10/547 , Y02E10/548 , Y02P70/521
摘要： An autonomous integrated circuit (IC) includes a solar cell formed on a bottom substrate of a silicon-on-insulator (SOI) substrate as a handle substrate; an insulating layer of the SOI substrate located on top of the solar cell; and a device layer formed on a top semiconductor layer of the SOI substrate located on top of the insulating layer, wherein a top contact of the device layer is electrically connected to a bottom contact of the solar cell such that the solar cell is enabled to power the device layer.
摘要翻译：自主集成电路（IC）包括形成在作为处理衬底的绝缘体上硅（SOI）衬底的底部衬底上的太阳能电池; 位于太阳能电池顶部的SOI衬底的绝缘层; 以及形成在位于绝缘层顶部的SOI衬底的顶部半导体层上的器件层，其中器件层的顶部接触电连接到太阳能电池的底部接触，使得太阳能电池能够通电设备层。

97. 发明申请

US20120003819A1 Methods and apparatus for selective epitaxy of si-containing materials and substitutionally doped crystalline si-containing material 有权
标题翻译：用于选择性外延Si含量材料和替代掺杂晶体含Si材料的方法和设备
公开(公告)号：US20120003819A1
公开(公告)日：2012-01-05
申请号：US13135031
申请日：2011-06-23
申请人： Terry Arthur Francis , Satoshi Hasaka , Paul David Brabant , Robert Torres, JR. , He Hong , Alexander Reznicek , Thomas N. Adam , Devendra K. Sadana
发明人： Terry Arthur Francis , Satoshi Hasaka , Paul David Brabant , Robert Torres, JR. , He Hong , Alexander Reznicek , Thomas N. Adam , Devendra K. Sadana
IPC分类号： H01L21/205
CPC分类号： H01L21/02532 , C23C16/30 , C23C16/325 , C30B25/02 , C30B29/06 , H01L21/0237 , H01L21/02529 , H01L21/02573 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/02636
摘要： The present invention discloses that under modified chemical vapor deposition (mCVD) conditions an epitaxial silicon film may be formed by exposing a substrate contained within a chamber to a relatively high carrier gas flow rate in combination with a relatively low silicon precursor flow rate at a temperature of less than about 550° C. and a pressure in the range of about 10 mTorr-200 Torr. Furthermore, the crystalline Si may be in situ doped to contain relatively high levels of substitutional carbon by carrying out the deposition at a relatively high flow rate using tetrasilane as a silicon source and a carbon-containing gas such as dodecalmethylcyclohexasilane or tetramethyldisilane under modified CVD conditions.
摘要翻译：本发明公开了在改进的化学气相沉积（mCVD）条件下，外延硅膜可以通过将包含在腔室内的衬底暴露于相对高的载气流量与在较低的硅前体流速小于约550℃，压力范围为约10mTorr-200Torr。此外，通过在改进的CVD条件下使用四硅烷作为硅源和含碳气体如十二烷基甲基环己硅烷或四甲基二硅烷以相对高的流速进行沉积，可以将晶体Si原位掺杂以含有相对高水平的取代碳。

98. 发明申请

US20110263104A1 THIN BODY SEMICONDUCTOR DEVICES 有权
标题翻译：薄体半导体器件
公开(公告)号：US20110263104A1
公开(公告)日：2011-10-27
申请号：US12766859
申请日：2010-04-24
申请人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Thomas N. Adam , Kangguo Cheng , Ali Khakifirooz , Alexander Reznicek , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L21/20
CPC分类号： H01L29/66628 , H01L29/66742 , H01L29/66772 , H01L29/66795 , H01L29/78696
摘要： A method for fabricating an FET device is disclosed. The method includes providing a body over an insulator, with the body having at least one surface adapted to host a device channel. Selecting the body to be Si, Ge, or their alloy mixtures. Choosing the body layer to be less than a critical thickness defined as the thickness where agglomeration may set in during a high temperature processing. Such critical thickness may be about 4 nm for a planar devices, and about 8 nm for a non-planar devices. The method further includes clearing surfaces of oxygen at low temperature, and forming a raised source/drain by selective epitaxy while using the cleared surfaces for seeding. After the clearing of the surfaces of oxygen, and before the selective epitaxy, oxygen exposure of the cleared surfaces is being prevented.
摘要翻译：公开了一种用于制造FET器件的方法。该方法包括在绝缘体上提供主体，其中主体具有适于承载设备通道的至少一个表面。选择身体为Si，Ge或其合金混合物。选择体层小于临界厚度，其临界厚度定义为在高温加工过程中聚集的厚度。这种临界厚度对于平面器件可以是约4nm，对于非平面器件而言约8nm。该方法还包括在低温下清除氧的表面，并且通过选择性外延形成凸起的源极/漏极，同时使用清除的表面进行接种。在氧的表面清除之后，并且在选择性外延之前，防止了清除的表面的氧曝光。

99. 发明申请

US20110186804A1 NANOSCALE CHEMICAL TEMPLATING WITH OXYGEN REACTIVE MATERIALS 有权
标题翻译：用氧化物反应材料进行纳米化学化学分析
公开(公告)号：US20110186804A1
公开(公告)日：2011-08-04
申请号：US12696417
申请日：2010-01-29
申请人： Maha M. Khayyat , Devendra K. Sadana , Brent A. Wacaser
发明人： Maha M. Khayyat , Devendra K. Sadana , Brent A. Wacaser
IPC分类号： H01L29/66 , H01L21/20 , H01L21/30 , H01L29/02
CPC分类号： H01L29/0676 , H01L21/20 , H01L21/30 , H01L29/02 , H01L29/20 , H01L29/66
摘要： A method of fabricating templated semiconductor nanowires on a surface of a semiconductor substrate for use in semiconductor device applications is provided. The method includes controlling the spatial placement of the semiconductor nanowires by using an oxygen reactive seed material. The present invention also provides semiconductor structures including semiconductor nanowires. In yet another embodiment, patterning of a compound semiconductor substrate or other like substrate which is capable of forming a compound semiconductor alloy with an oxygen reactive element during a subsequent annealing step is provided. This embodiment provides a patterned substrate that can be used in various applications including, for example, in semiconductor device manufacturing, optoelectronic device manufacturing and solar cell device manufacturing.
摘要翻译：提供了一种在用于半导体器件应用的半导体衬底的表面上制造模板化半导体纳米线的方法。该方法包括通过使用氧反应种子材料来控制半导体纳米线的空间位置。本发明还提供包括半导体纳米线的半导体结构。在又一个实施例中，提供了在随后的退火步骤期间能够与氧反应元件形成化合物半导体合金的化合物半导体衬底或其它类似衬底的图案化。该实施例提供可用于各种应用的图案化衬底，包括例如半导体器件制造，光电器件制造和太阳能电池器件制造。

100. 发明申请

US20110175166A1 STRAINED CMOS DEVICE, CIRCUIT AND METHOD OF FABRICATION 有权
标题翻译：应变CMOS器件，电路和制造方法
公开(公告)号：US20110175166A1
公开(公告)日：2011-07-21
申请号：US12689339
申请日：2010-01-19
申请人： Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Devendra K. Sadana , Ghavam G. Shahidi
发明人： Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Devendra K. Sadana , Ghavam G. Shahidi
IPC分类号： H01L27/12 , H01L21/782
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/7849
摘要： A semiconductor device and fabrication method include a strained semiconductor layer having a strain in one axis. A long fin and a short fin are formed in the semiconductor layer such that the long fin has a strained length along the one axis. An n-type transistor is formed on the long fin, and a p-type transistor is formed on the at least one short fin. The strain in the n-type transistor improves performance.
摘要翻译：半导体器件和制造方法包括在一个轴上具有应变的应变半导体层。在半导体层中形成长鳍片和短鳍片，使得长鳍片沿着一个轴线具有应变长度。在长鳍片上形成n型晶体管，在该至少一个短鳍片上形成p型晶体管。 n型晶体管中的应变提高了性能。

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