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91. 发明授权

US06323722B1 Apparatus for translating a voltage 有权
公开(公告)号：US06323722B1
公开(公告)日：2001-11-27
申请号：US09516399
申请日：2000-03-01
申请人： Robert J. Proebsting
发明人： Robert J. Proebsting
IPC分类号： G05F110
CPC分类号： G05F3/205 , G11C5/146 , H02M3/073 , H02M2001/0032 , H02M2003/071 , H02M2003/075 , H03B5/04 , Y02B70/16
摘要： A low voltage current source generates low voltage signals for powering a variable frequency oscillator. The low voltage signals are at a slightly higher voltage until a negative substrate bias is achieved. The oscillator operates at a low frequency for low power consumption when no charge pumping is needed and at a higher frequency when charge pumping is in fact needed or when charge pumping will most likely be needed. The variable frequency oscillator controls a timing signal generator which generates the timing signals used to control the overall operation of the charge pump system. Voltage translation circuitry translates the low voltage current source signals into higher voltage signals which are used to translate the substrate voltage from its negative value to a positive value so that the substrate voltage may be compared to a reference voltage using a conventional comparator. When the substrate voltage is above the desired level, the comparator generates a pump activating signals to a pump signal generator which, in turn, generates the necessary signal to cause the charge pump to operate.

92. 发明授权

US6163475A Bit line cross-over layout arrangement 有权
标题翻译：位线交叉布局布置
公开(公告)号：US6163475A
公开(公告)日：2000-12-19
申请号：US285232
申请日：1999-04-01
申请人： Robert J. Proebsting
发明人： Robert J. Proebsting
IPC分类号： G11C7/06 , G11C7/12 , G11C7/18 , G11C7/22 , G11C8/08 , G11C11/4091 , H01L21/8242 , H01L27/108 , G11C5/06
CPC分类号： G11C11/4091 , G11C7/04 , G11C7/065 , G11C7/12 , G11C7/18 , G11C7/22 , G11C8/08 , G11C2207/104 , G11C2207/229 , H01L27/10891 , H01L27/10897
摘要： A novel crossover arrangement reduces the area of a memory array by using only one crossover structure within each array block. Yet the total differential signal degradation for each respective true and complement bit line pair arising from coupling between the respective true bit line and the respective complement bit line as well as differential coupling to the respective true and complement bit lines from unrelated adjacent true or complement bit lines, is no worse than that resulting from a true bit line being adjacent to its complement bit line for their entire length. For one embodiment of the invention, each complementary pair of bit lines runs vertically within an array block from the top to the bottom of the array block. The true bit line and complement bit line of a first pair run adjacent to each other from the top to the bottom of the array block without any crossovers. The true bit line and complement bit line of a second pair do not run adjacent to each other, but instead straddle the first pair (i.e., both true and complement bit lines of the first pair lie between the true and complement bit lines of the second pair), with a single crossover half-way down the second bit line pair (vertically in the middle of the array block). This crossover arrangement repeats horizontally throughout each array block in groups of two pairs of bit lines (four physical bit line wires). By using this crossover arrangement, if guard cells are used only four groups of guard cells are needed in each array block-one each at the top and bottom of the array block, and one each at the top and bottom of the single crossover structure located preferably at the vertical center of the array block.
摘要翻译：新颖的交叉排列通过在每个阵列块内仅使用一个交叉结构来减小存储器阵列的面积。然而，由相应的真位线和相应的补码位线之间的耦合产生的每个相应的真和补码位线对的总差分信号衰减以及从不相关的相邻真或补位产生的相应真和补码位线的差分耦合线不会比真正的位线在其整个长度上与其补码位线相邻所产生的差。对于本发明的一个实施例，每个互补的位线对在阵列块内从阵列块的顶部到底部垂直延伸。第一对的真位线和补码位线从阵列块的顶部到底部彼此相邻运行，没有任何交叉。第二对的真位线和补码位线不会彼此相邻运行，而是跨越第一对（即，第一对的真位和补码位线位于第二对的真位和补位之间）对），在第二位线对（在阵列块的中间垂直）中间单向交叉。这种交叉排列在两组位线（四条物理位线）的组中在每个阵列块中水平地重复。通过使用这种交叉布置，如果使用保护单元，则在每个阵列块中仅需要四组保护单元，每组在阵列块的顶部和底部，每个位于单个交叉结构的顶部和底部，优选地在阵列块的垂直中心处。

93. 发明授权

US6137335A Oscillator receiving variable supply voltage depending on substrate voltage detection 有权
标题翻译：振荡器根据基板电压检测接收可变电源电压
公开(公告)号：US6137335A
公开(公告)日：2000-10-24
申请号：US324932
申请日：1999-06-03
申请人： Robert J. Proebsting
发明人： Robert J. Proebsting
IPC分类号： G05F3/20 , G06F17/30 , G11C5/14 , H02M3/07 , H03B5/04 , H03H11/26
CPC分类号： G05F3/205 , G11C5/146 , H02M3/073 , H03B5/04 , H02M2001/0032 , H02M2003/071 , H02M2003/075 , Y02B70/16
摘要： A low voltage current source generates low voltage signals for powering a variable frequency oscillator. The low voltage signals are at a slightly higher voltage until a negative substrate bias is achieved. The oscillator operates at a low frequency for low power consumption when no charge pumping is needed and at a higher frequency when charge pumping is in fact needed or when charge pumping will most likely be needed. The variable frequency oscillator controls a timing signal generator which generates the timing signals used to control the overall operation of the charge pump system. Voltage translation circuitry translates the low voltage current source signals into higher voltage signals which are used to translate the substrate voltage from its negative value to a positive value so that the substrate voltage may be compared to a reference voltage using a conventional comparator. When the substrate voltage is above the desired level, the comparator generates a pump activating signals to a pump signal generator which, in turn, generates the necessary signal to cause the charge pump to operate.
摘要翻译：低压电流源产生低电压信号，为变频振荡器供电。低电压信号处于略高的电压，直到达到负的衬底偏置。当不需要电荷泵浦时，振荡器以低频率工作，并且在实际需要电荷泵送时或者最有可能需要电荷泵浦时，频率较高。可变频率振荡器控制定时信号发生器，其产生用于控制电荷泵系统的总体操作的定时信号。电压转换电路将低电压电流源信号转换成更高电压信号，其用于将衬底电压从其负值转换为正值，使得可以使用常规比较器将衬底电压与参考电压进行比较。当衬底电压高于所需电平时，比较器产生泵激活信号到泵信号发生器，泵反过来产生必要的信号以使电荷泵工作。

94. 发明授权

US6031783A High speed video frame buffer 有权
公开(公告)号：US6031783A
公开(公告)日：2000-02-29
申请号：US179260
申请日：1998-10-26
申请人： Robert J. Proebsting
发明人： Robert J. Proebsting
IPC分类号： G11C8/12 , H04N9/64 , G11C7/00
CPC分类号： G11C8/12
摘要： A memory circuit achieves much higher bandwidth and reduced power consumption by maintaining the maximum number of memory arrays open simultaneously. Circuit area is also saved by sharing bit line sense amplifiers between adjacent arrays. When selected, an array remains open until a different row in the same array or an array adjacent to it is selected. Thus, as long as access is made to an open row of every other array, access time and power are reduced by eliminating the need to turn arrays on and off.

95. 发明授权

US5939919A Clock signal distribution method for reducing active power dissipation 失效
标题翻译：降低有功功耗的时钟信号分配方法
公开(公告)号：US5939919A
公开(公告)日：1999-08-17
申请号：US901594
申请日：1997-07-28
申请人： Robert J. Proebsting
发明人： Robert J. Proebsting
IPC分类号： G06F1/04 , G06F1/08 , G06F1/10 , G11C11/407 , H03K3/00 , H03K5/00 , H03K21/02 , H03K1/04
CPC分类号： G06F1/10 , H03K5/00006
摘要： A clocking scheme is provided which uses an external clock signal having a frequency F, and generates an internal master clock signal equal having a frequency lower than (e.g., 1/2) F. The internal master clock signal operating at, for example, half the speed of the external clock is routed throughout a device to components on the device requiring a clock signal (e.g., input or output buffers in a synchronous memory product). A stream of narrow pulses corresponding to rising and falling edges of the internal master clock signal are locally generated for those components which require a clock signal at full frequency. This stream of narrow pulses has a frequency of F.
摘要翻译：提供了一种使用具有频率F的外部时钟信号的时钟方案，并产生等于具有低于（例如+ E，fra 1/2 + EE）F的频率的内部主时钟信号。内部主时钟信号操作例如，外部时钟的一半速度通过整个设备被路由到需要时钟信号的设备上的组件（例如，同步存储器产品中的输入或输出缓冲器）。与内部主时钟信号的上升沿和下降沿对应的窄脉冲流局部地产生于需要全频率时钟信号的那些部件。这个窄脉冲流的频率为F.

96. 发明授权

US5936905A Self adjusting delay circuit and method for compensating sense amplifier clock timing 失效
标题翻译：自适应延迟电路和补偿读出放大器时钟时序的方法
公开(公告)号：US5936905A
公开(公告)日：1999-08-10
申请号：US890584
申请日：1997-07-09
申请人： Robert J. Proebsting
发明人： Robert J. Proebsting
IPC分类号： G11C11/419 , G11C7/02 , G11C7/06 , G11C11/407 , G11C11/409
CPC分类号： G11C7/02 , G11C7/06 , G11C7/08 , G11C7/227
摘要： A circuit technique that optimizes the activation timing of a dynamic sense amplifier includes a circuit that closely tracks process variations to generate the optimum activation signal for the dynamic sense amplifier. In another embodiment, the activation timing for the dynamic sense amplifier is made programmable on a chip-by-chip basis to not only arrive at the optimal timing for the activation signal, but to also enable the manufacturer to guarantee a certain amount of margin in the operation of the circuit.
摘要翻译：优化动态读出放大器的激活定时的电路技术包括紧密跟踪过程变化以产生用于动态读出放大器的最佳激活信号的电路。在另一个实施例中，动态读出放大器的激活定时是逐个可编程的，不仅可以达到激活信号的最佳定时，而且使制造商能够保证一定量的余量电路的运行。

97. 发明授权

US5926050A Separate set/reset paths for time critical signals 失效
标题翻译：用于时间关键信号的单独设置/复位路径
公开(公告)号：US5926050A
公开(公告)日：1999-07-20
申请号：US885145
申请日：1997-06-30
申请人： Robert J. Proebsting
发明人： Robert J. Proebsting
IPC分类号： H03K19/00 , H03K19/003 , H03K19/017 , H03K5/12
CPC分类号： H03K19/0013 , H03K19/00323 , H03K19/01721
摘要： A digital system includes apparatus for propagating falling and rising edges of a digital signal through two separate data paths each optimized to maximize propagation of one edge of the signal. The first data path is structured to propagate the first transition (e.g., falling edge) of the digital signal with a delay less than that experienced by the second transition (rising edge); and the second data path is structured to propagate the second transition with much less delay than that experienced by the first data transitions. The outputs of the two data paths are applied to a combining circuit, and put together to form a final representation of the digital signal to use the first and second state transitions as propagated by the apparatus.
摘要翻译：数字系统包括用于通过两个单独的数据路径传播数字信号的下降沿和上升沿的装置，每个数据路径被优化以最大化信号的一个边缘的传播。第一数据路径被构造为以比第二转变（上升沿）经历的延迟更小的延迟传播数字信号的第一转换（例如，下降沿）; 并且第二数据路径被构造为以比由第一数据转换所经历的延迟少得多的延迟来传播第二转换。两个数据路径的输出被施加到组合电路，并且放在一起以形成数字信号的最终表示，以使用由设备传播的第一和第二状态转换。

98. 发明授权

US5793383A Shared bootstrap circuit 失效
标题翻译：共享引导电路
公开(公告)号：US5793383A
公开(公告)日：1998-08-11
申请号：US656165
申请日：1996-05-31
申请人： Robert J. Proebsting
发明人： Robert J. Proebsting
IPC分类号： G11C11/407 , G11C8/08 , G11C8/10 , G11C11/401 , G09G5/00 , G11C8/00
CPC分类号： G11C8/08 , G11C8/10
摘要： A memory device according to the invention includes at least first and second memory arrays having a number of word lines. Each of the word lines are coupled to a shared word line bootstrap circuit so that every word line from the first array shares a bootstrap circuit with a word line from the second array.
摘要翻译：根据本发明的存储器件至少包括具有多个字线的第一和第二存储器阵列。每个字线被耦合到共享字线引导电路，使得来自第一阵列的每个字线与来自第二阵列的字线共享自举电路。

99. 发明授权

US5740116A Current limiting during block writes of memory circuits 失效
标题翻译：存储器电路的写入期间的电流限制
公开(公告)号：US5740116A
公开(公告)日：1998-04-14
申请号：US578885
申请日：1995-12-22
申请人： Robert J. Proebsting
发明人： Robert J. Proebsting
IPC分类号： G11C11/409 , G11C7/06 , G11C7/10 , G11C11/401 , H01L21/8242 , H01L27/108 , G11C7/00
CPC分类号： G11C7/1015 , G11C7/065
摘要： A circuit and a method for limiting current during block write operations in memory integrated circuits such as graphics or video RAMs. A bias line for all sense amplifiers located between two memory sub-arrays is divided into independent segments connected to groups of sense amplifiers. Each segment is biased by a separate sense amplifier enable transistor. With much reduced loading, each enable transistor connected to a segmented bias line is significantly smaller in size. Thus, the sense amplifier crowbar or switching current is significantly reduced when writing a block of data of opposite polarity into a block of memory cells.
摘要翻译：在诸如图形或视频RAM的存储器集成电路中在块写入操作期间限制电流的电路和方法。位于两个存储器子阵列之间的所有读出放大器的偏置线被分成连接到读出放大器组的独立段。每个段由独立的读出放大器使能晶体管偏置。随着负载的减少，连接到分段偏置线的每个使能晶体管的尺寸明显更小。因此，当将相反极性的数据块写入到存储器单元块中时，读出放大器撬棒或开关电流显着减小。

100. 发明授权

US5731713A TTL to CMOS level translator with voltage and threshold compensation 失效
标题翻译： TTL至CMOS电平转换器，具有电压和阈值补偿
公开(公告)号：US5731713A
公开(公告)日：1998-03-24
申请号：US704179
申请日：1996-08-27
申请人： Robert J. Proebsting , Hyunsoo Sim
发明人： Robert J. Proebsting , Hyunsoo Sim
IPC分类号： H03K19/00 , G11C7/10 , H03K19/003 , H03K19/0185 , H03K19/094
CPC分类号： G11C7/1084 , G11C7/1078 , H03K19/00361 , H03K19/00384 , H03K19/018521 , H01L2924/0002
摘要： A CMOS input buffer is described for such CMOS circuits as dynamic random access memories, microprocessors, and the like, for receiving TTL logic high and low level signals. The input buffer includes an input stage formed from a p-channel and n-channel MOS transistors configured to have substantially equal transconductances, connected to form a series current path between a bias voltage and a lower voltage (e.g., ground), setting the trip point of the input stage approximately midway between the typically specified TTL logic high and low levels. The differential between the bias and lower voltages from which the input buffer operates assures that at least one of the MOS transistors is off for a TTL logic high or low level input, obviating power consumption while the input signal is at such level. The input buffer is also made insensitive to symmetrical power supply noise, consumes less power, and is made insensitive to threshold voltage variations.
摘要翻译：对于用于接收TTL逻辑高电平和低电平信号的诸如动态随机存取存储器，微处理器等的CMOS电路，描述了CMOS输入缓冲器。输入缓冲器包括由p沟道形成的输入级和被配置为具有基本上相等的跨导的n沟道MOS晶体管，被连接以在偏置电压和较低电压（例如，接地）之间形成串联电流路径，设定跳闸输入级的大部分点在典型的TTL逻辑高电平和低电平之间。输入缓冲器工作的偏置电压和较低电压之间的差值保证至少一个MOS晶体管关断TTL逻辑高电平或低电平输入，从而消除功耗，同时输入信号处于该电平。输入缓冲器也对对称电源噪声不敏感，消耗更少的功率，并且对阈值电压变化不敏感。

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