专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明申请

US20100283700A1 Antennas Using Chip-Package Interconnections for Millimeter-wave Wireless Communication 有权
标题翻译：天线使用芯片封装相互连接用于毫米波无线通信
公开(公告)号：US20100283700A1
公开(公告)日：2010-11-11
申请号：US12437809
申请日：2009-05-08
申请人： Fnu Rajanish , Nitin Jain , Gaurav Menon , Angelos Alexanian
发明人： Fnu Rajanish , Nitin Jain , Gaurav Menon , Angelos Alexanian
IPC分类号： H01Q1/00 , H01Q9/16
CPC分类号： H01Q9/16 , H01L23/66 , H01L24/48 , H01L24/49 , H01L2223/6611 , H01L2223/6677 , H01L2224/05554 , H01L2224/056 , H01L2224/48011 , H01L2224/48091 , H01L2224/484 , H01L2224/49171 , H01L2224/49175 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/3025 , H01Q1/2283 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： A compact millimeter-wave transmitter and receiver make use of interconnections within a chip-containing package for providing an integrated antenna. Due to shorter wavelength of millimeter-waves, these interconnections can be used as antennas for radiation of electromagnetic waves. A dielectric cover or lens is provided within the package to increase the antenna's directivity and to provide a mechanical shield for the chip.
摘要翻译：紧凑型毫米波发射器和接收器利用包含芯片的封装内的互连来提供集成天线。由于毫米波的波长较短，这些互连可用作电磁波辐射的天线。在封装内提供电介质盖或透镜，以增加天线的方向性，并为芯片提供机械屏蔽。

92. 发明申请

US20100157699A1 WRITE CIRCUITRY FOR HIERARCHICAL MEMORY ARCHITECTURE 有权
标题翻译：用于分层存储器架构的写入电路
公开(公告)号：US20100157699A1
公开(公告)日：2010-06-24
申请号：US12641102
申请日：2009-12-17
申请人： Siddharth GUPTA , Nitin JAIN , Anand MISHRA
发明人： Siddharth GUPTA , Nitin JAIN , Anand MISHRA
IPC分类号： G11C11/416 , G11C8/00 , G11C8/18 , G11C7/10
CPC分类号： G11C7/1096 , G11C7/18 , G11C7/22 , G11C8/12 , G11C8/18 , G11C11/413
摘要： A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.
摘要翻译：存储器架构包括多个本地输入和输出电路，其中每个本地输入和输出电路与至少一个存储体相关联。存储器架构还包括全局输入和输出电路，其包括多个全局子写入电路，耦合到多个本地输入和输出电路。一个全局子写入电路被使能，并将写入数据提供给选择本地输入和输出电路。

93. 发明申请

US20100091188A1 SYNCHRONIZATION OF SECONDARY DECODED MEDIA STREAMS WITH A PRIMARY MEDIA STREAM 审中-公开
标题翻译：二级解码媒体流与主媒体流的同步
公开(公告)号：US20100091188A1
公开(公告)日：2010-04-15
申请号：US12500692
申请日：2009-07-10
申请人： Kausik Maiti , Philippe Monnier , Shiv Kumar Singh , Rahul Bansal , Nitin Jain , Bharat Jauhari
发明人： Kausik Maiti , Philippe Monnier , Shiv Kumar Singh , Rahul Bansal , Nitin Jain , Bharat Jauhari
IPC分类号： H04N7/00 , H04N9/76 , H04N7/16 , H04N5/91
CPC分类号： H04N21/4305 , G11B20/10527 , G11B27/034 , G11B27/10 , G11B2020/10546 , G11B2020/10574 , G11B2020/10842 , G11B2220/90
摘要： System and method for synchronizing one or more secondary decoded media streams to a primary decoded media stream. The system includes a media stream processor and a mixer. The media stream processor receives a primary decoded media stream and secondary decoded media streams. The media stream processor synchronizes the secondary decoded media streams with the primary decoded media stream. The output of the media stream processor is coupled to the mixer. The mixer receives its second input from the primary decoded media stream. The mixer mixes the received streams and generates a PTS value for its output media stream by extrapolating the PTS of the primary decoded media stream.
摘要翻译：用于将一个或多个二次解码的媒体流同步到主要解码的媒体流的系统和方法。该系统包括媒体流处理器和混音器。媒体流处理器接收主解码的媒体流和二次解码的媒体流。媒体流处理器将二次解码的媒体流与主要解码的媒体流同步。媒体流处理器的输出耦合到混频器。混合器从主解码的媒体流接收其第二输入。混合器混合接收到的流，并通过外推初步解码的媒体流的PTS，为其输出媒体流生成PTS值。

94. 发明申请

US20100046556A1 Priority Aware MAC Flow Control 有权
标题翻译：优先级MAC流量控制
公开(公告)号：US20100046556A1
公开(公告)日：2010-02-25
申请号：US12615142
申请日：2009-11-09
申请人： Nitin Jain , Rajkumar Jalan
发明人： Nitin Jain , Rajkumar Jalan
IPC分类号： H04J3/24
CPC分类号： H04L47/10 , G06F15/17368 , H04L12/2852 , H04L47/2433
摘要： Solutions are provided that allow a network device to apply flow control on the MAC layer while taking into account the priority of the frame of traffic. This may be accomplished by generating a frame indicating that traffic flow should be paused, while utilizing a new opcode value, or alternatively by utilizing a new type/length value (possibly combined with a new opcode value). A receiving device may then examine the fields of the frame to determine whether it should it should use priority-based pausing, and then examine other fields to determine which priority-levels to pause and for how long. This allows for improved efficiency in flow control on the MAC layer.
摘要翻译：提供的解决方案允许网络设备在考虑到流量帧的优先级的情况下对MAC层应用流量控制。这可以通过生成指示业务流应该被暂停，同时利用新的操作码值，或者通过利用新的类型/长度值（可能与新的操作码值组合）来实现。然后，接收设备可以检查帧的字段以确定是否应该使用基于优先级的暂停，然后检查其他字段以确定要暂停的优先级等级以及多长时间。这样可以提高MAC层的流量控制效率。

95. 发明授权

US07639608B1 Priority aware MAC flow control 有权
标题翻译：优先级感知MAC流量控制
公开(公告)号：US07639608B1
公开(公告)日：2009-12-29
申请号：US10693037
申请日：2003-10-23
申请人： Nitin Jain , Rajkumar Jalan
发明人： Nitin Jain , Rajkumar Jalan
IPC分类号： H04L12/28 , H04L12/56 , G06F15/16
CPC分类号： H04L47/10 , G06F15/17368 , H04L12/2852 , H04L47/2433
摘要： Solutions are provided that allow a network device to apply flow control on the MAC layer while taking into account the priority of the frame of traffic. This may be accomplished by generating a frame indicating that traffic flow should be paused, while utilizing a new opcode value, or alternatively by utilizing a new type/length value (possibly combined with a new opcode value). A receiving device may then examine the fields of the frame to determine whether it should it should use priority-based pausing, and then examine other fields to determine which priority-levels to pause and for how long. This allows for improved efficiency in flow control on the MAC layer.
摘要翻译：提供的解决方案允许网络设备在考虑到流量帧的优先级的情况下对MAC层应用流量控制。这可以通过生成指示业务流应该被暂停，同时利用新的操作码值，或者通过利用新的类型/长度值（可能与新的操作码值组合）来实现。然后，接收设备可以检查帧的字段以确定是否应该使用基于优先级的暂停，然后检查其他字段以确定要暂停的优先级等级以及多长时间。这样可以提高MAC层的流量控制效率。

96. 发明申请

US20090205011A1 CHANGE RECOMMENDATIONS FOR COMPLIANCE POLICY ENFORCEMENT 有权
标题翻译：更改遵守政策执行的建议
公开(公告)号：US20090205011A1
公开(公告)日：2009-08-13
申请号：US12029049
申请日：2008-02-11
申请人： Nitin Jain , Amit Bhalla , Sourav Mukherjee , Macks Ningombam
发明人： Nitin Jain , Amit Bhalla , Sourav Mukherjee , Macks Ningombam
IPC分类号： G06F11/30
CPC分类号： G06F8/65
摘要： Some embodiments of the present invention provide a system for maintaining a software system. During operation, the system obtains a compliance policy for the software system and monitors the software system for a violation of the compliance policy. If a violation is detected, the system generates a change recommendation associated with the violation using the compliance policy and provides the change recommendation to an administrator, so that the administrator can use the change recommendation to resolve the violation.
摘要翻译：本发明的一些实施例提供了一种用于维护软件系统的系统。在运行期间，系统获得软件系统的合规性策略，并监视软件系统违反合规策略。如果检测到违规，则系统使用合规性策略生成与违规相关联的更改建议，并向管理员提供更改建议，以便管理员可以使用更改建议来解决违规。

97. 发明申请

US20050282503A1 Combined matching and filter circuit 有权
标题翻译：组合匹配和滤波电路
公开(公告)号：US20050282503A1
公开(公告)日：2005-12-22
申请号：US10872947
申请日：2004-06-21
申请人： Peter Onno , Rajanish , Nitin Jain , Christopher Weigand
发明人： Peter Onno , Rajanish , Nitin Jain , Christopher Weigand
IPC分类号： H03H2/00 , H03H7/01 , H03H7/09 , H03H7/38 , H04B1/00
CPC分类号： H03H7/1758 , H03H7/0115 , H03H7/0123 , H03H7/1766 , H03H7/1783 , H03H7/1791 , H03H7/38 , H03H2001/0064 , H03H2001/0078
摘要： A combined matching and harmonic rejection circuit with increased harmonic rejection provided by a split resonance for one or more of the capacitive or inductive elements of the circuit. At a fundamental frequency, the circuit comprises an inductive series arm with capacitive shunt arms. The capacitance of a shunt arm may be provided by two or more parallel paths, each having a capacitor and an inductor in series so that, in addition to providing the effective capacitance necessary for impedance matching at the fundamental frequency, two separate harmonics represented by the series resonances of the parallel paths are rejected. In this manner, an extra null in the circuit's stop-band may be achieved using the same number of shunt elements necessary to achieve impedance matching at the fundamental frequency.
摘要翻译：一种组合匹配和谐波抑制电路，其具有由电路的一个或多个电容或电感元件的分裂谐振提供的增加的谐波抑制电路。在基频处，电路包括具有电容分流臂的感应串联臂。分流臂的电容可以由两个或更多个并联路径提供，每个并联路径具有串联的电容器和电感器，使得除了提供在基频处的阻抗匹配所必需的有效电容之外，由并行路径的串联谐振被拒绝。以这种方式，可以使用在基频实现阻抗匹配所需的相同数量的并联元件来实现电路的阻带中的额外零点。

98. 发明授权

US6133805A Isolation in multi-layer structures 失效
标题翻译：多层结构中的隔离
公开(公告)号：US6133805A
公开(公告)日：2000-10-17
申请号：US71568
申请日：1998-05-01
申请人： Nitin Jain , John Stephen Atherton , Paul John Schwab , Graham J. H. Wells
发明人： Nitin Jain , John Stephen Atherton , Paul John Schwab , Graham J. H. Wells
IPC分类号： H01P3/08 , H05K1/00 , H05K1/02 , H05K3/42 , H01P5/00
CPC分类号： H01P3/088 , H05K1/0219 , H05K1/0298 , H05K2201/09618 , H05K2201/09718 , H05K2201/0979 , H05K2201/09854 , H05K3/429
摘要： An apparatus for propagating high frequency energy hag a wavelength of .lambda. in a dielectric medium has first and second signal lines, substantially coplanar with each other, and carrying high frequency energy, A ground trace separates the signal lines and has a plurality of vias, each spaced a distance greater than one quarter .lambda. and less than one half .lambda. apart from another one of the vias.
摘要翻译：用于在电介质介质中传播λ波长的高频能量的装置具有彼此基本上共面并且承载高频能量的第一和第二信号线，A接地迹线分离信号线并且具有多个通孔间隔大于四分之一λ的距离，并且距另一个通孔的距离小于一半。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式