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91. 发明授权

US07606302B2 Method and apparatus for non-linear decision-feedback equalization in the presence of asymmetric channel 有权
标题翻译：在存在非对称信道的情况下进行非线性判决反馈均衡的方法和装置
公开(公告)号：US07606302B2
公开(公告)日：2009-10-20
申请号：US11541379
申请日：2006-09-29
申请人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
发明人： Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03057 , H04B10/695
摘要： Methods and apparatus are provided for determining the threshold position of one or more latches employed for decision-feedback equalization in the presence of a non-linear channel. A latch employed by a decision-feedback equalizer is positioned by constraining input data such that the input data only contains transitions from a first binary value; obtaining a plurality of samples of a single-sided data eye associated with the constrained input data; determining a threshold position of the latch based on the samples; and transforming the determined position to address the non-linearity of the channel. For example, a non-linear mapping table can map measured threshold values to transformed threshold values based on distance.
摘要翻译：提供了用于在存在非线性通道的情况下确定用于判决反馈均衡的一个或多个锁存器的阈值位置的方法和装置。由判决反馈均衡器采用的锁存器通过约束输入数据来定位，使得输入数据仅包含来自第一二进制值的转换; 获得与所述约束输入数据相关联的单面数据眼睛的多个样本; 基于所述样本确定所述锁存器的阈值位置; 并且变换确定的位置以解决信道的非线性。例如，非线性映射表可以将测量的阈值映射到基于距离的变换的阈值。

92. 发明申请

US20090086807A1 METHODS AND APPARATUS FOR DETERMINING THRESHOLD OF ONE OR MORE DFE TRANSITION LATCHES BASED ON INCOMING DATA EYE 有权
标题翻译：用于确定基于入眼数据的一个或多个DFE转换锁存器的阈值的方法和装置
公开(公告)号：US20090086807A1
公开(公告)日：2009-04-02
申请号：US11864110
申请日：2007-09-28
申请人： Pervez M. Aziz , Mohammad S. Mobin
发明人： Pervez M. Aziz , Mohammad S. Mobin
IPC分类号： H04L27/01
CPC分类号： H04L25/03063 , H04L25/0307
摘要： Methods and apparatus are provided for determining the threshold position of one or mote DFE latches using an evaluation of the incoming data eye. A threshold position is determined for one or more transition latches employed by a decision-feedback equalizer by obtaining a plurality of samples of a data eye using a data eye monitor; obtaining a vertical eye opening metric from the data eye monitor; and determining the threshold position for the one or more transition latches based on the vertical eye opening metric. A decision-feedback equalizer is also disclosed that comprises at least one data latch having a data threshold; and at least one transition latching having a transition threshold, wherein the transition threshold and the data threshold ate unequal
摘要翻译：提供方法和装置，用于使用输入数据眼的评估来确定一个或微尘DFE锁存器的阈值位置。通过使用数据眼睛监视器获得数据眼睛的多个采样来确定由判决反馈均衡器采用的一个或多个转换锁存器的阈值位置; 从数据眼监视器获得垂直眼睛开度度量; 以及基于所述垂直眼图开度度量确定所述一个或多个过渡锁存器的阈值位置。还公开了一种包括具有数据阈值的至少一个数据锁存器的判决反馈均衡器; 以及至少一个具有转变阈值的转换锁存器，其中转换阈值和数据阈值不相等

93. 发明授权

US07495494B2 Parallel trimming method and apparatus for a voltage controlled delay loop 有权
标题翻译：用于电压控制延迟回路的平行修整方法和装置
公开(公告)号：US07495494B2
公开(公告)日：2009-02-24
申请号：US11141703
申请日：2005-05-31
申请人： Ronald L. Freyman , Mohammad S. Mobin , Vladimir Sindalovsky , Lane A. Smith
发明人： Ronald L. Freyman , Mohammad S. Mobin , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： H03H11/26
CPC分类号： H03L7/0814 , H04L7/0337
摘要： A parallel trimming method and apparatus are provided for a voltage controlled delay loop. A plurality of delay units in a voltage controlled delay loop are trimmed. Each delay unit comprises a delay element and a latch buffer. A reference signal is applied to each of the delay units and a position of an edge (such as a rising or falling edge) associated with each of the delay units is identified. The edges of the delay units are then aligned by adjusting a trim setting of the respective latch buffer.
摘要翻译：提供了一种用于电压控制延迟环路的并行修整方法和装置。电压控制延迟环中的多个延迟单元被修整。每个延迟单元包括延迟元件和锁存缓冲器。参考信号被施加到每个延迟单元，并且识别与每个延迟单元相关联的边缘（例如上升沿或下降沿）的位置。然后通过调整相应的锁存缓冲器的修整设置来对准延迟单元的边缘。

94. 发明申请

US20080225734A1 METHOD AND APPARATUS FOR DATA RATE DETECTION USING A DATA EYE MONITOR 有权
标题翻译：使用数据眼监视器进行数据速率检测的方法和装置
公开(公告)号：US20080225734A1
公开(公告)日：2008-09-18
申请号：US11686144
申请日：2007-03-14
申请人： Dwight D. Daugherty , Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
发明人： Dwight D. Daugherty , Mohammad S. Mobin , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy
IPC分类号： H04J1/16
CPC分类号： H04L25/0262
摘要： Methods and apparatus are provided for data rate detection using a data eye monitor. The data rate is one of a plurality of data rates comprising a base rate and one or more divide-by-N multiples of the base rate, where N is an integer. The data rate of a received signal is detected by sampling the received signal; comparing the samples for a plurality of full rate data eyes associated with the received signal to determine if there is a mismatch between at least two predefined samples; and detecting the data rate by evaluating the comparison based on predefined criteria. The comparison can be performed by an exclusive or (XOR) logic gate for samples of at least two adjacent data eyes of a given rate.
摘要翻译：提供了使用数据眼监视器进行数据速率检测的方法和装置。数据速率是包括基本速率和基本速率的一个或多个除以N倍数的多个数据速率之一，其中N是整数。通过对接收到的信号进行采样来检测接收信号的数据速率; 比较与所接收的信号相关联的多个全速率数据眼睛的样本，以确定是否存在至少两个预定样本之间的不匹配; 以及通过基于预定标准评估比较来检测数据速率。可以通过异或（XOR）逻辑门对给定速率的至少两个相邻数据眼的样本执行比较。

95. 发明申请

US20080191789A1 Method and apparatus for adjusting a power supply of an integrated circuit 有权
标题翻译：用于调整集成电路的电源的方法和装置
公开(公告)号：US20080191789A1
公开(公告)日：2008-08-14
申请号：US12012761
申请日：2008-02-05
申请人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
发明人： Joseph Anidjar , Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： G05F1/10
CPC分类号： H03K19/0027 , G06F1/3203 , H03K19/00384 , Y10T307/74
摘要： Disclosed is a circuit configured to apply a supply voltage to a switching element (e.g., a transistor). The circuit includes a latch and a processor. The latch is configured to sample a voltage of an output signal of the switching element, and the processor is configured to generate a power adjustment signal to adjust the supply voltage based on the voltage sampled by the latch.
摘要翻译：公开了一种被配置为向开关元件（例如，晶体管）施加电源电压的电路。该电路包括一个锁存器和一个处理器。锁存器被配置为对开关元件的输出信号的电压进行采样，并且处理器被配置为产生功率调整信号，以基于由锁存器采样的电压来调节电源电压。

96. 发明授权

US07312667B2 Statically controlled clock source generator for VCDL clock phase trimming 失效
标题翻译：用于VCDL时钟相位修整的静态时钟源发生器
公开(公告)号：US07312667B2
公开(公告)日：2007-12-25
申请号：US11221316
申请日：2005-09-07
申请人： Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith , Craig B. Ziemer
发明人： Mohammad S. Mobin , Gregory W. Sheets , Vladimir Sindalovsky , Lane A. Smith , Craig B. Ziemer
IPC分类号： H03B27/00
CPC分类号： H03L7/00 , H04L7/0337
摘要： The present invention addresses the generation of a controlled clock source for use in trimming VCDL delay line output clocks. In this trimming process, adjustments are made for static variations in these output clocks. The invention's use of a controlled clock source eliminates the need for this trimming process to be conducted in real time and reduces the expense of the circuitry required.
摘要翻译：本发明解决了用于微调VCDL延迟线输出时钟的受控时钟源的产生。在这个修整过程中，对这些输出时钟的静态变化进行调整。本发明使用受控的时钟源消除了对该修整过程的实时性的需要，并且降低了所需电路的费用。

97. 发明授权

US06791991B1 Channel sequencing using a round-robin scheduler 失效
标题翻译：频道排序使用循环调度程序
公开(公告)号：US06791991B1
公开(公告)日：2004-09-14
申请号：US09702366
申请日：2000-10-31
申请人： Mohammad S. Mobin , Kalyan Mondal , Himanshu M. Thaker
发明人： Mohammad S. Mobin , Kalyan Mondal , Himanshu M. Thaker
IPC分类号： H04J317
CPC分类号： H04L47/6225 , H04J3/1611 , H04L47/50
摘要： A terminal receives one or more input frames comprising one or more logical channels and may generate one or more output frames including the data received in the logical channels. Each logical channel is dispersed throughout the input frame in one or more timeslots, and each logical channel has an associated buffer. The data of each logical channel received from the timeslot(s) of the input frame(s) is stored in the corresponding buffer. The terminal uses channel sequencing for round-robin scheduling to transfer the data of the received logical channels, if present, in each buffer to one or more output frames. Channel sequencing may apply round-robin scheduling of service of buffers in ascending or descending order of non-empty buffers, accounting for newly filled buffers. Channel sequencing generates a binary word, termed a channels service request (CSR) word, with each bit of the CSR word corresponding to a buffer and indicating whether the buffer requests service. When at least one bit of the CSR word is set, a cycle of round-robin scheduling begins. During a cycle, logic combines the CSR word with a mask to form a masked CSR word, and the mask resets those bits of the CSR word that correspond to newly filled buffers that should be served during the next cycle. The masked CSR word identifies the next, non-empty buffer to be serviced by the buffer server, and the mask generator employs either the CSR word at the beginning of the cycle or the current masked CSR word during the cycle to generate the next mask.
摘要翻译：终端接收包括一个或多个逻辑信道的一个或多个输入帧，并且可以生成包括在逻辑信道中接收的数据的一个或多个输出帧。每个逻辑信道在一个或多个时隙中分散在整个输入帧中，并且每个逻辑信道具有相关联的缓冲器。从输入帧的时隙接收的每个逻辑信道的数据被存储在相应的缓冲器中。终端使用用于循环调度的信道排序来将接收到的逻辑信道的数据（如果存在）在每个缓冲器中传送到一个或多个输出帧。信道排序可以以非空缓冲区的升序或降序顺序对缓冲区的服务进行循环调度，从而占新填充的缓冲区。信道排序产生称为信道服务请求（CSR）字的二进制字，其中CSR字的每个位对应于缓冲器并指示缓冲器是否请求服务。当CSR字的至少一位被设置时，循环调度开始。在一个周期中，逻辑将CSR字与掩码相结合，形成一个掩蔽的CSR字，掩码会重置与下一个周期内应该提供的新填充缓冲区对应的CSR字的那些位。被屏蔽的CSR字识别由缓冲服务器服务的下一个不空的缓冲区，掩码生成器在循环开始时使用CSR字或循环中的当前屏蔽的CSR字以生成下一个掩码。

98. 发明授权

US5465275A Efficient utilization of present state/next state registers 失效
标题翻译：高效利用当前状态/下一状态寄存器
公开(公告)号：US5465275A
公开(公告)日：1995-11-07
申请号：US153334
申请日：1993-11-16
申请人： David M. Blaker , Marc S. Diamondstein , Gregory S. Ellard , Mohammad S. Mobin , Homayoon Sam , Mark E. Thierbach
发明人： David M. Blaker , Marc S. Diamondstein , Gregory S. Ellard , Mohammad S. Mobin , Homayoon Sam , Mark E. Thierbach
IPC分类号： G06F11/10 , H03M13/23 , H03M13/41 , H03M13/45 , H04L25/08 , H04L27/06
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/41
摘要： In accordance with the present invention, a technique for efficiently utilizing memory in determining which next state accumulated cost to retain, such as in a communication system or a Viterbi decoder. The system includes a memory having a portion of registers allocated to a first array and a portion of registers allocated to a second array. The technique includes retrieving a present state accumulated cost from a storage register of the first array and calculating a next state accumulated cost based on the present state accumulated cost. The next state accumulated cost is stored in a storage register of the second array. The second array is designated as containing present state accumulated costs. A present state accumulated cost is retrieved from a storage register of the second array and used in calculating a subsequent next state accumulated cost. The subsequent next state accumulated cost is stored in a storage register of the first array.
摘要翻译：根据本发明，一种用于在诸如通信系统或维特比解码器中确定下一状态累积成本的情况下有效利用存储器的技术。该系统包括具有分配给第一阵列的寄存器的一部分和分配给第二阵列的寄存器的一部分的存储器。该技术包括从第一阵列的存储寄存器检索当前状态累积成本，并基于当前状态累积成本计算下一状态累积成本。下一个状态累积成本被存储在第二阵列的存储寄存器中。第二个阵列被指定为包含当前状态累积成本。从第二阵列的存储寄存器检索当前状态累积成本，并用于计算后续的下一状态累积成本。随后的下一状态累积成本被存储在第一阵列的存储寄存器中。

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