会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 91. 发明申请
    • DUAL MODE PHONE AND SECURITY KEY SETTING METHOD
    • 双模式电话和安全关键设置方法
    • US20100016001A1
    • 2010-01-21
    • US12483230
    • 2009-06-11
    • SHU-MIN YANG
    • SHU-MIN YANG
    • H04W4/12H04M1/00
    • H04W4/12H04L63/18H04W84/12H04W88/06
    • A dual mode phone communicating via a wireless local area network (WLAN) includes a WLAN module, a mobile communication module, and a short message module. The WLAN module communicates via the WLAN and stores a current security key and security mode communicating via the WLAN. The mobile communication module receives a short message via a wireless wide area network, and the short message includes the updated security key and security mode. The short message module receives the short message from the mobile communication module, prompts a user to determine if the current security key and security mode stored in the WLAN module need to be updated, and transmits the updated security key and security mode to the WLAN module if so.
    • 通过无线局域网(WLAN)通信的双模式电话包括WLAN模块,移动通信模块和短消息模块。 WLAN模块通过WLAN进行通信,并存储当前的安全密钥和通过WLAN进行通信的安全模式。 移动通信模块通过无线广域网接收短消息,短消息包括更新的安全密钥和安全模式。 短消息模块从移动通信模块接收短消息,提示用户确定是否需要更新存储在WLAN模块中的当前安全密钥和安全模式,并将更新后的安全密钥和安全模式发送给WLAN模块 如果是这样。
    • 97. 发明授权
    • Substrate engineering for optimum CMOS device performance
    • 基板工程,实现最佳的CMOS器件性能
    • US07482216B2
    • 2009-01-27
    • US11474774
    • 2006-06-26
    • Victor W. C. ChanMeikei IeongMin Yang
    • Victor W. C. ChanMeikei IeongMin Yang
    • H01L21/8238
    • H01L21/823807
    • An integrated semiconductor structure having different types of complementary metal oxide semiconductor devices (CMOS), i.e., PFETs and NFETs, located atop a semiconductor substrate, wherein each CMOS device is fabricated such that the current flow for each device is optimal is provided. Specifically, the structure includes a semiconductor substrate that has a (110) surface orientation and a notch pointing in a direction of current flow; and at least one PFET and at least one NFET located on the semiconductor substrate. The at least one PFET has a current flow in a direction and the at least one NFET has a current flow in a direction. The direction is perpendicular to the direction. A method of fabricating such as integrated semiconductor structure is also provided.
    • 提供了位于半导体衬底顶部的具有不同类型的互补金属氧化物半导体器件(CMOS)即PFET和NFET的集成半导体结构,其中每个CMOS器件被制造成使得每个器件的电流是最佳的。 具体地,该结构包括具有(110)表面取向的半导体衬底和指向电流<001>方向的凹口; 以及位于半导体衬底上的至少一个PFET和至少一个NFET。 所述至少一个PFET具有沿<110>方向的电流,并且所述至少一个NFET具有沿<100>方向的电流。 <110>方向垂直于<100>方向。 还提供了诸如集成半导体结构的制造方法。
    • 100. 发明授权
    • Hybrid orientation CMOS with partial insulation process
    • 混合定向CMOS与部分绝缘工艺
    • US07439542B2
    • 2008-10-21
    • US10958717
    • 2004-10-05
    • Min Yang
    • Min Yang
    • H01L29/04
    • H01L27/1203H01L21/84H01L27/1207
    • The present invention provides a method of integrated semiconductor devices such that different types of devices are formed upon a specific crystallographic orientation of a hybrid substrate. In accordance with the present invention, junction capacitance of one of the devices is improved in the present invention by forming the source/drain diffusion regions of the device in an epitiaxial semiconductor material such that they are situated on a buried insulating layer that extends partially underneath the body of the second semiconductor device. The second semiconductor device, together with the first semiconductor device, is both located atop the buried insulating layer. Unlike the first semiconductor device in which the body thereof is floating, the second semiconductor device is not floating. Rather, it is in contact with an underlying first semiconducting layer.
    • 本发明提供一种集成半导体器件的方法,使得在混合衬底的特定晶体取向上形成不同类型的器件。 根据本发明,通过在外延半导体材料中形成器件的源极/漏极扩散区域,使得它们位于在部分下方延伸的掩埋绝缘层上,从而在本发明中提高了器件之一的结电容 第二半导体器件的主体。 第二半导体器件与第一半导体器件一起位于掩埋绝缘层的上方。 与其主体浮动的第一半导体器件不同,第二半导体器件不浮动。 而是与底层的第一半导体层接触。