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    • 100. 发明申请
    • Gate structure including multi-tunneling layer and method of fabricating the same, non-volatile memory device and method of fabricating the same
    • 包括多隧道层的栅结构及其制造方法,非易失性存储器件及其制造方法
    • US20070114572A1
    • 2007-05-24
    • US11600737
    • 2006-11-17
    • Kwang-Soo SeolWoong-Chul ShinByung KimEun-Kyung LeeKyung-Sang Cho
    • Kwang-Soo SeolWoong-Chul ShinByung KimEun-Kyung LeeKyung-Sang Cho
    • H01L29/76
    • H01L29/42332B82Y10/00H01L27/115H01L29/7881
    • Provided is a gate structure including a multi-tunneling layer and method of fabricating the same. Also provided is a nanodot semiconductor memory device including such gate structure and method of fabricating the same. The gate structure may include a first insulation layer, a second insulation layer, a charge storage layer including nanodots and formed on the second insulation layer, a third insulation layer formed on the charge storage layer, and a gate electrode layer formed on the third insulation layer. There may also be a nanodot semiconductor memory device including a semiconductor substrate, in which a first impurity region and a second impurity region may be formed, and including the gate structure formed on the semiconductor substrate which contacts the first and second impurity regions. The second insulation layer may be formed on the first insulation layer and may include a material whose energy level may be lower than an energy level of the conduction band of the first insulation layer and higher an energy level of the valence band of the first insulation layer.
    • 提供一种包括多隧道层的栅极结构及其制造方法。 还提供了包括这种栅极结构的纳米点半导体存储器件及其制造方法。 栅极结构可以包括第一绝缘层,第二绝缘层,包括纳米点并形成在第二绝缘层上的电荷存储层,形成在电荷存储层上的第三绝缘层,以及形成在第三绝缘层上的栅电极层 层。 还可以存在包括可以形成第一杂质区域和第二杂质区域的半导体衬底的纳米点半导体存储器件,并且包括形成在与第一和第二杂质区域接触的半导体衬底上的栅极结构。 第二绝缘层可以形成在第一绝缘层上,并且可以包括其能级可以低于第一绝缘层的导带的能级的材料,并且第一绝缘层的价带的能级越高 。