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91. 发明授权

US06929901B2 Method for reworking a lithographic process to provide an undamaged and residue free arc layer 失效
标题翻译：对光刻工艺进行再加工以提供无损和无残留弧的层的方法
公开(公告)号：US06929901B2
公开(公告)日：2005-08-16
申请号：US10323376
申请日：2002-12-18
申请人： Ai-Sen Lui , Chun-Hsien Lin
发明人： Ai-Sen Lui , Chun-Hsien Lin
IPC分类号： B08B7/00 , G03F7/09 , G03F7/42
CPC分类号： B08B7/0021 , G03F7/091 , G03F7/422 , G03F7/425
摘要： A method of removing resinous organic material over a semiconductor process surface including providing a semiconductor wafer having a process surface comprising a resinous organic material; and, exposing the process surface to a supercritical CO2 containing medium further comprising at least a first solvent for a predetermined period to produce a substantially resinous organic material free and undamaged process surface.
摘要翻译：一种在半导体工艺表面上去除树脂状有机材料的方法，包括提供具有包含树脂有机材料的工艺表面的半导体晶片; 并且将所述工艺表面暴露于含至少第一溶剂的含超临界含CO 2的介质中预定的时间以产生基本上树脂状的无机材料和未损坏的工艺表面。

92. 发明申请

US20050144584A1 Programmable logic module and upgrade method thereof 失效
标题翻译：可编程逻辑模块及其升级方法
公开(公告)号：US20050144584A1
公开(公告)日：2005-06-30
申请号：US10748963
申请日：2003-12-29
申请人： Tzu-Shern Chen , Chun-Hsien Lin , Ming-Chief Chaw
发明人： Tzu-Shern Chen , Chun-Hsien Lin , Ming-Chief Chaw
IPC分类号： G06F17/50 , H05K1/14
CPC分类号： G06F17/5054 , H05K1/141 , H05K2201/10159 , H05K2201/10212 , H05K2201/10325 , H05K2201/10689
摘要： A programmable logic module. In the programmable logic module, a first printed circuit board has a socket and a downloading unit. A field programmable gate array (FPGA) is disposed on the first printed circuit board. A nonvolatile memory stores program codes for programming the field programmable gate array. The nonvolatile memory is soldered to a second printed circuit board with a plurality of pins corresponding to the socket, and the second printed circuit board is plugged into the socket of the first printed circuit board. The nonvolatile memory downloads program codes thereof to the field programmable gate array by the downloading unit.
摘要翻译：可编程逻辑模块。在可编程逻辑模块中，第一印刷电路板具有插座和下载单元。现场可编程门阵列（FPGA）设置在第一印刷电路板上。非易失性存储器存储用于编程现场可编程门阵列的程序代码。非易失性存储器被焊接到具有与插座对应的多个引脚的第二印刷电路板，并且第二印刷电路板插入第一印刷电路板的插座中。非易失性存储器通过下载单元将其程序代码下载到现场可编程门阵列。

93. 发明授权

US09478627B2 Semiconductor structure and process thereof 有权
标题翻译：半导体结构及其工艺
公开(公告)号：US09478627B2
公开(公告)日：2016-10-25
申请号：US13474730
申请日：2012-05-18
申请人： Chen-Kuo Chiang , Chun-Hsien Lin
发明人： Chen-Kuo Chiang , Chun-Hsien Lin
IPC分类号： H01L29/02 , H01L29/49 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823462 , H01L21/02181 , H01L21/02189 , H01L21/02194 , H01L21/02205 , H01L21/0228 , H01L27/092 , H01L29/42364 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/78
摘要： A semiconductor structure includes a stacked metal oxide layer on a substrate, wherein the stacked metal oxide layer includes a first metal oxide layer, a second metal oxide layer, and a third metal oxide layer from top to bottom, and the energy bandgap of the second metal oxide layer is lower than the energy bandgap of the first metal oxide layer and that of the third metal oxide layer. The semiconductor structure includes a metal oxide layer on a substrate, wherein the energy bandgap of the metal oxide layer changes along a direction perpendicular to the surface of the substrate. The present invention also provides a semiconductor process forming said semiconductor structure.
摘要翻译：半导体结构包括在基板上的堆叠的金属氧化物层，其中堆叠的金属氧化物层包括从顶部到底部的第一金属氧化物层，第二金属氧化物层和第三金属氧化物层，以及第二金属氧化物层的能带隙金属氧化物层比第一金属氧化物层和第三金属氧化物层的能带隙低。半导体结构包括在基板上的金属氧化物层，其中金属氧化物层的能带隙沿着垂直于衬底表面的方向改变。本发明还提供了形成所述半导体结构的半导体工艺。

94. 发明授权

US09142649B2 Semiconductor structure with metal gate and method of fabricating the same 有权
标题翻译：具有金属栅极的半导体结构及其制造方法
公开(公告)号：US09142649B2
公开(公告)日：2015-09-22
申请号：US13454036
申请日：2012-04-23
申请人： An-Chi Liu , Chun-Hsien Lin
发明人： An-Chi Liu , Chun-Hsien Lin
IPC分类号： H01L27/088 , H01L29/66 , H01L29/78 , H01L29/165 , H01L29/49 , H01L29/51
CPC分类号： H01L29/66795 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848 , H01L29/785
摘要： A metal gate process comprises the steps of providing a substrate, forming a dummy gate on said substrate, forming dummy spacers on at least one of the surrounding sidewalls of said dummy gate, forming a source and a drain respectively in said substrate at both sides of said dummy gate, performing a replacement metal gate process to replace said dummy gate with a metal gate, removing said dummy spacers, and forming low-K spacers to replace said dummy spacers.
摘要翻译：金属浇口工艺包括以下步骤：提供衬底，在所述衬底上形成虚拟栅极，在所述伪栅极的至少一个周围侧壁上形成虚设间隔物，分别在所述衬底的两侧形成源极和漏极所述虚拟栅极，执行替换金属栅极工艺以用金属栅极替换所述伪栅极，去除所述虚设间隔物，以及形成低K间隔物以代替所述虚拟间隔物。

95. 发明授权

US09063011B2 Method of signal adjustment in an optical sensing device and the optical sensing device 有权
标题翻译：光学感测装置和光学感测装置中的信号调节方法
公开(公告)号：US09063011B2
公开(公告)日：2015-06-23
申请号：US13074254
申请日：2011-03-29
申请人： Meng-Kun Chen , Chun-Hsien Lin , Yi-Tsung Li
发明人： Meng-Kun Chen , Chun-Hsien Lin , Yi-Tsung Li
IPC分类号： G01J1/44 , G01J1/16
CPC分类号： G01J1/1626
摘要： A method of signal adjustment in an optical sensing device is provided. The optical sensing device includes a first optical sensor and a first reference optical sensor. The first optical sensor corresponds to a first specified ideal spectral response and generates a first output signal corresponding to light detected thereby. The first reference optical sensor generates a first reference signal corresponding to light detected thereby, and is disposed adjacent to the first optical sensor such that the light detected by the first reference optical sensor is substantially the light detected by the first optical sensor. The method includes the steps of: a) receiving the first output signal and the first reference signal; and b) generating a first adjusted output signal having a spectral response that approximates the first specified ideal spectral response, by adjusting the first output signal according to the first reference signal.
摘要翻译：提供了一种在光学传感器件中进行信号调节的方法。光学感测装置包括第一光学传感器和第一参考光学传感器。第一光学传感器对应于第一指定的理想光谱响应，并产生对应于由此检测的光的第一输出信号。第一参考光学传感器产生对应于由此检测的光的第一参考信号，并且被布置为与第一光学传感器相邻，使得由第一参考光学传感器检测到的光基本上是由第一光学传感器检测到的光。该方法包括以下步骤：a）接收第一输出信号和第一参考信号; 以及b）通过根据第一参考信号调整第一输出信号，产生具有近似于第一指定理想频谱响应的频谱响应的第一调整输出信号。

96. 发明授权

US08975672B2 Metal oxide semiconductor transistor and manufacturing method thereof 有权
标题翻译：金属氧化物半导体晶体管及其制造方法
公开(公告)号：US08975672B2
公开(公告)日：2015-03-10
申请号：US13292086
申请日：2011-11-09
申请人： Wen-Tai Chiang , Chun-Hsien Lin
发明人： Wen-Tai Chiang , Chun-Hsien Lin
IPC分类号： H01L29/76 , H01L21/285 , H01L29/417 , H01L29/49 , H01L29/51 , H01L29/66 , H01L21/768 , H01L29/78
CPC分类号： H01L21/28518 , H01L21/28008 , H01L21/76804 , H01L21/76814 , H01L29/41725 , H01L29/4958 , H01L29/4966 , H01L29/516 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7848 , H01L29/785
摘要： The present invention provides a MOS transistor, including a substrate, a gate oxide, a gate, a source/drain region and a silicide layer. The gate oxide is disposed on the substrate and the gate is disposed on the gate oxide. The source/drain region is disposed in the substrate at two sides of the gate. The silicide layer is disposed on the source/drain region, wherein the silicide layer includes a curved bottom surface. The present invention further provides a manufacturing method of the MOS transistor.
摘要翻译：本发明提供一种MOS晶体管，其包括衬底，栅极氧化物，栅极，源极/漏极区域和硅化物层。栅极氧化物设置在衬底上，并且栅极设置在栅极氧化物上。源极/漏极区域设置在栅极两侧的衬底中。硅化物层设置在源/漏区上，其中硅化物层包括弯曲的底表面。本发明还提供一种MOS晶体管的制造方法。

97. 发明授权

US08781614B2 Semiconductor processing dispatch control 有权
标题翻译：半导体处理调度控制
公开(公告)号：US08781614B2
公开(公告)日：2014-07-15
申请号：US13620115
申请日：2012-09-14
申请人： Sunny Wu , Yen-Di Tsen , Chun-Hsien Lin , Keung Hui , Jo Fei Wang , Jong-I Mou
发明人： Sunny Wu , Yen-Di Tsen , Chun-Hsien Lin , Keung Hui , Jo Fei Wang , Jong-I Mou
IPC分类号： G06F19/00
CPC分类号： G05B19/4187 , G05B19/042 , G05B19/41865 , G05B2219/2602 , G05B2219/32237 , G05B2219/32423 , G05B2219/45031 , G05B2219/50065 , Y02P90/20
摘要： An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, and dispatching the wafer to one of a first plurality of tools in a tuning process stage. The one of the first plurality of tools is determined based on the trend.
摘要翻译：实施例是用于半导体处理控制的方法。该方法包括基于处理的晶片的参数从多个处理阶段识别关键处理阶段，基于该参数来预测由密钥处理阶段处理的晶片的趋势以及多个处理阶段中的一些，以及调度晶片转换为调谐处理阶段中的第一多个工具之一。根据趋势确定第一组多个工具中的一个。

98. 发明授权

US08704294B2 Semiconductor device having metal gate and manufacturing method thereof 有权
标题翻译：具有金属栅极的半导体器件及其制造方法
公开(公告)号：US08704294B2
公开(公告)日：2014-04-22
申请号：US13158479
申请日：2011-06-13
申请人： Po-Jui Liao , Tsung-Lung Tsai , Chien-Ting Lin , Shao-Hua Hsu , Yeng-Peng Wang , Chun-Hsien Lin , Chan-Lon Yang , Guang-Yaw Hwang , Shin-Chi Chen , Hung-Ling Shih , Jiunn-Hsiung Liao , Chia-Wen Liang
发明人： Po-Jui Liao , Tsung-Lung Tsai , Chien-Ting Lin , Shao-Hua Hsu , Yeng-Peng Wang , Chun-Hsien Lin , Chan-Lon Yang , Guang-Yaw Hwang , Shin-Chi Chen , Hung-Ling Shih , Jiunn-Hsiung Liao , Chia-Wen Liang
IPC分类号： H01L29/66
CPC分类号： H01L29/78 , H01L21/823842 , H01L21/82385 , H01L29/66545
摘要： A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.
摘要翻译：一种制造具有金属栅极的半导体器件的方法包括：提供具有形成在其上的第一晶体管和第二晶体管的衬底，所述第一晶体管具有形成在其中的第一栅极沟槽，在所述第一栅极沟槽中形成第一功函数金属层，在第一栅极沟槽中的牺牲掩模层，去除牺牲掩模层的一部分以暴露第一功函数金属层的一部分，去除暴露的第一功能金属层，以在第一栅极沟槽中的第一栅极沟槽中形成U形功函数金属层栅极沟槽，以及去除牺牲掩模层。第一晶体管包括第一导电类型，第二晶体管包括第二导电类型。第一导电类型和第二导电类型是互补的。

99. 发明申请

US20130307152A1 SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US20130307152A1
公开(公告)日：2013-11-21
申请号：US13588103
申请日：2012-08-17
申请人： Wei Chung Hsiao , Chun Hsien Lin , Yu Cheng Pai , Liang Yi Hung , Ming Chen Sun , Shao Tzu Tang , Ying Chou Tsai , Chang Yi Lan
发明人： Wei Chung Hsiao , Chun Hsien Lin , Yu Cheng Pai , Liang Yi Hung , Ming Chen Sun , Shao Tzu Tang , Ying Chou Tsai , Chang Yi Lan
IPC分类号： H01L23/48 , H01L21/56
CPC分类号： H01L24/97 , H01L21/4846 , H01L21/561 , H01L21/568 , H01L23/3128 , H01L23/49816 , H01L23/49861 , H01L24/05 , H01L2224/04042 , H01L2224/04105 , H01L2224/05083 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A fabrication method of a semiconductor package is provided, which includes the steps of: forming a packaging substrate on a first carrier; bonding a second carrier to the packaging substrate; removing the first carrier; disposing a chip on the packaging substrate; forming an encapsulant on the packaging substrate for encapsulating the chip; and removing the second carrier. The first and second carriers provide the thin-type packaging substrate with sufficient rigidity for undergoing the fabrication processes without cracking or warpage, thereby meeting the miniaturization requirement and improving the product yield.
摘要翻译：提供一种半导体封装的制造方法，其包括以下步骤：在第一载体上形成封装衬底; 将第二载体粘合到所述包装基材上; 移除第一载体; 在包装基板上放置芯片; 在封装衬底上形成密封剂以封装芯片; 并移除第二载体。第一和第二载体为薄型包装基材提供足够的刚性以进行制造工艺而不会出现开裂或翘曲，从而满足小型化需求并提高产品产量。

100. 发明授权

US08562163B2 Power transmission circuit with EMI shielding, lighting module, and panel display module 有权
标题翻译：电力传输电路采用EMI屏蔽，照明模块和面板显示模块
公开(公告)号：US08562163B2
公开(公告)日：2013-10-22
申请号：US13029177
申请日：2011-02-17
申请人： Chun-Hsien Lin , Tsung-Hung Lee , Chih-Liang Pan
发明人： Chun-Hsien Lin , Tsung-Hung Lee , Chih-Liang Pan
IPC分类号： G09F13/04
CPC分类号： H05K9/0026 , G02F2001/133612
摘要： A power transmission circuit, a light source module including the power transmission circuit, and a panel display device are provided. The power transmission circuit includes a substrate, a power transmission layer, a metal shielding layer, a first protective layer, and a second protective layer. The substrate has a first surface and a second surface with the power transmission layer and the metal shielding layer respectively formed thereon. The metal shielding layer covers a projection region of a transmission section of the power transmission layer. The first and second protective layers are respectively disposed on the power transmission layer and the metal shielding layer and opposite to the substrate to protect the power transmission layer and the metal shielding layer.
摘要翻译：提供电力传输电路，包括电力传输电路的光源模块和面板显示装置。电力传输电路包括基板，电力传输层，金属屏蔽层，第一保护层和第二保护层。基板具有第一表面和第二表面，其上分别形成有电力传输层和金属屏蔽层。金属屏蔽层覆盖电力传输层的发送部的投影区域。第一和第二保护层分别设置在电力传输层和金属屏蔽层上并与基板相对，以保护电力传输层和金属屏蔽层。

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