专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

KR100789626B1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 无效
标题翻译：制造半导体器件的方法
公开(公告)号：KR100789626B1
公开(公告)日：2007-12-27
申请号：KR20060135755
申请日：2006-12-27
申请人： DONGBU ELECTRONICS CO LTD
发明人： HONG JI HO
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L25/0655 , G11C16/10 , H01L25/50 , H01L27/11526 , H01L27/11546 , H01L2224/24227
摘要： A method for manufacturing a semiconductor device is provided to reduce a manufacturing cost by packaging a cell region and a peripheral region on different wafers. A first manufacturing process is performed to manufacture a cell region on a first wafer as a chip(S101). A second manufacturing process is performed to manufacture a low-voltage region on a second wafer as a chip(S103). A third manufacturing process is performed to manufacture a high-voltage region on a third wafer as a chip(S105). A sawing process is performed to cut each of the chips formed on the first to third wafers(S107). A first to third packaging regions as chip packaging spaces are formed on a fourth wafer(S109). The chips formed on the first to third wafers are packaged on the first to third packaging regions(S111).
摘要翻译：提供了一种用于制造半导体器件的方法，以通过将单元区域和外围区域封装在不同的晶片上来降低制造成本。执行第一制造工艺以制造作为芯片的第一晶片上的单元区域（S101）。执行第二制造工艺以制造作为芯片的第二晶片上的低电压区域（S103）。执行第三制造工艺以制造作为芯片的第三晶片上的高电压区域（S105）。执行锯切处理以切割形成在第一至第三晶片上的每个芯片（S107）。在第四晶片上形成作为芯片封装空间的第一至第三封装区域（S109）。形成在第一至第三晶片上的芯片被封装在第一至第三封装区域上（S111）。

2. 发明授权

KR100783280B1 A FABRICATION METHOD FOR A PHOTO MASK 无效
标题翻译：一种照相胶片的制造方法
公开(公告)号：KR100783280B1
公开(公告)日：2007-12-06
申请号：KR20060068700
申请日：2006-07-21
申请人： DONGBU ELECTRONICS CO LTD
发明人： DO MUN HOE
IPC分类号： H01L21/027
CPC分类号： G03F1/36 , G03F1/144 , G03F7/705
摘要： A method for manufacturing photomasks is provided to reduce OPC executing time by enhancing process speed when OPC(Optical Proximity Correction) of design patterns is executed. Database of design patterns is inputted(S100). Dummy patterns around the design patterns are formed(S110). A predetermined distance from the design pattern is set as an OPC recognition area and then the dummy patterns are separated into the inner portion of the OPC recognition area and the outer portion(S120). OPC amounts of the design patterns are determined by simulating the dummy and design patterns in the OPC recognition area(S130,S140). Then, mask patterns applied the OPC amounts are formed(S150).
摘要翻译：提供一种制造光掩模的方法，用于通过在执行设计模式的OPC（光学邻近校正）时提高处理速度来减少OPC执行时间。输入设计图案的数据库（S100）。形成围绕设计图案的虚拟图案（S110）。将设计图案的预定距离设置为OPC识别区域，然后将虚设图案分离成OPC识别区域和外部部分的内部（S120）。通过模拟OPC识别区域中的虚拟和设计模式来确定OPC量的设计模式（S130，S140）。然后，形成施加OPC量的掩模图案（S150）。

3. 发明授权

KR100781888B1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 无效
标题翻译：制造半导体器件的方法
公开(公告)号：KR100781888B1
公开(公告)日：2007-12-05
申请号：KR20060135701
申请日：2006-12-27
申请人： DONGBU ELECTRONICS CO LTD
发明人： KIM HEE DAE
IPC分类号： H01L21/336
摘要： A method for manufacturing a semiconductor device is provided to improve breakdown characteristic by using an epitaxial process for forming a semiconductor layer through a dielectric pattern as a mask. A dielectric pattern(102) for defining a gate region is formed on a semiconductor substrate(101). A semiconductor layer(104) is formed on the semiconductor substrate at both sides of the dielectric pattern. The dielectric pattern is selectively removed from a surface of a semiconductor substrate. A gate dielectric(105) is formed on the dielectric pattern remaining between semiconductor layers. A gate electrode(106) is formed on the dielectric pattern between the gate dielectrics. A source/drain impurity region is formed on the semiconductor layer at both sides of the gate electrode. An epitaxial process is performed on the semiconductor substrate by using the dielectric pattern as a mask to form the semiconductor layer.
摘要翻译：提供一种用于制造半导体器件的方法，以通过使用通过电介质图案形成半导体层作为掩模的外延工艺来改善击穿特性。用于限定栅极区的电介质图案（102）形成在半导体衬底（101）上。半导体层（104）在电介质图案的两侧形成在半导体衬底上。从半导体衬底的表面选择性地去除电介质图案。栅极电介质（105）形成在保留在半导体层之间的电介质图案上。栅极电极（106）形成在栅极电介质之间的电介质图案上。在栅极两侧的半导体层上形成源/漏杂质区。通过使用电介质图案作为掩模在半导体衬底上进行外延工艺以形成半导体层。

4. 发明授权

KR100781894B1 METHOD FOR EXPOSURE OF SEMICONDUCTOR DEVICE 无效
标题翻译：半导体器件接触方法
公开(公告)号：KR100781894B1
公开(公告)日：2007-12-03
申请号：KR20060132686
申请日：2006-12-22
申请人： DONGBU ELECTRONICS CO LTD
发明人： BAIK JEONG HEON
IPC分类号： H01L21/027
CPC分类号： G03F9/7003 , G03F9/7046 , G03F9/7088
摘要： A method for exposing a semiconductor device is provided to maximize productivity by performing TIS(Tool Induced Shift) correction in an exposure process. A wafer is loaded in a wafer stage(100). Whether TIS correction is executed is determined(110). When the TIS correction is executed, the wafer is rotated as much as a predetermined angle(120). A first alignment is then executed(130-150). The wafer is recovered from the rotated angle(160). A second alignment is then executed(170-190) and an alignment correction is executed(200). An exposure process is then executed(210). The first and second alignments sequentially execute pre-alignment, search alignment, and fine alignment.
摘要翻译：提供一种用于暴露半导体器件的方法，以通过在曝光过程中执行TIS（工具诱导偏移）校正来最大化生产率。将晶片装载在晶片台（100）中。确定是否执行TIS校正（110）。当执行TIS校正时，晶片旋转预定角度（120）。然后执行第一对准（130-150）。从旋转角度（160）恢复晶片。然后执行第二对准（170-190）并执行对准校正（200）。然后执行曝光处理（210）。第一和第二对准顺序地执行预对准，搜索对齐和精细对准。

5. 发明授权

KR100780248B1 DIODE AND METHOD FOR MANUFACTURING THEREOF 无效
标题翻译：二极管及其制造方法
公开(公告)号：KR100780248B1
公开(公告)日：2007-11-27
申请号：KR20060135756
申请日：2006-12-27
申请人： DONGBU ELECTRONICS CO LTD
发明人： LIM SU
IPC分类号： H01L29/93 , H01L21/265 , H01L21/28 , H01L21/76
CPC分类号： H01L29/93
摘要： A diode and a method for manufacturing the same are provided to form a semiconductor device having high capacitance by increasing the capacitance on the same area. A plurality of first conductive type wells(120,160,200) are formed vertically to a substrate(110). A plurality of second conductive type ion implantation regions(130,170,220) are formed on each of the first conductive type wells. One or more second conductive type plugs(150,210) are formed to connect electrically the second conductive type ion implantation regions with each other. An isolation layer(190) is formed at both sides of the highest ion implantation region of the second conductive type ion implantation regions. A first conductive type source/drain region(230) is formed on the highest well of the first conductive type wells which are separated from the highest ion implantation region of the second conductive type ion implantation regions by using an isolation layer.
摘要翻译：提供二极管及其制造方法以通过增加同一区域上的电容来形成具有高电容的半导体器件。多个第一导电类型孔（120,160,200）垂直于衬底（110）形成。在每个第一导电类型的孔上形成多个第二导电型离子注入区（130,170,220）。形成一个或多个第二导电型插头（150,210），以将第二导电型离子注入区域彼此电连接。隔离层（190）形成在第二导电型离子注入区域的最高离子注入区域的两侧。第一导电型源极/漏极区域（230）通过使用隔离层与第二导电型离子注入区域的最高离子注入区域分开形成在第一导电类型阱的最高阱上。

6. 发明授权

KR100779399B1 METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE 无效
标题翻译：制造半导体器件的方法
公开(公告)号：KR100779399B1
公开(公告)日：2007-11-23
申请号：KR20060134063
申请日：2006-12-26
申请人： DONGBU ELECTRONICS CO LTD
发明人： LEE SANG SEOP
IPC分类号： H01L21/336
摘要： A method for manufacturing a semiconductor device is provided to improve a yield of the semiconductor device by reducing a block etch ratio of a gate region in a post-process. A first gate oxide layer(103) is formed on a silicon substrate(101) including a high voltage region and a low voltage region. An etch process is performed to remove the first gate oxide layer except for the low voltage region. A second gate oxide layer(104) thicker than the first oxide layer is formed on the front surface of the silicon substrate. A selective etch process is performed to remove the second gate oxide layer except for the high voltage region. A cleaning process is performed to remove foreign materials from the first and second gate oxide layers. A megasonic cleaning process is performed to remove water marks from the first and second gate oxide layers.
摘要翻译：提供一种用于制造半导体器件的方法，以通过降低后处理中的栅极区域的块蚀刻比来提高半导体器件的产量。在包括高电压区域和低电压区域的硅衬底（101）上形成第一栅极氧化物层（103）。执行蚀刻处理以除去除了低电压区域之外的第一栅极氧化物层。在硅衬底的前表面上形成比第一氧化物层厚的第二栅氧化层（104）。执行选择性蚀刻处理以去除除了高电压区域之外的第二栅极氧化物层。执行清洁处理以从第一和第二栅极氧化物层去除异物。执行兆声波清洗处理以从第一和第二栅极氧化物层去除水痕。

7. 发明授权

KR100776168B1 MASK USED FOR MANUFACTURING CMOS IMAGE SENSOR 无效
标题翻译：用于制造CMOS图像传感器的掩模
公开(公告)号：KR100776168B1
公开(公告)日：2007-11-12
申请号：KR20060073476
申请日：2006-08-03
申请人： DONGBU ELECTRONICS CO LTD
发明人： SHIM YEON AH
IPC分类号： H01L27/146 , H01L21/027
CPC分类号： G03F1/26 , G03F1/38
摘要： A mask for manufacturing a CMOS(Complementary Metal Oxide Semiconductor) image sensor is provided to suppress a corner rounding phenomenon on a microlens by applying a phase difference of 180 degrees between phase shifts units, which are formed on a mask. A mask for manufacturing a CMOS image sensor includes first and second phase shift units(101,102). The first and second phase shift units have different phases. An edge region of the mask is protruded in a triangular shape, so that the protruded regions are mated with each other. The first and second phase shift units are adjoined with each other on the edge region. Light is interfered by the first and second phase shift units. The first phase shift unit is a 0 degree-phase shift, while the second phase shift unit is a 180 degree-phase shift unit.
摘要翻译：提供了用于制造CMOS（互补金属氧化物半导体）图像传感器的掩模，以通过在形成在掩模上的相移单元之间施加180度的相位差来抑制微透镜上的拐角舍入现象。用于制造CMOS图像传感器的掩模包括第一和第二相移单元（101,102）。第一和第二相移单元具有不同的相位。掩模的边缘区域以三角形突出，使得突出区域彼此配合。第一和第二相移单元在边缘区域上彼此相邻。光被第一和第二相移单元干扰。第一相移单元是0度相移，而第二相移单元是180度相移单元。

8. 发明授权

KR100774830B1 PATTERNING METHOD OF NONSALICIDATION REGION FOR SEMICONDUCTOR MANUFACTURING 无效
标题翻译：半导体制造非非晶化区的方法
公开(公告)号：KR100774830B1
公开(公告)日：2007-11-07
申请号：KR20060066503
申请日：2006-07-14
申请人： DONGBU ELECTRONICS CO LTD
发明人： KIM TAE WOO
IPC分类号： H01L21/32 , H01L21/24
CPC分类号： H01L21/823418 , H01L21/823443
摘要： A method of forming a non-salicide region for a semiconductor device is provided to improve an operation reliability of the semiconductor device by preventing an under-cut phenomenon during a wet etching process. A silicon oxide film is deposited on a semiconductor substrate(10) by using PECVD(Plasma Enhanced Chemical Vapor Deposition) deposition scheme. A photolithography process is performed to pattern a non-salicide region. A plasma nitrogen gas reacts with the silicon oxide film in a dry etching apparatus and a photo-sensitive film is removed. A wet etching process is performed to remove a non-used silicon oxide film. A metal is deposited on the result structure before annealing the structure. A remaining metal is removed. The photolithography process is realized by performing a patterning using a negative photo-sensitive film.
摘要翻译：提供了一种形成用于半导体器件的非自对准硅化物区域的方法，以通过在湿法蚀刻工艺期间防止下切现象来改善半导体器件的操作可靠性。通过使用PECVD（等离子体增强化学气相沉积）沉积方案将氧化硅膜沉积在半导体衬底（10）上。进行光刻工艺以对非自对准区域进行图案化。等离子体氮气在干蚀刻装置中与氧化硅膜反应，除去感光膜。进行湿蚀刻处理以除去未使用的氧化硅膜。在退火结构之前，将金属沉积在结果结构上。剩下的金属被去除。通过使用负型感光膜进行图案化来实现光刻工艺。

9. 发明授权

KR100772836B1 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE 无效
标题翻译：制造半导体器件的方法
公开(公告)号：KR100772836B1
公开(公告)日：2007-11-01
申请号：KR20060068303
申请日：2006-07-21
申请人： DONGBU ELECTRONICS CO LTD
发明人： PARK JIN HA
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/26586 , H01L21/26506 , H01L21/28035 , H01L21/823807 , H01L29/4925 , H01L29/7845
摘要： A method for manufacturing a semiconductor device is provided to increase mobility of electrons by applying a stress on a poly layer, rather than a barrier layer, which is directly contacted with a channel region of a semiconductor substrate. Poly layers(25a,25b) with a predetermined thickness are formed on a semiconductor substrate(21). The poly layer is etched to a predetermined depth by using a photoresist pattern(27) as a mask. Ions are implanted on the poly layers with a predetermined angle. The poly layer is etched again by using the photoresist potential as the mask, such that the semiconductor substrate is exposed. The etch depth is 60~80 % of the thickness of the poly layer.
摘要翻译：提供一种制造半导体器件的方法，通过在多层而不是与半导体衬底的沟道区直接接触的阻挡层施加应力来增加电子的迁移率。在半导体衬底（21）上形成具有预定厚度的多层（25a，25b）。通过使用光致抗蚀剂图案（27）作为掩模将多层蚀刻到预定深度。离子以预定角度植入多层。通过使用光致抗蚀剂电位作为掩模再次蚀刻多晶硅层，使得半导体基板被暴露。蚀刻深度为多层厚度的60〜80％。

10. 发明授权

KR100772270B1 RAPID THERMAL PROCESSING APPARATUS AND METHOD FOR PREVENTING WARP OF WAFER 无效
标题翻译：快速热处理装置和防止波浪的方法
公开(公告)号：KR100772270B1
公开(公告)日：2007-11-01
申请号：KR20060072818
申请日：2006-08-02
申请人： DONGBU ELECTRONICS CO LTD
发明人： BAN SANG HYUN
IPC分类号： H01L21/324
CPC分类号： H01L21/67115 , H01L21/324 , H01L21/687
摘要： A method and an apparatus for performing a rapid thermal process on a wafer are provided to prevent the wafer from being bent by minimizing a temperature difference between a wafer edge and a wafer center. A rapid thermal process is performed on a wafer in a process chamber(300). A lift pin driver(312) raises the wafer to a heater, preheats a wafer center by using the heater, and mounts the wafer on a wafer chuck. The heaters(302a,302b) radiate stronger heat on the wafer center, before the wafer is mounted on the wafer chuck. A controller(316) drives the lift pin driver and preheats the wafer center for a predetermined period of time.
摘要翻译：提供一种用于在晶片上进行快速热处理的方法和装置，以通过最小化晶片边缘和晶片中心之间的温度差来防止晶片弯曲。在处理室（300）中的晶片上进行快速热处理。提升销驱动器（312）将晶片升高到加热器，通过使用加热器预热晶片中心，并将晶片安装在晶片卡盘上。在将晶片安装在晶片卡盘上之前，加热器（302a，302b）在晶片中心上辐射更强的热量。控制器（316）驱动升降销驱动器并预热晶片中心一段预定的时间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式