专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090193159A1 BUS ENCODING/DECODING METHOD AND BUS ENCODER/DECODER 失效
标题翻译：总线编码/解码方法和总线编码器/解码器
公开(公告)号：US20090193159A1
公开(公告)日：2009-07-30
申请号：US12360914
申请日：2009-01-28
申请人： Yu Li , Haibo Lin , Wen Bo Shen , Kai Zheng
发明人： Yu Li , Haibo Lin , Wen Bo Shen , Kai Zheng
IPC分类号： G06F13/32
CPC分类号： H04L25/4906 , G06F1/3253 , G06F9/3802 , Y02D10/151
摘要： An encoding method and an encoder for encoding data transmitted in a manner of bursts via a parallel bus and a decoding method and a decoder. The encoding method includes organizing data of the bursts into matrixes, determining for each of the matrixes whether a transform mode capable of decreasing the bus transition number exists, determining that the matrix needs to be transformed, determining a transform mode for transforming the matrix, and replacing the initial matrix with the transformed matrix. Then, forming a new matrix to be transmitted from matrixes which do not need to be transformed and matrixes which have been transformed. Thereafter, first generating a transform information word indicating transform states of the respective matrixes and then attaching the transform information word to the matrix to be transmitted to form an encoded matrix for actual transmission.
摘要翻译：一种编码方法和编码器，用于经由并行总线和解码方法以及解码器对以脉冲串的方式发送的数据进行编码。该编码方法包括将脉冲串的数据组织成矩阵，确定每个矩阵是否存在能够减小总线转换数的变换模式，确定矩阵需要变换，确定用于转换矩阵的变换模式，以及用转换的矩阵代替初始矩阵。然后，形成要从不需要变换的矩阵发送的新矩阵和已经被变换的矩阵。此后，首先产生指示各个矩阵的变换状态的变换信息字，然后将变换信息字附加到要发送的矩阵，以形成用于实际发送的编码矩阵。

2. 发明授权

US08085172B2 Bus encoding/decoding method and bus encoder/decoder 失效
标题翻译：总线编码/解码方式和总线编码器/解码器
公开(公告)号：US08085172B2
公开(公告)日：2011-12-27
申请号：US12360914
申请日：2009-01-28
申请人： Yu Li , Haibo Lin , Wen Bo Shen , Kai Zheng
发明人： Yu Li , Haibo Lin , Wen Bo Shen , Kai Zheng
IPC分类号： H03M5/00
CPC分类号： H04L25/4906 , G06F1/3253 , G06F9/3802 , Y02D10/151
摘要： An encoding method and an encoder for encoding data transmitted in a manner of bursts via a parallel bus and a decoding method and a decoder. The encoding method includes organizing data of the bursts into matrixes, determining for each of the matrixes whether a transform mode capable of decreasing the bus transition number exists, determining that the matrix needs to be transformed, determining a transform mode for transforming the matrix, and replacing the initial matrix with the transformed matrix. Then, forming a new matrix to be transmitted from matrixes which do not need to be transformed and matrixes which have been transformed. Thereafter, first generating a transform information word indicating transform states of the respective matrixes and then attaching the transform information word to the matrix to be transmitted to form an encoded matrix for actual transmission.
摘要翻译：一种编码方法和编码器，用于经由并行总线和解码方法以及解码器对以脉冲串的方式发送的数据进行编码。该编码方法包括将脉冲串的数据组织成矩阵，确定每个矩阵是否存在能够减小总线转换数的变换模式，确定矩阵需要变换，确定用于转换矩阵的变换模式，以及用转换的矩阵代替初始矩阵。然后，形成要从不需要变换的矩阵发送的新矩阵和已经被变换的矩阵。此后，首先产生指示各个矩阵的变换状态的变换信息字，然后将变换信息字附加到要发送的矩阵，以形成用于实际发送的编码矩阵。

3. 发明授权

US09286259B2 Method and apparatus for lowering I/O power of a computer system and computer system 有权
标题翻译：用于降低计算机系统和计算机系统的I / O功率的方法和装置
公开(公告)号：US09286259B2
公开(公告)日：2016-03-15
申请号：US12738908
申请日：2008-10-10
申请人： Yu Li , Wen Bo Shen , Yan Qi Wang , Yudong Yang
发明人： Yu Li , Wen Bo Shen , Yan Qi Wang , Yudong Yang
IPC分类号： G06F13/00 , G06F13/42 , G06F13/14
CPC分类号： G06F13/4286 , G06F13/14 , G06F13/42 , Y02D10/14 , Y02D10/151
摘要： The present invention provides a method and an apparatus for lowering I/O power of a computer system and a computer system. According to an aspect of the present invention, there is provided a method for lowering I/O power of a computer system, comprising: buffering a plurality of ways of data to be sent to a bus; encoding each of the plurality of ways of data buffered from n bits to n+m bits based on an encoding rule, wherein n and m are both an integer larger than or equal to 1, the encoding rule is used to lower code switching frequency; and sending the plurality of ways of data encoded to the bus.
摘要翻译：本发明提供一种用于降低计算机系统和计算机系统的I / O功率的方法和装置。根据本发明的一个方面，提供了一种用于降低计算机系统的I / O功率的方法，包括：缓冲要发送到总线的数据的多种方式; 基于编码规则对从n位缓冲到n + m位的多个数据路径中的每一个编码，其中n和m都是大于或等于1的整数，编码规则用于降低编码切换频率; 以及将多个编码的数据的方式发送到总线。

4. 发明申请

US20100211707A1 METHOD AND APPARATUS FOR LOWERING I/O POWER OF A COMPUTER SYSTEM AND COMPUTER SYSTEM 有权
标题翻译：降低计算机系统和计算机系统的I / O能力的方法和装置
公开(公告)号：US20100211707A1
公开(公告)日：2010-08-19
申请号：US12738908
申请日：2008-10-10
申请人： Yu Li , Wen Bo Shen , Yan Qi Wang , Yudong Yang
发明人： Yu Li , Wen Bo Shen , Yan Qi Wang , Yudong Yang
IPC分类号： G06F13/14 , G06F1/32 , G06F13/42 , G06F3/00
CPC分类号： G06F13/4286 , G06F13/14 , G06F13/42 , Y02D10/14 , Y02D10/151
摘要： The present invention provides a method and an apparatus for lowering I/O power of a computer system and a computer system. According to an aspect of the present invention, there is provided a method for lowering I/O power of a computer system, comprising: buffering a plurality of ways of data to be sent to a bus; encoding each of the plurality of ways of data buffered from n bits to n+m bits based on an encoding rule, wherein n and m are both an integer larger than or equal to 1, the encoding rule is used to lower code switching frequency; and sending the plurality of ways of data encoded to the bus.
摘要翻译：本发明提供一种用于降低计算机系统和计算机系统的I / O功率的方法和装置。根据本发明的一个方面，提供了一种用于降低计算机系统的I / O功率的方法，包括：缓冲要发送到总线的数据的多种方式; 基于编码规则对从n位缓冲到n + m位的多个数据路径中的每一个编码，其中n和m都是大于或等于1的整数，编码规则用于降低编码切换频率; 以及将多个编码的数据的方式发送到总线。

5. 发明申请

US20080205439A1 METHOD AND DEVICE FOR COMPENSATING FOR DELAYS OF A PLURALITY OF COMMUNICATION CHANNELS 审中-公开
标题翻译：用于补偿通信信道多路延迟的方法和设备
公开(公告)号：US20080205439A1
公开(公告)日：2008-08-28
申请号：US11871825
申请日：2007-10-12
申请人： Yu Li , Guo Hui Lin , Wen Bo Shen , Yu Dong Yang
发明人： Yu Li , Guo Hui Lin , Wen Bo Shen , Yu Dong Yang
IPC分类号： H04J3/16
CPC分类号： H04L25/03878 , H04L25/0272
摘要： A device and method for compensating for delays of a plurality of communication channels, provides signals with a certain frequency range, wherein the signals form standing waves in the plurality of communication channels; calculates phase differences between the plurality of communication channels according to the signal frequencies at the peak values of the standing waves; and determines the delay of each communication channel according to the above phase differences. The device and method may be applied to the communication channels of high speed parallel connection to eliminate the delays of the communication channels and realize length matching. Since the device and method determine the delays of communication channels by means of the phase differences, even when the delay difference exceeds a clock cycle, it can calculate the phase differences properly.
摘要翻译：用于补偿多个通信信道的延迟的装置和方法提供具有一定频率范围的信号，其中信号在多个通信信道中形成驻波; 根据在驻波的峰值处的信号频率，计算多个通信信道之间的相位差; 并根据上述相位差确定每个通信信道的延迟。该装置和方法可以应用于高速并行通信通道，以消除通信信道的延迟并实现长度匹配。由于设备和方法通过相位差确定通信信道的延迟，所以即使延迟差超过时钟周期，也可以正确计算相位差。

6. 发明授权

US09563259B2 Apparatus and method for activating and shutting down individual enhanced pipeline stages based on stage priority and performance requirements 有权
标题翻译：基于阶段优先级和性能要求激活和关闭各个增强流水线阶段的装置和方法
公开(公告)号：US09563259B2
公开(公告)日：2017-02-07
申请号：US12357910
申请日：2009-01-22
申请人： Wen Bo Shen , Peng Shao , Yu Li , Xiao Tao Chang , Yi Ge , Huayong Wang , Huan Hao Zou
发明人： Wen Bo Shen , Peng Shao , Yu Li , Xiao Tao Chang , Yi Ge , Huayong Wang , Huan Hao Zou
IPC分类号： G06F1/32 , G06F9/30 , G06F11/30 , G06F9/38 , G06F9/48
CPC分类号： G06F1/3287 , G06F9/3867 , G06F9/3885 , G06F9/4818 , G06F11/30 , G06F13/18 , Y02D10/14
摘要： The present invention discloses a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, the base pipeline stages being activated all the while, and the enhanced pipeline stages being activated or shutdown according to requirements for performance of a workload. The present invention further discloses a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, each pipeline stage being partitioned into a base module and at least one enhanced module, the base module being activated all the while, and the enhanced module being activated or shutdown according to requirements for performance of a workload.
摘要翻译：本发明公开了一种基于流水线的中央处理单元，其特征在于，根据功能，将流水线划分为基本流水线阶段和增强流水线阶段，基础流水线段同时被激活，而增强流水线阶段根据对工作负载的性能要求。本发明还公开了一种基于流水线的中央处理单元，其中根据功能将流水线划分为基本流水线阶段和增强流水线阶段，每个流水线分段分为基本模块和至少一个增强模块，基模块为激活所有时间，增强模块根据工作负载的性能要求被激活或关闭。

7. 发明申请

US20090193424A1 METHOD OF PROCESSING INSTRUCTIONS IN PIPELINE-BASED PROCESSOR AND CORRESPONDING PROCESSOR 有权
标题翻译：基于管道处理器和相应处理器的处理指令的方法
公开(公告)号：US20090193424A1
公开(公告)日：2009-07-30
申请号：US12357910
申请日：2009-01-22
申请人： Wen Bo Shen , Peng Shao , Yu Li , Xiao Tao Chang , Yi Ge , Huayong Wang , Huan Hao Zou
发明人： Wen Bo Shen , Peng Shao , Yu Li , Xiao Tao Chang , Yi Ge , Huayong Wang , Huan Hao Zou
IPC分类号： G06F9/46
CPC分类号： G06F1/3287 , G06F9/3867 , G06F9/3885 , G06F9/4818 , G06F11/30 , G06F13/18 , Y02D10/14
摘要： The present invention discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, the base pipeline stages being activated all the while, and the enhanced pipeline stages being activated or shutdown according to requirements for performance of a workload. The present invention further discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, each pipeline stage being partitioned into a base module and at least one enhanced module, the base module being activated all the while, and the enhanced module being activated or shutdown according to requirements for performance of a workload.
摘要翻译：本发明公开了一种在基于流水线的中央处理单元中处理指令的方法，其中根据功能将流水线划分为基本流水线阶段和增强流水线阶段，基本流水线阶段同时被激活，增强的流水线阶段根据工作负载的性能要求被激活或关闭。本发明还公开了一种在基于流水线的中央处理单元中处理指令的方法，其中根据功能将流水线划分成基本流水线级和增强的流水线级，每个流水线级分为基模块和至少一增强型模块，基本模块一直被激活，并且增强模块根据工作负载的性能要求被激活或关闭。

8. 发明授权

US09348406B2 Apparatus and method for activating and shutting down enhanced modules within an activated pipeline stage based on performance requirements and module priority 有权
标题翻译：基于性能要求和模块优先级激活和关闭激活的流水线级中的增强模块的装置和方法
公开(公告)号：US09348406B2
公开(公告)日：2016-05-24
申请号：US13457011
申请日：2012-04-26
申请人： Wen Bo Shen , Peng Shao , Yu Li , Xiao Tao Chang , Yi Ge , Hua Yong Wang , Huan Hao Zou
发明人： Wen Bo Shen , Peng Shao , Yu Li , Xiao Tao Chang , Yi Ge , Hua Yong Wang , Huan Hao Zou
IPC分类号： G06F1/32 , G06F9/30 , G06F11/30 , G06F9/38
CPC分类号： G06F1/3287 , G06F9/3867 , G06F9/3885 , G06F9/4818 , G06F11/30 , G06F13/18 , Y02D10/14
摘要： The present invention discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, the base pipeline stages being activated all the while, and the enhanced pipeline stages being activated or shutdown according to requirements for performance of a workload. The present invention further discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, each pipeline stage being partitioned into a base module and at least one enhanced module, the base module being activated all the while, and the enhanced module being activated or shutdown according to requirements for performance of a workload.
摘要翻译：本发明公开了一种在基于流水线的中央处理单元中处理指令的方法，其中根据功能将流水线划分为基本流水线阶段和增强流水线阶段，基本流水线阶段同时被激活，增强的流水线阶段根据工作负载的性能要求被激活或关闭。本发明还公开了一种在基于流水线的中央处理单元中处理指令的方法，其中根据功能将流水线划分成基本流水线级和增强的流水线级，每个流水线级分为基模块和至少一增强型模块，基本模块一直被激活，并且增强模块根据工作负载的性能要求被激活或关闭。

9. 发明申请

US20120210106A1 METHOD OF PROCESSING INSTRUCTIONS IN PIPELINE-BASED PROCESSOR 有权
标题翻译：基于管道处理器的处理指令的方法
公开(公告)号：US20120210106A1
公开(公告)日：2012-08-16
申请号：US13457011
申请日：2012-04-26
申请人： Wen Bo Shen , Peng Shao , Yu Li , Xiao Tao Chang , Yi Ge , Huayong Wang , Huan Hao Zou
发明人： Wen Bo Shen , Peng Shao , Yu Li , Xiao Tao Chang , Yi Ge , Huayong Wang , Huan Hao Zou
IPC分类号： G06F9/38
CPC分类号： G06F1/3287 , G06F9/3867 , G06F9/3885 , G06F9/4818 , G06F11/30 , G06F13/18 , Y02D10/14
摘要： The present invention discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, the base pipeline stages being activated all the while, and the enhanced pipeline stages being activated or shutdown according to requirements for performance of a workload. The present invention further discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, each pipeline stage being partitioned into a base module and at least one enhanced module, the base module being activated all the while, and the enhanced module being activated or shutdown according to requirements for performance of a workload.
摘要翻译：本发明公开了一种在基于流水线的中央处理单元中处理指令的方法，其中根据功能将流水线划分为基本流水线阶段和增强流水线阶段，基本流水线阶段同时被激活，增强的流水线阶段根据工作负载的性能要求被激活或关闭。本发明还公开了一种在基于流水线的中央处理单元中处理指令的方法，其中根据功能将流水线划分成基本流水线级和增强的流水线级，每个流水线级分为基模块和至少一增强型模块，基本模块一直被激活，并且增强模块根据工作负载的性能要求被激活或关闭。

10. 发明授权

US10788164B1 LED emitter and LED lamp having the same 有权
公开(公告)号：US10788164B1
公开(公告)日：2020-09-29
申请号：US16424475
申请日：2019-05-28
申请人： Wenbo Ma , Qiurong Liao , Yu Li , Kuo-Hsin Chang , Chung-Ping Lai
发明人： Wenbo Ma , Qiurong Liao , Yu Li , Kuo-Hsin Chang , Chung-Ping Lai
IPC分类号： F21K9/232 , F21K9/235 , H01L33/50 , H01L25/075 , F21K9/64
摘要： A light-emitting diode (LED) emitter and a LED lamp having the same are revealed. The LED emitter includes a first LED chip string, a second LED chip string, a substrate, two electrodes, a high-color-temperature phosphor layer and a low-color-temperature phosphor layer. The substrate where the first LED chip string and the second LED chip string are arranged is electrically connected to the two electrodes. The high-color-temperature phosphor layer and low-color-temperature phosphor layer cover the first LED chip string and the second LED chip string respectively. The total resistance value of the first LED chip string is different from the total resistance value of the second LED chip string.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式