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1. 发明申请

US20140200319A1 FLUORESCENT POTASSIUM ION SENSORS 有权
标题翻译：荧光钾离子传感器
公开(公告)号：US20140200319A1
公开(公告)日：2014-07-17
申请号：US13985260
申请日：2012-02-13
申请人： Yanqing Tian , Deirdre Meldrum , Xianfeng Zhou , Fengyu Su , Roger H. Johnson , Cody Youngbull
发明人： Yanqing Tian , Deirdre Meldrum , Xianfeng Zhou , Fengyu Su , Roger H. Johnson , Cody Youngbull
IPC分类号： C08F226/06 , C08F230/04 , C07D498/08
CPC分类号： C08F226/06 , C07D498/08 , C07D519/00 , C07F15/0093 , C08F230/04 , C08G2261/226 , C08G2261/3223 , G01N33/84
摘要： This disclosure relates generally to potassium ion sensors and monomers derived from such sensors. The disclosure also provides for polymers (e.g., random copolymers, nanoparticles, polymer thin films, and sensors) having polymerized monomeric potassium ion sensors as described herein. These compounds and polymers are useful for measuring intracellular and extracellular potassium ion concentrations.
摘要翻译：本公开一般涉及衍生自这种传感器的钾离子传感器和单体。本公开还提供了具有如本文所述的聚合的单体钾离子传感器的聚合物（例如，无规共聚物，纳米颗粒，聚合物薄膜和传感器）。这些化合物和聚合物可用于测量细胞内和细胞外钾离子浓度。

2. 发明授权

US09181375B2 Fluorescent potassium ion sensors 有权
标题翻译：荧光钾离子传感器
公开(公告)号：US09181375B2
公开(公告)日：2015-11-10
申请号：US13985260
申请日：2012-02-13
申请人： Yanqing Tian , Deirdre Meldrum , Xianfeng Zhou , Fengyu Su , Roger H. Johnson , Cody Youngbull
发明人： Yanqing Tian , Deirdre Meldrum , Xianfeng Zhou , Fengyu Su , Roger H. Johnson , Cody Youngbull
IPC分类号： C08F226/06 , C07D498/08 , C07D519/00 , G01N33/84 , C07F15/00 , C08F230/04
CPC分类号： C08F226/06 , C07D498/08 , C07D519/00 , C07F15/0093 , C08F230/04 , C08G2261/226 , C08G2261/3223 , G01N33/84
摘要： This disclosure relates generally to potassium ion sensors and monomers derived from such sensors. The disclosure also provides for polymers (e.g., random copolymers, nanoparticles, polymer thin films, and sensors) having polymerized monomeric potassium ion sensors as described herein. These compounds and polymers are useful for measuring intracellular and extracellular potassium ion concentrations.
摘要翻译：本公开一般涉及衍生自这种传感器的钾离子传感器和单体。本公开还提供了具有如本文所述的聚合的单体钾离子传感器的聚合物（例如，无规共聚物，纳米颗粒，聚合物薄膜和传感器）。这些化合物和聚合物可用于测量细胞内和细胞外钾离子浓度。

3. 发明授权

US08585890B2 Tubular cracking furnace 有权
标题翻译：管式裂解炉
公开(公告)号：US08585890B2
公开(公告)日：2013-11-19
申请号：US12593216
申请日：2008-03-28
申请人： Guoqing Wang , Lijun Zhang , Zhiguo Du , Shuo Chen , Zhaobin Zhang , Cong Zhou , Xianfeng Zhou
发明人： Guoqing Wang , Lijun Zhang , Zhiguo Du , Shuo Chen , Zhaobin Zhang , Cong Zhou , Xianfeng Zhou
IPC分类号： C10G9/14 , B01J8/00
CPC分类号： F28F13/12 , C10G2400/20 , F28D2021/0059 , F28F1/40 , F28F19/00 , Y10T29/4935
摘要： This invention relates to a tubular cracking furnace, especially an ethylene cracking furnace, which comprises a convection section and a or dual radiant section(s), at least one heat transfer intensifying member arranged in at least one pass each radiant tube in said radiant section, said at least one heat transfer intensifying member comprises a first heat transfer intensifying member, which is arranged at a location between 10D and 25D upstream of the extreme point of said at least one pass radiant tube metal temperature, wherein D is the inner diameter of the radiant tube having heat transfer intensifying members. The present invention could achieve the best enhanced heat transfer result with given number of heat transfer intensifying member, by optimizing the locations of heat transfer intensifying members in the radiant tube.
摘要翻译：本发明涉及一种管状裂解炉，特别是一种乙烯裂解炉，其包括一个对流段和一个或两个辐射区，至少一个传热增强构件，其布置在至少一个通路中，每个辐射管中的每个辐射管所述至少一个传热增强构件包括第一传热增强构件，其布置在所述至少一个通过辐射管金属温度的极限点上游的10D和25D之间的位置，其中D是辐射管具有传热增强构件。通过优化辐射管中的传热增强构件的位置，本发明可以通过给定数量的传热增强构件实现最佳的增强的传热结果。

4. 发明申请

US20100295137A1 METHOD AND APPARATUS PROVIDING DIFFERENT GATE OXIDES FOR DIFFERENT TRANSITORS IN AN INTEGRATED CIRCUIT 有权
标题翻译：在集成电路中为不同传输器提供不同栅极氧化物的方法和装置
公开(公告)号：US20100295137A1
公开(公告)日：2010-11-25
申请号：US12851278
申请日：2010-08-05
申请人： Xianfeng Zhou
发明人： Xianfeng Zhou
IPC分类号： H01L27/088
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： An integrated circuit and gate oxide forming process are disclosed which provide a gate structure that is simple to integrate with conventional fabrication processes while providing different gate oxide thicknesses for different transistors within the integrated circuit. For a flash memory, which may utilize the invention, the different gate oxide thicknesses may be used for lower voltage transistors, memory array transistors, and higher voltage transistors.
摘要翻译：公开了集成电路和栅极氧化物形成工艺，其提供了与常规制造工艺集成的简单栅极结构，同时为集成电路内的不同晶体管提供不同的栅极氧化物厚度。对于可以利用本发明的闪速存储器，不同的栅极氧化物厚度可以用于较低电压晶体管，存储器阵列晶体管和较高电压晶体管。

5. 发明申请

US20100276781A1 Semiconductor Constructions 有权
标题翻译：半导体建筑
公开(公告)号：US20100276781A1
公开(公告)日：2010-11-04
申请号：US12837378
申请日：2010-07-15
申请人： Michael A. Smith , Sukesh Sandhu , Xianfeng Zhou , Graham Wolstenholme
发明人： Michael A. Smith , Sukesh Sandhu , Xianfeng Zhou , Graham Wolstenholme
IPC分类号： H01L29/06
CPC分类号： H01L29/7833 , H01L21/76205
摘要： The invention includes methods of forming oxide structures under corners of transistor gate stacks and adjacent trenched isolation regions. Such methods can include exposure of a semiconductor material to steam and H2, with the H2 being present to a concentration of from about 2% to about 40%, by volume. An oxide structure formed under the bottom corner of a transistor gate stack can have a bottom surface with a topography that includes a step of at least about 50 Å, and an upper surface directly over the bottom surface and having a topography that is substantially planar. Methodology of the present invention can be utilized to form semiconductor constructions suitable for incorporation into highly integrated circuitry. The highly integrated circuitry can be incorporated into electronic systems, and can, for example, be utilized in processors and/or memory storage devices.
摘要翻译：本发明包括在晶体管栅极堆叠和相邻沟槽隔离区域的角落处形成氧化物结构的方法。这样的方法可以包括将半导体材料暴露于蒸汽和H2，其中H2以体积计约2％至约40％的浓度存在。形成在晶体管栅极堆叠的底角下方的氧化物结构可以具有底表面，其具有包括至少约为50埃的步骤的形貌，以及直接在底表面上方的上表面，并且具有基本平坦的形貌。本发明的方法可以用于形成适合并入高度集成电路的半导体结构。高度集成的电路可以并入到电子系统中，并且可以例如在处理器和/或存储器存储设备中使用。

6. 发明申请

US20100148300A1 ISOLATION TRENCH FILL USING OXIDE LINER AND NITRIDE ETCH BACK TECHNIQUE WITH DUAL TRENCH DEPTH CAPABILITY 有权
标题翻译：使用氧化锌衬垫和氮化钛回填技术的隔离透气膜，具有双重深度深度能力
公开(公告)号：US20100148300A1
公开(公告)日：2010-06-17
申请号：US12712401
申请日：2010-02-25
申请人： Xianfeng Zhou
发明人： Xianfeng Zhou
IPC分类号： H01L29/06
CPC分类号： H01L29/0653 , H01L21/31051 , H01L21/31053 , H01L21/311 , H01L21/76224 , H01L21/76229 , H01L27/11548 , H01L29/0649
摘要： An oxide layer is formed over a substrate having a smaller isolation trench and a large isolation trench. A nitride layer is formed over the oxide layer such that it completely fills the smaller isolation trench and lines the larger isolation trench. The nitride layer is etched back to form a recess in the nitride layer in the smaller isolation trench while at least a portion of the nitride layer lining the larger isolation trench is completely removed. A layer of HDP oxide is deposited over the substrate, completely filling the smaller and larger isolation trenches. The HDP oxide layer is planarized to the upper surface of the substrate. The deeper larger isolation trench may be formed by performing an etching step after the nitride layer has been etched back, prior to depositing HDP oxide.
摘要翻译：在具有较小隔离沟槽和大隔离沟槽的衬底上形成氧化物层。在氧化物层上形成氮化物层，使得其完全填充较小的隔离沟槽并对较大的隔离沟槽进行排列。蚀刻氮化物层以在更小的隔离沟槽中的氮化物层中形成凹陷，同时完全去除衬在较大隔离沟槽的氮化物层的至少一部分。在衬底上沉积一层HDP氧化物，完全填充越来越小的隔离沟槽。 HDP氧化物层平坦化到衬底的上表面。在沉积HDP氧化物之前，可以通过在氮化物层被回蚀后进行蚀刻步骤来形成更深的较大的隔离沟槽。

7. 发明申请

US20090286366A1 FORMATION OF STANDARD VOLTAGE THRESHOLD AND LOW VOLTAGE THRESHOLD MOSFET DEVICES 失效
标题翻译：形成标准电压阈值和低电压阈值MOSFET器件
公开(公告)号：US20090286366A1
公开(公告)日：2009-11-19
申请号：US12512631
申请日：2009-07-30
申请人： Mark Helm , Xianfeng Zhou
发明人： Mark Helm , Xianfeng Zhou
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/823807 , H01L21/823892 , H01L29/6659 , H01L29/7833
摘要： Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within wells defining the second type standard Vt devices, and each of the first and second type low Vt devices. Wells that define the locations of second type standard Vt devices are masked, and a second voltage threshold implant adjustment is performed to the wells defining the first type standard Vt devices, and each of the first and second type low Vt devices. Doped polysilicon gate stacks are then formed over the wells. Performance characteristics and control of each device Vt is controlled by regulating at least one of the first and second voltage threshold implant adjustments, and the polysilicon gate stack doping.
摘要翻译：孔形成在要制造第一和第二类型的标准Vt和低Vt装置的基板中。限定第一类型标准Vt器件的位置的阱被掩蔽，并且在限定第二类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个上执行第一电压阈值注入调整。限定第二类型标准Vt器件的位置的阱被屏蔽，并且对定义第一类型标准Vt器件的阱以及第一和第二类型低Vt器件中的每一个执行第二电压阈值注入调整。然后在孔上形成掺杂的多晶硅栅极叠层。通过调节第一和第二电压阈值注入调整和多晶硅栅极堆叠掺杂中的至少一个来控制每个器件Vt的性能特征和控制。

8. 发明申请

US20120108051A1 DIFFERENT GATE OXIDES THICKNESSES FOR DIFFERENT TRANSISTORS IN AN INTEGRATED CIRCUIT 有权
标题翻译：不同栅极氧化层对集成电路中不同晶体管的厚度
公开(公告)号：US20120108051A1
公开(公告)日：2012-05-03
申请号：US13344329
申请日：2012-01-05
申请人： Xianfeng Zhou
发明人： Xianfeng Zhou
IPC分类号： H01L21/28
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： An integrated circuit and gate oxide forming process are disclosed which provide a gate structure that is simple to integrate with conventional fabrication processes while providing different gate oxide thicknesses for different transistors within the integrated circuit. For a flash memory, which may utilize the invention, the different gate oxide thicknesses may be used for lower voltage transistors, memory array transistors, and higher voltage transistors.
摘要翻译：公开了集成电路和栅极氧化物形成工艺，其提供了与常规制造工艺集成的简单栅极结构，同时为集成电路内的不同晶体管提供不同的栅极氧化物厚度。对于可以利用本发明的闪速存储器，不同的栅极氧化物厚度可以用于较低电压晶体管，存储器阵列晶体管和较高电压晶体管。

9. 发明授权

US08102006B2 Different gate oxides thicknesses for different transistors in an integrated circuit 有权
标题翻译：集成电路中不同晶体管的不同栅极氧化物厚度
公开(公告)号：US08102006B2
公开(公告)日：2012-01-24
申请号：US12851278
申请日：2010-08-05
申请人： Xianfeng Zhou
发明人： Xianfeng Zhou
IPC分类号： H01L21/70
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： An integrated circuit and gate oxide forming process are disclosed which provide a gate structure that is simple to integrate with conventional fabrication processes while providing different gate oxide thicknesses for different transistors within the integrated circuit. For a flash memory, which may utilize the invention, the different gate oxide thicknesses may be used for lower voltage transistors, memory array transistors, and higher voltage transistors.
摘要翻译：公开了集成电路和栅极氧化物形成工艺，其提供了与常规制造工艺集成的简单栅极结构，同时为集成电路内的不同晶体管提供不同的栅极氧化物厚度。对于可以利用本发明的闪速存储器，不同的栅极氧化物厚度可以用于较低电压晶体管，存储器阵列晶体管和较高电压晶体管。

10. 发明授权

US07790544B2 Method of fabricating different gate oxides for different transistors in an integrated circuit 有权
标题翻译：在集成电路中制造用于不同晶体管的不同栅极氧化物的方法
公开(公告)号：US07790544B2
公开(公告)日：2010-09-07
申请号：US11387707
申请日：2006-03-24
申请人： Xianfeng Zhou
发明人： Xianfeng Zhou
IPC分类号： H01L21/8238
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： An integrated circuit and gate oxide forming process are disclosed which provide a gate structure that is simple to integrate with conventional fabrication processes while providing different gate oxide thicknesses for different transistors within the integrated circuit. For a flash memory, which may utilize the invention, the different gate oxide thicknesses may be used for lower voltage transistors, memory array transistors, and higher voltage transistors.
摘要翻译：公开了集成电路和栅极氧化物形成工艺，其提供了与常规制造工艺集成的简单栅极结构，同时为集成电路内的不同晶体管提供不同的栅极氧化物厚度。对于可以利用本发明的闪速存储器，不同的栅极氧化物厚度可以用于较低电压晶体管，存储器阵列晶体管和较高电压晶体管。

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