专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06754746B1 Memory array with read/write methods 失效
标题翻译：具有读/写方式的内存数组
公开(公告)号：US06754746B1
公开(公告)日：2004-06-22
申请号：US09535656
申请日：2000-03-23
申请人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
发明人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
IPC分类号： G06F1300
CPC分类号： H04L25/026 , G06F13/40 , G06F13/4072 , G06F13/4077
摘要： Improved circuitry for connecting the memory array to a data bus allows for high speed accessing of the memory array. Sense amplifier latches are coupled to each column of memory cells. The latched sense amplifiers are coupled to decoders which, in turn, are coupled to data amplifiers. The data amplifiers are coupled to a data bus. Data being read from or written to the memory cells is via the sense amplifier latches, the decoders, and data amplifiers.
摘要翻译：用于将存储器阵列连接到数据总线的改进的电路允许存储器阵列的高速存取。读出放大器锁存器耦合到每列存储器单元。锁存的读出放大器耦合到解码器，解码器又耦合到数据放大器。数据放大器耦合到数据总线。通过读出放大器锁存器，解码器和数据放大器读取或写入存储器单元的数据。

2. 发明授权

US5729152A Termination circuits for reduced swing signal lines and methods for operating same 失效
标题翻译：用于减少摆动信号线的终端电路及其操作方法
公开(公告)号：US5729152A
公开(公告)日：1998-03-17
申请号：US549610
申请日：1995-10-27
申请人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
发明人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
IPC分类号： G11C11/41 , G06F3/00 , G06F12/16 , G06F13/16 , G06F13/40 , G11C7/00 , G11C11/401 , G11C11/407 , G11C11/417 , G11C29/00 , G11C29/04 , H04L25/02 , H03K17/16
CPC分类号： H04L25/028 , G06F13/40 , G06F13/4072 , G06F13/4077 , H04L25/026 , H04L25/0292 , Y02B60/1228 , Y02B60/1235
摘要： A memory device which utilizes a plurality of memory modules coupled in parallel to a master I/O module through a single directional asymmetrical signal swing (DASS) bus. This structure provides an I/O scheme having symmetrical swing around half the supply voltage, high through-put, high data bandwidth, short access time, low latency and high noise immunity. The memory device utilizes improved column access circuitry including an improved address sequencing circuit and a data amplifier within each memory module. The memory device includes a resynchronization circuit which allows the device to operate either synchronously and asynchronously using the same pins. Each memory module has independent address and command decoders to enable independent operation. Thus, each memory module is activated by commands on the DASS bus only when a memory access operation is performed within the particular memory module. The memory device includes redundant memory modules to replace defective memory modules. Replacement can be carried out through commands on the DASS bus. The memory device can be configured to simultaneously write a single input data stream to multiple memory modules or to perform high-speed interleaved read and write operations. In one embodiment, multiple memory devices are coupled to a common, high-speed I/O bus without requiring large bus drivers and complex bus receivers in the memory modules.
摘要翻译：一种存储器件，其利用通过单向非对称信号摆幅（DASS）总线并联到主I / O模块的多个存储器模块。这种结构提供了一个在电源电压的一半左右，高输入，高数据带宽，短访问时间，低延迟和高抗噪声的对称摆动的I / O方案。存储器件利用改进的列存取电路，包括改进的地址排序电路和每个存储器模块内的数据放大器。存储器件包括再同步电路，其允许器件使用相同的引脚同步和异步地操作。每个存储器模块具有独立的地址和命令解码器，以实现独立操作。因此，只有当在特定存储器模块内执行存储器访问操作时，每个存储器模块才被DASS总线上的命令激活。存储器件包括用于替换有缺陷的存储器模块的冗余存储器模块。可以通过DASS总线上的命令进行更换。存储器件可被配置为将单个输入数据流同时写入多个存储器模块或执行高速交错读写操作。在一个实施例中，多个存储器件耦合到公共的高速I / O总线，而不需要存储器模块中的大的总线驱动器和复杂的总线接收器。

3. 发明授权

US5498990A Reduced CMOS-swing clamping circuit for bus lines 失效
标题翻译：减少用于总线的CMOS摆幅钳位电路
公开(公告)号：US5498990A
公开(公告)日：1996-03-12
申请号：US417511
申请日：1995-04-05
申请人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
发明人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
IPC分类号： G06F5/16 , G06F11/00 , G06F11/10 , G06F11/20 , G06F12/06 , G06F13/40 , G11C29/00 , G11C29/48 , H01L21/66 , H01L27/02 , H04L25/02 , H03K5/08
CPC分类号： H04L25/026 , G06F12/0661 , G06F13/4077 , G06F5/16 , G11C29/006 , G11C29/48 , G11C29/76 , G11C29/808 , G11C29/832 , G11C29/88 , H01L22/22 , G06F11/006 , G06F11/10 , G06F11/1666 , H01L27/0203 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235
摘要： A memory system having several memory devices coupled to a memory controller through an I/O bus, each memory device including multiple memory modules coupled to a chip I/O interface through an internal bus. The system includes a circuit for driving the I/O bus with a reduced CMOS-swing, a circuit for driving the internal bus with a full CMOS-swing in one bus direction and with a reduced CMOS-swing in the other bus direction, a column address generation circuit for allowing sequentially addressed data to be accessed with the decoder delay being eliminated, and a circuit for re-synchronizing data from a source clock to a destination clock with reduced access latency penalty. Simultaneously writing data into multiple circuit modules significantly increases the write bandwidth of the memory. Also included are a dynamic base-address mapping into an address space, a read or write operation across multiple memory modules, a novel I/O bus format, and a protocol and test mode for testing redundant memory sub-arrays.
摘要翻译：具有通过I / O总线耦合到存储器控制器的几个存储器件的存储器系统，每个存储器件包括通过内部总线耦合到芯片I / O接口的多个存储器模块。该系统包括用于以减小的CMOS摆动驱动I / O总线的电路，用于在一个总线方向上以完全CMOS摆动驱动内部总线并且在另一个总线方向上以减小的CMOS摆幅驱动内部总线的电路列地址产生电路，用于允许在解码器延迟被消除的情况下访问顺序寻址的数据;以及电路，用于将来自源时钟的数据重新同步到具有降低的访问延迟代价的目的地时钟。同时将数据写入多个电路模块会显着增加存储器的写入带宽。还包括动态基地址映射到地址空间，跨多个存储器模块的读或写操作，新颖的I / O总线格式以及用于测试冗余存储器子阵列的协议和测试模式。

4. 发明授权

US06272577B1 Data processing system with master and slave devices and asymmetric signal swing bus 失效
标题翻译：数据处理系统具有主从设备和不对称信号摆幅总线
公开(公告)号：US06272577B1
公开(公告)日：2001-08-07
申请号：US08960951
申请日：1997-10-30
申请人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
发明人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
IPC分类号： G06F1300
CPC分类号： H04L25/028 , G06F13/40 , G06F13/4072 , G06F13/4077 , H04L25/026 , H04L25/0292 , Y02D10/14 , Y02D10/151
摘要： A memory device which utilizes a plurality of memory modules coupled in parallel to a master I/O module through a single directional asymmetrical signal swing (DASS) bus. This structure provides an I/O scheme having symmetrical swing around half the supply voltage, high through-put, high data bandwidth, short access time, low latency and high noise immunity. The device utilizes improved column access circuitry including an improved address sequencing circuit and a data amplifier within each memory module. A resynchronization circuit allows the device to operate either synchronously and asynchronously using the same pins. Each memory module has independent address and command decoders to enable independent operation so that each memory module is activated by commands on the DASS bus only when a memory access operation is performed within the particular memory module. Redundant memory modules are included to replace defective memory modules, and replacement can be carried out through commands on the DASS bus. The memory device can be configured to simultaneously write a single input data stream to multiple memory modules or to perform high-speed interleaved read and write operations. In one embodiment, multiple memory devices are coupled to a common, high-speed I/O bus without requiring large bus drivers and complex bus receivers in the memory modules.
摘要翻译：一种存储器件，其利用通过单向非对称信号摆幅（DASS）总线并联到主I / O模块的多个存储器模块。这种结构提供了一个在电源电压的一半左右，高输入，高数据带宽，短访问时间，低延迟和高抗噪声的对称摆动的I / O方案。该器件利用改进的列存取电路，包括改进的地址排序电路和每个存储器模块内的数据放大器。同步电路允许器件使用相同的引脚进行同步和异步操作。每个存储器模块具有独立的地址和命令解码器，以实现独立操作，使得仅当在特定存储器模块内执行存储器访问操作时，每个存储器模块才被DASS总线上的命令激活。包括冗余内存模块以替换有缺陷的内存模块，并可通过DASS总线上的命令进行更换。存储器件可被配置为将单个输入数据流同时写入多个存储器模块或执行高速交错读写操作。在一个实施例中，多个存储器件耦合到公共的高速I / O总线，而不需要存储器模块中的大的总线驱动器和复杂的总线接收器。

5. 发明授权

US5655113A Resynchronization circuit for a memory system and method of operating same 失效
标题翻译：用于存储器系统的再同步电路及其操作方法
公开(公告)号：US5655113A
公开(公告)日：1997-08-05
申请号：US270856
申请日：1994-07-05
申请人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
发明人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
IPC分类号： G11C11/41 , G06F3/00 , G06F12/16 , G06F13/16 , G06F13/40 , G11C7/00 , G11C11/401 , G11C11/407 , G11C11/417 , G11C29/00 , G11C29/04 , H04L25/02 , G06F13/00
CPC分类号： H04L25/028 , G06F13/40 , G06F13/4072 , G06F13/4077 , H04L25/026 , H04L25/0292 , Y02B60/1228 , Y02B60/1235
摘要： A resynchronization circuit for processing a stream of data values read from a memory system, and a method of operating the same. The resynchronization circuit includes a first in, first out (FIFO) memory device, a phase locked loop circuit and a latency control circuit. The FIFO memory device receives a stream of data values and a first clock signal from the memory system. The data values are sequentially read into the FIFO memory device in response to the first clock signal. The phase locked loop circuit receives a second clock signal, and in response generates an output clock signal which leads in phase the second clock signal. The output clock signal is provided to the FIFO memory device to cause the data values to be sequentially read from the FIFO memory device. As a result, a stream of data values is generated which is synchronized with the second clock signal. The latency control circuit, which is coupled to the FIFO memory device, enables the data values to be read from the FIFO memory device after a selectable delay period which follows the initiation of the read operation from the memory system.
摘要翻译：一种用于处理从存储器系统读取的数据流流的再同步电路及其操作方法。再同步电路包括先入先出（FIFO）存储器件，锁相环电路和等待时间控制电路。 FIFO存储器件从存储器系统接收数据流流和第一时钟信号。响应于第一时钟信号，将数据值依次读入FIFO存储器件。锁相环电路接收第二时钟信号，并且响应于产生一个使第二时钟信号同相引出的输出时钟信号。将输出时钟信号提供给FIFO存储器件，以使数据值从FIFO存储器件顺序读取。结果，产生与第二时钟信号同步的数据流流。耦合到FIFO存储器件的等待时间控制电路使得能够在从存储器系统开始读取操作之后的可选延迟周期之后从FIFO存储器件读取数据值。

6. 发明授权

US06393504B1 Dynamic address mapping and redundancy in a modular memory device 有权
标题翻译：模块化存储设备中的动态地址映射和冗余
公开(公告)号：US06393504B1
公开(公告)日：2002-05-21
申请号：US09493781
申请日：2000-01-28
申请人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
发明人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
IPC分类号： G06F1300
CPC分类号： H04L25/028 , G06F13/40 , G06F13/4072 , G06F13/4077 , H04L25/026 , H04L25/0292 , Y02D10/14 , Y02D10/151
摘要： A memory device which utilizes a plurality of memory modules coupled in parallel to a master I/O module through a bus. Each memory module has independent address and command decoders to enable independent operation. Thus each memory module is activated by commands on the bus only when a memory access operation is performed within the particular memory module. Each memory module has a programmable identification register which stores a communication address of the module. The communication address for each module can be changed during operation of the memory device by a command from the bus. The memory device includes redundant memory modules to replace defective memory modules. Replacement can be carried out through commands on the bus.
摘要翻译：一种利用通过总线并联到主I / O模块的多个存储器模块的存储器件。每个存储器模块具有独立的地址和命令解码器，以实现独立操作。因此，只有当在特定存储器模块内执行存储器访问操作时，每个存储器模块才被总线上的命令激活。每个存储器模块具有存储模块的通信地址的可编程标识寄存器。通过总线的命令可以在存储器件的操作期间改变每个模块的通信地址。存储器件包括用于替换有缺陷的存储器模块的冗余存储器模块。可以通过总线上的命令进行更换。

7. 发明授权

US5737587A Resynchronization circuit for circuit module architecture 失效
标题翻译：电路模块架构的再同步电路
公开(公告)号：US5737587A
公开(公告)日：1998-04-07
申请号：US473633
申请日：1995-06-06
申请人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
发明人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
IPC分类号： G06F5/16 , G06F11/00 , G06F11/10 , G06F11/20 , G06F12/06 , G06F13/40 , G11C29/00 , G11C29/48 , H01L21/66 , H01L27/02 , H04L25/02 , G06F1/04
CPC分类号： H04L25/026 , G06F12/0661 , G06F13/4077 , G06F5/16 , G11C29/006 , G11C29/48 , G11C29/76 , G11C29/808 , G11C29/832 , G11C29/88 , H01L22/22 , G06F11/006 , G06F11/10 , G06F11/1666 , H01L27/0203 , Y02B60/1225 , Y02B60/1228 , Y02B60/1235
摘要： A memory system having several memory devices coupled to a memory controller through an I/O bus, each memory device including multiple memory modules coupled to a chip I/O interface through an internal bus. The system includes a circuit for driving the I/O bus with a reduced CMOS-swing, a circuit for driving the internal bus with a full CMOS-swing in one bus direction and with a reduced CMOS-swing in the other bus direction, a column address generation circuit for allowing sequentially addressed data to be accessed with the decoder delay being eliminated, and a circuit for re-synchronizing data from a source clock to a destination clock with reduced access latency penalty. Simultaneously writing data into multiple circuit modules significantly increases the write bandwidth of the memory. Also included are a dynamic base-address mapping into an address space, a read or write operation across multiple memory modules, a novel I/O bus format, and a protocol and test mode for testing redundant memory sub-arrays.
摘要翻译：具有通过I / O总线耦合到存储器控制器的几个存储器件的存储器系统，每个存储器件包括通过内部总线耦合到芯片I / O接口的多个存储器模块。该系统包括用于以减小的CMOS摆动驱动I / O总线的电路，用于在一个总线方向上以完全CMOS摆动驱动内部总线并且在另一个总线方向上以减小的CMOS摆幅驱动内部总线的电路列地址产生电路，用于允许在解码器延迟被消除的情况下访问顺序寻址的数据;以及电路，用于将来自源时钟的数据重新同步到具有降低的访问延迟代价的目的地时钟。同时将数据写入多个电路模块会显着增加存储器的写入带宽。还包括动态基地址映射到地址空间，跨多个存储器模块的读或写操作，新颖的I / O总线格式以及用于测试冗余存储器子阵列的协议和测试模式。

8. 发明授权

US07353438B2 Transparent error correcting memory 失效
标题翻译：透明错误纠正内存
公开(公告)号：US07353438B2
公开(公告)日：2008-04-01
申请号：US10645861
申请日：2003-08-20
申请人： Wingyu Leung , Kit Sang Tam , Mikolaj Tworek , Fu-Chieh Hsu
发明人： Wingyu Leung , Kit Sang Tam , Mikolaj Tworek , Fu-Chieh Hsu
IPC分类号： G11C29/00
CPC分类号： G06F11/1048
摘要： A memory system with transparent error correction circuitry provides full stuck-at fault coverage for both test data patterns and the corresponding error correction code (ECC) values. The memory system includes a semiconductor memory having a memory array, a memory interface and an error detection/correction unit. The memory array is configured to store test data patterns and corresponding error correction code (ECC) values. The memory interface is configured such that the ECC values are not directly accessible. The error detection/correction unit is configured to correct single-bit errors in the test data patterns and corresponding ECC values. A set of test data patterns associated with the semiconductor memory is selected such that any multiple-bit error in a test data pattern and the corresponding ECC value causes the error detection/correction unit to provide an output data pattern having an error, thereby rendering multiple-bit faults 100% detectable.
摘要翻译：具有透明误差校正电路的存储器系统为测试数据模式和相应的纠错码（ECC）值提供完全卡住的故障覆盖。存储器系统包括具有存储器阵列，存储器接口和错误检测/校正单元的半导体存储器。存储器阵列被配置为存储测试数据模式和相应的纠错码（ECC）值。存储器接口被配置为使得ECC值不能直接访问。错误检测/校正单元被配置为校正测试数据模式中的单位错误和对应的ECC值。选择与半导体存储器相关联的一组测试数据模式，使得测试数据模式中的任何多位错误和相应的ECC值导致错误检测/校正单元提供具有错误的输出数据模式，从而渲染多个位错误100％可检测。

9. 发明授权

US07206913B2 High speed memory system 有权
标题翻译：高速存储系统
公开(公告)号：US07206913B2
公开(公告)日：2007-04-17
申请号：US10927157
申请日：2004-08-25
申请人： Fu-Chieh Hsu , Wingyu Leung
发明人： Fu-Chieh Hsu , Wingyu Leung
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F12/0855 , G06F12/0879 , G06F12/0897 , G06F12/10 , G11C7/10 , G11C7/1018 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C11/406 , G11C11/4076 , G11C11/4096
摘要： A method and structure for implementing a DRAM memory array as a second level cache memory in a computer system. The computer system includes a central processing unit (CPU), a first level SRAM cache memory, a CPU bus coupled to the CPU, and second level cache memory which includes a DRAM array coupled to the CPU bus. When accessing the DRAM array, row access and column decoding operations are performed in a self-timed asynchronous manner. Predetermined sequences of column select operations are then performed in a synchronous manner with respect to a clock signal. A widened data path is provided to the DRAM array, effectively increasing the data rate of the DRAM array. By operating the DRAM array at a higher data rate than the CPU bus, additional time is provided for precharging the DRAM array. As a result, precharging of the DRAM array is transparent to the CPU bus.
摘要翻译：一种用于在计算机系统中实现DRAM存储器阵列作为第二级高速缓冲存储器的方法和结构。计算机系统包括中央处理单元（CPU），第一级SRAM缓存存储器，耦合到CPU的CPU总线以及包括与CPU总线耦合的DRAM阵列的第二级高速缓冲存储器。当访问DRAM阵列时，以自定时的异步方式执行行访问和列解码操作。然后以相对于时钟信号的同步方式执行列选择操作的预定序列。向DRAM阵列提供加宽的数据路径，有效地增加DRAM阵列的数据速率。通过以比CPU总线更高的数据速率操作DRAM阵列，为DRAM阵列预充电提供了额外的时间。因此，DRAM阵列的预充电对于CPU总线是透明的。

10. 发明申请

US20050027929A1 High speed memory system 有权
标题翻译：高速存储系统
公开(公告)号：US20050027929A1
公开(公告)日：2005-02-03
申请号：US10927157
申请日：2004-08-25
申请人： Fu-Chieh Hsu , Wingyu Leung
发明人： Fu-Chieh Hsu , Wingyu Leung
IPC分类号： G06F12/00 , G06F12/06 , G06F12/08
CPC分类号： G06F12/0893 , G06F12/0855 , G06F12/0879 , G06F12/0897 , G06F12/10 , G11C7/10 , G11C7/1018 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C11/406 , G11C11/4076 , G11C11/4096
摘要： A method and structure for implementing a DRAM memory array as a second level cache memory in a computer system. The computer system includes a central processing unit (CPU), a first level SRAM cache memory, a CPU bus coupled to the CPU, and second level cache memory which includes a DRAM array coupled to the CPU bus. When accessing the DRAM array, row access and column decoding operations are performed in a self-timed asynchronous manner. Predetermined sequences of column select operations are then performed in a synchronous manner with respect to a clock signal. A widened data path is provided to the DRAM array, effectively increasing the data rate of the DRAM array. By operating the DRAM array at a higher data rate than the CPU bus, additional time is provided for precharging the DRAM array. As a result, precharging of the DRAM array is transparent to the CPU bus.
摘要翻译：一种用于在计算机系统中实现DRAM存储器阵列作为第二级高速缓冲存储器的方法和结构。计算机系统包括中央处理单元（CPU），第一级SRAM缓存存储器，耦合到CPU的CPU总线以及包括与CPU总线耦合的DRAM阵列的第二级高速缓冲存储器。当访问DRAM阵列时，以自定时的异步方式执行行访问和列解码操作。然后以相对于时钟信号的同步方式执行列选择操作的预定序列。向DRAM阵列提供加宽的数据路径，有效地增加了DRAM阵列的数据速率。通过以比CPU总线更高的数据速率操作DRAM阵列，为DRAM阵列预充电提供了额外的时间。因此，DRAM阵列的预充电对于CPU总线是透明的。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式