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1. 发明授权

US4317169A Data processing system having centralized memory refresh 失效
标题翻译：数据处理系统具有集中的内存刷新
公开(公告)号：US4317169A
公开(公告)日：1982-02-23
申请号：US12081
申请日：1979-02-14
申请人： William Panepinto, Jr. , Ming T. Miu , Chester M. Nibby, Jr. , Jian-Kuo Shen
发明人： William Panepinto, Jr. , Ming T. Miu , Chester M. Nibby, Jr. , Jian-Kuo Shen
IPC分类号： G06F12/00 , G11C11/406 , G06F13/00
CPC分类号： G11C11/406
摘要： In a data processing system which includes a central processing unit and one or more main memory units for storing program software instructions and program data, logic is provided within the CPU to signal the main memory units, comprised of semiconductor random access memory chips, that a memory refresh operation can be performed. The logic is organized such that the memory refresh operation signal may be given to the main memory units in parallel with and without detracting from other CPU operations. Further, logic is provided within the CPU to interrupt the CPU normal processing and perform a memory refresh operation if one has not been performed with a predetermined time period. Logic is provided within each main memory unit to accept the memory refresh signals from the CPU and to discard those memory refresh signals that would refresh the memory more frequently than required to retain the memory contents thus reducing main memory power consumption.
摘要翻译：在包括中央处理单元和用于存储程序软件指令和程序数据的一个或多个主存储器单元的数据处理系统中，在CPU内提供逻辑以对由半导体随机存取存储器芯片组成的主存储器单元进行信号，可以执行存储器刷新操作。逻辑被组织使得可以将存储器刷新操作信号并行并且不降低其他CPU操作的情况下给予主存储器单元。此外，在CPU内提供中断CPU正常处理的逻辑，并且如果在预定时间段内未执行存储器刷新操作则执行存储器刷新操作。在每个主存储器单元内提供逻辑以接受来自CPU的存储器刷新信号，并且丢弃将比保持存储器内容所需的频率更新的内存刷新信号，从而减少主存储器功耗的那些存储器刷新信号。

2. 发明授权

US4340933A Data processing system having centralized nonexistent memory address detection 失效
标题翻译：数据处理系统具有集中的不存在的存储器地址检测
公开(公告)号：US4340933A
公开(公告)日：1982-07-20
申请号：US8010
申请日：1979-02-12
申请人： Ming T. Miu , John J. Bradley , William Panepinto, Jr. , Jian-Kuo Shen
发明人： Ming T. Miu , John J. Bradley , William Panepinto, Jr. , Jian-Kuo Shen
IPC分类号： G06F12/06 , G06F13/362 , G06F11/00 , G06F13/00
CPC分类号： G06F13/362 , G06F12/0684
摘要： In a data processing system which includes a central processing unit (CPU) having one or more common buses to which one or more main memory units for storing program software instructions and program data are connected, logic is provided within the CPU for detecting an attempt to access a main memory location not contained in the one or more main memory units present in the data processing system. Logic is provided for detecting the attempt to access the nonexistent memory location for the case where the access was being done in the course of the CPU executing a software instruction or for the case of where the access was being done to transfer data between the main memory and an input/output controller connected to one of the one or more common buses.
摘要翻译：在包括具有连接有用于存储程序软件指令和程序数据的一个或多个主存储单元的一个或多个公共总线的中央处理单元（CPU）的数据处理系统中，在CPU内提供逻辑，以检测尝试访问未包含在数据处理系统中存在的一个或多个主存储器单元中的主存储器位置。提供逻辑用于检测在CPU执行软件指令的过程中进行访问的情况下的访问不存在的存储器位置的尝试，或者在执行访问以在主存储器之间传送数据的情况下以及连接到所述一个或多个公共总线中的一个的输入/输出控制器。

3. 发明授权

US4296467A Rotating chip selection technique and apparatus 失效
标题翻译：旋转芯片选择技术和装置
公开(公告)号：US4296467A
公开(公告)日：1981-10-20
申请号：US921292
申请日：1978-07-03
申请人： Chester M. Nibby, Jr. , William Panepinto, Jr.
发明人： Chester M. Nibby, Jr. , William Panepinto, Jr.
IPC分类号： G06F12/06 , G11C11/407 , G11C13/00
CPC分类号： G11C11/407 , G06F12/0669
摘要： A memory subsystem includes at least one up to a number of memory module boards identical in layout and construction. The board includes a number of memory chips which are positioned at an initial physical row location providing a predetermined number of addressable contiguous memory locations corresponding to a predetermined increment of memory capacity. The board further includes a register for receiving address signals for accessing the contents of a memory location, rotating chip selection circuits which include a set of switches and an arithmetic unit having first and second sets of input terminals. The first set of input terminals is connected to the register for receiving predetermined ones of the address signals representative of the physical row location of chips being addressed and the second set of input terminals are connected to receive signals from the set of switches. The arithmetic unit operates to perform a predetermined arithmetic operation upon the signals applied to the sets of input terminals to generate a set of logical row address signals for enabling the number of chips at the initial row location.
摘要翻译：存储器子系统包括至少一个在布局和结构上相同的多个存储器模块板。该板包括多个存储器芯片，这些存储器芯片位于初始物理行位置，提供对应于预定增量的存储器容量的预定数量的可寻址连续存储器位置。板还包括一个寄存器，用于接收访问存储器位置的内容的地址信号，旋转芯片选择电路包括一组开关和具有第一组和第二组输入端的运算单元。第一组输入端子连接到寄存器，用于接收表示正在寻址的芯片的物理行位置的预定的地址信号，并且第二组输入端子被连接以从该组开关接收信号。算术单元操作以对施加到输入端子组的信号执行预定的算术运算，以产生用于使初始行位置处的码片数量的一组逻辑行地址信号。

4. 发明授权

US4303993A Memory present apparatus 失效
标题翻译：存储器设备
公开(公告)号：US4303993A
公开(公告)日：1981-12-01
申请号：US83438
申请日：1979-10-10
申请人： William Panepinto, Jr. , Chester M. Nibby, Jr.
发明人： William Panepinto, Jr. , Chester M. Nibby, Jr.
IPC分类号： G06F12/06 , G11C8/12 , G11C13/00
CPC分类号： G06F12/0669 , G11C8/12
摘要： A memory subsystem includes at least one up to a number of memory module boards identical in layout and construction. The board includes a number of memory chips which are positioned in a number of physical row locations together providing a predetermined number of addressable contiguous memory locations corresponding to a predetermined increment of memory capacity. The board includes a set of switches whose input terminals are connected to receive predetermined ones of a plurality of address signals. These predetermined signals are coded specifying the segments of memory being accessed. The signals applied to the switch output terminals are logically combined and the resulting signal is applied to a group of memory present circuits connected to receive other ones of the address signals representative of the row of chips being addressed. By altering the set of switches, the group of memory present circuits can be conditioned to generate an output signal for indicating that the same increment is present for accessing within any one of a number of different segments thereby enabling the same board to be used in any available address slot position.
摘要翻译：存储器子系统包括至少一个在布局和结构上相同的多个存储器模块板。该板包括多个存储器芯片，这些存储器芯片位于多个物理行位置，一起提供对应于预定增量的存储器容量的预定数量的可寻址连续存储单元。该板包括一组开关，其输入端连接以接收多个地址信号中的预定的开关。这些预定信号被编码，指定被访问的存储器的段。施加到开关输出端子的信号被逻辑地组合，并且所得到的信号被施加到连接的一组存储器当前电路，以接收代表所寻址的芯片行的其他地址信号。通过改变开关组，可以调节存储器组电路以产生输出信号，以指示存在相同的增量用于在多个不同段中的任何一个中进行访问，从而使同一板可以用于任何可用的地址槽位置。

5. 发明授权

US4195341A Initialization of cache store to assure valid data 失效
标题翻译：初始化缓存存储以确保有效的数据
公开(公告)号：US4195341A
公开(公告)日：1980-03-25
申请号：US863094
申请日：1977-12-22
申请人： Thomas F. Joyce , William Panepinto, Jr.
发明人： Thomas F. Joyce , William Panepinto, Jr.
IPC分类号： F02B75/02 , G06F11/22 , G06F12/08 , G06F13/00 , G11C9/06
CPC分类号： G06F11/2284 , G06F12/0891 , F02B2075/027
摘要： A data processing system includes a central processor subsystem, a main memory subsystem and a cache subsystem, all coupled in common to a system bus. During the overall system initialization process, apparatus in the cache subsystem effects the transfer of information from the main memory subsystem to the cache subsystem to load all address locations of the cache subsystem. The transfer of information from the main memory subsystem to the cache subsystem starts from the lowest order address locations in main memory and continues from successive address locations until the cache subsystem is fully loaded. This assures that the cache subsystem contains valid information during normal data processing.
摘要翻译：数据处理系统包括中央处理器子系统，主存储器子系统和高速缓存子系统，其全部共同耦合到系统总线。在整个系统初始化过程中，缓存子系统中的装置影响从主存储器子系统到缓存子系统的信息传输，以加载高速缓存子系统的所有地址位置。从主存储器子系统到高速缓存子系统的信息传输从主存储器中的最低地址位置开始，并从连续的地址位置继续，直到缓存子系统完全加载。这确保了缓存子系统在正常数据处理期间包含有效信息。

6. 发明授权

US4214303A Word oriented high speed buffer memory system connected to a system bus 失效
标题翻译：面向文字的高速缓冲存储器系统连接到系统总线
公开(公告)号：US4214303A
公开(公告)日：1980-07-22
申请号：US863093
申请日：1977-12-22
申请人： Thomas F. Joyce , Thomas O. Holtey , William Panepinto, Jr.
发明人： Thomas F. Joyce , Thomas O. Holtey , William Panepinto, Jr.
IPC分类号： F02B75/02 , G06F12/08 , G06F12/12 , G06F13/00
CPC分类号： G06F12/0862 , G06F12/123 , F02B2075/027
摘要： A word oriented data processing system includes a plurality of system units all connected in common to a system bus. Included are a central processor unit (CPU), a memory system and a high speed buffer or cache system. The cache system is also coupled to the CPU. The cache includes an address directory and a data store with each address location of directory addressing its respective word in data store. The CPU requests a word of cache by sending a memory request to cache which includes a memory address location. If the requested word is stored in the data store, then it is sent to the CPU. If the word is not stored in cache, the cache requests the word of memory. When the cache receives the word from memory, the word is sent to the CPU and also stored in the data store.
摘要翻译：面向字的数据处理系统包括多个系统单元，其全部共同连接到系统总线。包括中央处理器单元（CPU），存储器系统和高速缓冲器或缓存系统。缓存系统也耦合到CPU。高速缓存包括地址目录和数据存储，其中目录的每个地址位置在数据存储器中寻址其相应的字。 CPU通过发送包含存储器地址位置的高速缓存的存储器请求来请求高速缓存字。如果请求的字存储在数据存储中，则发送到CPU。如果该字未存储在高速缓存中，则缓存请求内存字。当缓存从存储器接收到该字时，该字被发送到CPU并存储在数据存储器中。

7. 发明授权

US4167782A Continuous updating of cache store 失效
标题翻译：连续更新缓存存储
公开(公告)号：US4167782A
公开(公告)日：1979-09-11
申请号：US863092
申请日：1977-12-22
申请人： Thomas F. Joyce , Thomas O. Holtey , William Panepinto, Jr.
发明人： Thomas F. Joyce , Thomas O. Holtey , William Panepinto, Jr.
IPC分类号： F02B75/02 , G06F12/08 , G06F12/12 , G06F13/14 , G06F13/16 , G06F13/00
CPC分类号： G06F12/0862 , G06F12/0802 , G06F12/0831 , G06F12/123 , F02B2075/027
摘要： A data processing system includes a plurality of system units all connected in common to a system bus. Included are a main memory system and a high speed buffer or cache store. System units communicate with each other over the system bus. Apparatus in the cache store monitors each communication between system units to determine if it is a communication from a system unit to main memory which will update a word location in main memory. If that word location is also stored in cache then the word location in cache will be updated in addition to the word location in main memory.
摘要翻译：数据处理系统包括多个系统单元，它们都共同连接到系统总线。包括主存储系统和高速缓存或缓存存储。系统单元通过系统总线相互通信。高速缓存存储器中的装置监视系统单元之间的每个通信，以确定它是否是从系统单元到主存储器的通信，其将更新主存储器中的字位置。如果该字位置也存储在高速缓存中，除了主存储器中的单词位置之外，高速缓存中的单词位置将被更新。

8. 发明授权

US4266285A Row selection circuits for memory circuits 失效
标题翻译：存储电路的行选择电路
公开(公告)号：US4266285A
公开(公告)日：1981-05-05
申请号：US52999
申请日：1979-06-28
申请人： William Panepinto, Jr.
发明人： William Panepinto, Jr.
IPC分类号： G06F12/06 , G11C11/407 , G11C13/00
CPC分类号： G11C11/407 , G06F12/06
摘要： A memory subsystem includes a memory board comprising of a number of memory chips positioned at a corresponding number of physical row locations. The memory chips are one of two types selected to provide a predetermined memory capacity. The board further includes a number of decoder circuits connected to generate a corresponding number of sets of chip select signals in response to address signals applied thereto. These signals are applied through corresponding sets of logic circuits for application to the memory chips of each row. Additionally, logic gating circuits logically combine predetermined chip select signals for generating additional chip select signals. These additional chip select signals are applied through switches, the outputs of which are applied to predetermined ones of the sets of logic circuits. When the switches are positioned in a predetermined manner, the additional chip select signals are directed to only predetermined one of the physical row locations via the sets of logic circuits. In this case, only the predetermined row locations are populated with one of the types of memory chips of much larger capacity. This provides the same predetermined memory capacity that is provided when all of the physical row locations are populated with the other type of memory chips of smaller capacity making possible reductions in manufacturing costs.
摘要翻译：存储器子系统包括存储器板，该存储器板包括位于相应数量的物理行位置的多个存储器芯片。存储器芯片是选择用于提供预定存储器容量的两种类型之一。该板还包括多个解码器电路，连接到响应于施加到其上的地址信号而产生相应数量的片选信号。这些信号通过相应的逻辑电路组施加到每一行的存储器芯片上。此外，逻辑选通电路逻辑地组合用于产生附加芯片选择信号的预定芯片选择信号。这些附加的芯片选择信号通过开关施加，其输出被施加到逻辑电路组中的预定的一组。当开关以预定的方式定位时，附加芯片选择信号经由逻辑电路集合仅指向物理行位置中的预定的一个。在这种情况下，只有预定的行位置用大容量的存储器芯片的种类之一填充。这提供了当所有物理行位置都填充有较小容量的其他类型的存储器芯片时提供的相同的预定存储器容量，从而可能降低制造成本。

9. 发明授权

US4190885A Out of store indicator for a cache store in test mode 失效
标题翻译：测试模式下缓存存储的存储指示符
公开(公告)号：US4190885A
公开(公告)日：1980-02-26
申请号：US863096
申请日：1977-12-22
申请人： Thomas F. Joyce , William Panepinto, Jr.
发明人： Thomas F. Joyce , William Panepinto, Jr.
IPC分类号： G06F12/16 , F02B75/02 , G06F11/267 , G06F12/08 , G06F11/00 , G06F13/00
CPC分类号： G06F11/267 , F02B2075/027
摘要： A Data Processing System comprises a central processor unit, a main memory and a cache, all coupled in common to a system bus. The central processor unit is also separately coupled to the cache. Apparatus in cache is responsive to signals received from the central processor unit to initiate a test and verification mode of operation in cache. This mode enables the cache to exercise various logic areas of cache and to indicate to the central processor unit hardware faults.
摘要翻译：数据处理系统包括中央处理器单元，主存储器和高速缓存，所有这些都与系统总线共同耦合。中央处理器单元也单独耦合到高速缓存。高速缓存中的设备响应于从中央处理器单元接收的信号，以启动高速缓存中的测试和验证模式。该模式使高速缓存能够运行各种高速缓存的逻辑区域，并向中央处理器单元指示硬件故障。

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