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1. 发明申请

US20120326260A1 PHOTODIODE THAT INCORPORATES A CHARGE BALANCED SET OF ALTERNATING N AND P DOPED SEMICONDUCTOR REGIONS 审中-公开
标题翻译：包含N和P多个半导体区域的充电平衡组的光电
公开(公告)号：US20120326260A1
公开(公告)日：2012-12-27
申请号：US13165050
申请日：2011-06-21
申请人： William French , Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko
发明人： William French , Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko
IPC分类号： H01L31/06 , H01L31/18
CPC分类号： H01L31/103 , H01L31/03529 , Y02E10/50
摘要： A photodiode comprises a first terminal formed in a surface of a semiconductor substrate; a second terminal formed in the substrate surface and spaced apart from the first terminal; and a plurality of adjacent alternating N-type and P-type diffusion regions formed in the substrate surface between the first terminal and the second terminal.
摘要翻译：光电二极管包括形成在半导体衬底的表面中的第一端子; 形成在所述基板表面中并与所述第一端子间隔开的第二端子; 以及形成在第一端子和第二端子之间的衬底表面中的多个相邻的交替的N型和P型扩散区域。

2. 发明授权

US08324603B2 Galvanic isolation that incorporates a transformer with an optical link and that can be integrated onto a single semiconductor substrate 有权
标题翻译：具有变压器和光学链路并且可以集成到单个半导体衬底上的电隔离
公开(公告)号：US08324603B2
公开(公告)日：2012-12-04
申请号：US12862136
申请日：2010-08-24
申请人： William French , Peter J. Hopper , Vladislav Vashchenko , Philipp Lindorfer
发明人： William French , Peter J. Hopper , Vladislav Vashchenko , Philipp Lindorfer
IPC分类号： G02B27/00 , H01L29/00
CPC分类号： G02B6/43 , G02B6/12004 , G02B6/136 , Y10T29/49155
摘要： Methods and structures provide galvanic isolation for electrical systems using a wide oxide filled trench, and that allows power across the system divide with a transformer, and that transmits data at a high baud rate using an optical link. The system solution allows the integration of all of these elements onto a single semiconductor substrate in contrast to currently available galvanic isolation systems that require multiple individual silicon die that are connected by wire bonds and are relatively slow.
摘要翻译：方法和结构为使用宽氧化物填充沟槽的电气系统提供电流隔离，并且允许跨系统的功率与变压器分压，并且使用光链路以高波特率传输数据。与目前可用的电隔离系统相比，该系统解决方案允许将所有这些元件集成到单个半导体衬底上，该电隔离系统需要通过引线键连接并且相对较慢的多个单独的硅管芯。

3. 发明申请

US20110174999A1 GALVANIC ISOLATION THAT INCORPORATES A TRANSFORMER WITH AN OPTICAL LINK AND THAT CAN BE INTEGRATED ONTO A SINGLE SEMICONDUCTOR SUBSTRATE 有权
标题翻译：具有光学链路的变压器并可以集成到单个半导体基板上的隔离隔离
公开(公告)号：US20110174999A1
公开(公告)日：2011-07-21
申请号：US12862136
申请日：2010-08-24
申请人： William French , Peter J. Hopper , Vladislav Vashchenko , Philipp Lindorfer
发明人： William French , Peter J. Hopper , Vladislav Vashchenko , Philipp Lindorfer
IPC分类号： G02B27/00 , H05K3/10
CPC分类号： G02B6/43 , G02B6/12004 , G02B6/136 , Y10T29/49155
摘要： Methods and structures provide galvanic isolation for electrical systems using a wide oxide filled trench, and that allows power across the system divide with a transformer, and that transmits data at a high baud rate using an optical link. The system solution allows the integration of all of these elements onto a single semiconductor substrate in contrast to currently available galvanic isolation systems that require multiple individual silicon die that are connected by wire bonds and are relatively slow.
摘要翻译：方法和结构为使用宽氧化物填充沟槽的电气系统提供电流隔离，并且允许跨系统的功率与变压器分压，并且使用光链路以高波特率传输数据。与目前可用的电隔离系统相比，该系统解决方案允许将所有这些元件集成到单个半导体衬底上，该电隔离系统需要通过引线键连接并且相对较慢的多个单独的硅管芯。

4. 发明授权

US07754505B1 Method of forming a silicon-based light-emitting structure 有权
标题翻译：形成硅基发光结构的方法
公开(公告)号：US07754505B1
公开(公告)日：2010-07-13
申请号：US12284290
申请日：2008-09-19
申请人： Peter J. Hopper , Philipp Lindorfer , William French , Vladislav Vashchenko
发明人： Peter J. Hopper , Philipp Lindorfer , William French , Vladislav Vashchenko
IPC分类号： H01L21/00
CPC分类号： H01L33/387 , H01L33/04 , H01L33/08
摘要： A silicon-based light emitting structure is formed as a high density array of light-emitting p-n junctions that substantially increases the intensity of the light emitted in a planar region. The p-n junctions are formed using standard CMOS processing methods, and emit light in response to applied voltages that generate avalanche breakdown and an avalanche current.
摘要翻译：形成硅基发光结构作为发光p-n结的高密度阵列，其显着增加在平坦区域中发射的光的强度。使用标准CMOS处理方法形成p-n结，并响应于产生雪崩击穿和雪崩电流的施加电压而发光。

5. 发明授权

US07462874B1 Silicon-based light-emitting structure 有权
标题翻译：硅基发光结构
公开(公告)号：US07462874B1
公开(公告)日：2008-12-09
申请号：US11403516
申请日：2006-04-13
申请人： Peter J. Hopper , Philipp Lindorfer , William French , Vladislav Vashchenko
发明人： Peter J. Hopper , Philipp Lindorfer , William French , Vladislav Vashchenko
IPC分类号： H01L33/00
CPC分类号： H01L33/387 , H01L33/04 , H01L33/08
摘要： A silicon-based light emitting structure is formed as a high density array of light-emitting p-n junctions that substantially increases the intensity of the light emitted in a planar region. The p-n junctions are formed using standard CMOS processing methods, and emit light in response to applied voltages that generate avalanche breakdown and an avalanche current.
摘要翻译：形成硅基发光结构作为发光p-n结的高密度阵列，其显着增加在平坦区域中发射的光的强度。使用标准CMOS处理方法形成p-n结，并响应于产生雪崩击穿和雪崩电流的施加电压而发光。

6. 发明授权

US07479435B1 Method of forming a circuit having subsurface conductors 有权
标题翻译：形成具有地下导体的电路的方法
公开(公告)号：US07479435B1
公开(公告)日：2009-01-20
申请号：US11007565
申请日：2004-12-08
申请人： Peter J. Hopper , Vladislav Vashchenko , Philipp Lindorfer , Andy Strachan
发明人： Peter J. Hopper , Vladislav Vashchenko , Philipp Lindorfer , Andy Strachan
IPC分类号： H01L29/788
CPC分类号： H01L21/26586 , H01L21/2652 , H01L21/823418 , H01L27/088 , H01L29/0847
摘要： A MOS transistor and subsurface collectors can be formed by using a hard mask and precisely varying the implant angle, rotation, dose, and energy. In this case, a particular atomic species can be placed volumetrically in a required location under the hard mask. The dopant can be implanted to form sub-silicon volumes of arbitrary shapes, such as pipes, volumes, hemispheres, and interconnects.
摘要翻译：可以通过使用硬掩模并精确地改变植入角度，旋转，剂量和能量来形成MOS晶体管和地下收集器。在这种情况下，特定的原子物质可以体积地放置在硬掩模下的所需位置。可以将掺杂剂注入以形成任意形状的子硅体积，例如管道，体积，半球和互连。

7. 发明授权

US07394133B1 Dual direction ESD clamp based on snapback NMOS cell with embedded SCR 有权
标题翻译：基于具有嵌入式SCR的快速恢复NMOS单元的双向ESD钳位
公开(公告)号：US07394133B1
公开(公告)日：2008-07-01
申请号：US11216774
申请日：2005-08-31
申请人： Vladislav Vashchenko , Peter J. Hopper , Philipp Lindorfer
发明人： Vladislav Vashchenko , Peter J. Hopper , Philipp Lindorfer
IPC分类号： H01L29/72
CPC分类号： H01L27/0262 , H01L29/0692 , H01L29/7436 , H01L29/87
摘要： In an ESD protection structure, dual direction ESD protection is provided by forming an n-well isolation ring around an NMOS device so that the p-well in which the NMOS drain is formed is isolated from the underlying p-substrate by the n-well isolation ring. By forming the n-well isolation ring the p-n-p-n structure of an embedded SCR for reverse ESD protection is provided. The width of the n-well isolation ring and its spacing from the NMOS drain are adjusted to provide the desired SCR parameters.
摘要翻译：在ESD保护结构中，通过在NMOS器件周围形成n阱隔离环来提供双向ESD保护，使得形成NMOS漏极的p阱通过n阱与下面的p衬底隔离隔离环。通过形成n阱隔离环，提供了用于反向ESD保护的嵌入式SCR的p-n-p-n结构。调整n阱隔离环的宽度及其与NMOS漏极的间隔，以提供所需的SCR参数。

8. 发明授权

US07218555B2 Imaging cell that has a long integration period and method of operating the imaging cell 有权
标题翻译：成像细胞具有长的积分期和操作成像细胞的方法
公开(公告)号：US07218555B2
公开(公告)日：2007-05-15
申请号：US11242094
申请日：2005-10-03
申请人： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko , Robert Drury
发明人： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko , Robert Drury
IPC分类号： G11C11/34 , H01L29/788
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11531 , H01L27/14603 , H01L27/14609
摘要： The integration period of an imaging cell, or the time that an imaging cell is exposed to light energy, is substantially increased by utilizing a single-poly, electrically-programmable, read-only-memory (EPROM) structure to capture the light energy. Photogenerated electrons are formed in the channel region of the EPROM structure from the light energy. The photogenerated electrons are then accelerated into having ionizing collisions which, in turn, leads to electrons being injected onto the floating gate of the EPROM structure at a rate that is proportionate to the number of photons captured by the channel region.
摘要翻译：成像单元的积分周期或成像单元暴露于光能的时间通过利用单聚电子可编程只读存储器（EPROM）结构捕获光能而大大增加。光能从EPROM结构的沟道区形成光电子。光生成的电子然后被加速成具有电离碰撞，其进而导致电子以与通道区域捕获的光子数成正比的速率注入到EPROM结构的浮动栅极上。

9. 发明授权

US07209503B1 Laser powered integrated circuit 有权
标题翻译：激光电源集成电路
公开(公告)号：US07209503B1
公开(公告)日：2007-04-24
申请号：US10838671
申请日：2004-05-03
申请人： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko , Yuri Mirgorodski
发明人： Peter J. Hopper , Philipp Lindorfer , Vladislav Vashchenko , Yuri Mirgorodski
IPC分类号： H01S5/00
CPC分类号： H01L27/1446 , H01L27/146
摘要： An integrated circuit is powered by exposing conductive regions, such as the p+ source regions of the PMOS transistors that are formed to receive a supply voltage, to light energy from a light source. The conductive regions function as photodiodes that produce voltages on the conductive regions via the photovoltaic effect.
摘要翻译：集成电路通过将形成为接收电源电压的PMOS晶体管的p +源极区域等导电区域暴露于来自光源的光能来供电。导电区域用作通过光电效应在导电区域上产生电压的光电二极管。

10. 发明授权

US07113427B1 NVM PMOS-cell with one erased and two programmed states 有权
标题翻译： NVM PMOS单元具有一个擦除和两个编程状态
公开(公告)号：US07113427B1
公开(公告)日：2006-09-26
申请号：US11076711
申请日：2005-03-09
申请人： Yuri Mirgorodski , Peter J. Hopper , Vladislav Vashchenko , Philipp Lindorfer
发明人： Yuri Mirgorodski , Peter J. Hopper , Vladislav Vashchenko , Philipp Lindorfer
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/12 , G11C16/3459 , H01L27/115 , H01L29/7881
摘要： NVM cell for storing three levels of charge: one erased and two programmed states. The cell comprises a transistor structure providing a gate current versus gate voltage curve having a shape with a flat region or a second peak. To provide such a structure, one embodiment combines two parallel transistors having different threshold voltages, and another embodiment uses one transistor with variable doping. The gate current curve provides two programming zones. Programming the first state includes applying a voltage across a channel, ramping up a gate voltage in the first programming zone, followed by ramping it back down. Programming the second state comprises applying a voltage across a channel, ramping up a gate voltage past the first programming zone and into the second programming zone, followed by ramping it back down. Ramping the voltage back down may optionally be preceded by turning off the voltage across the channel.
摘要翻译：用于存储三个电荷电平的NVM单元：一个擦除和两个编程状态。该单元包括提供具有平坦区域或第二峰值的形状的栅极电流对栅极电压曲线的晶体管结构。为了提供这样的结构，一个实施例组合了具有不同阈值电压的两个并联晶体管，另一实施例使用一个具有可变掺杂的晶体管栅极电流曲线提供两个编程区域。对第一状态进行编程包括在一个通道上施加电压，使第一个编程区中的栅极电压升高，然后将其向下斜坡。对第二状态进行编程包括在通道上施加电压，将栅极电压升高到第一编程区并进入第二编程区，然后将其向下斜坡。可以选择先将电压降低，然后关闭通道上的电压。

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