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1. 发明申请

US20080268612A1 METHOD OF FORMING ISOLATION LAYER IN SEMICONDUCTOR DEVICE 审中-公开
标题翻译：在半导体器件中形成隔离层的方法
公开(公告)号：US20080268612A1
公开(公告)日：2008-10-30
申请号：US11962611
申请日：2007-12-21
申请人： Whee Won Cho , Cheol Mo Jeong , Jung Geun Kim , Suk Joong Kim , Jong Hye Cho
发明人： Whee Won Cho , Cheol Mo Jeong , Jung Geun Kim , Suk Joong Kim , Jong Hye Cho
IPC分类号： H01L21/762
CPC分类号： H01L21/76232
摘要： The present invention discloses to a method of forming an isolation layer in a semiconductor device. In particular, the method of forming an isolation layer in a semiconductor device of the present invention comprises the steps of providing a semiconductor substrate on which a trench is formed; forming spacers on side walls of the trench; forming a first insulating layer to fill a portion of the trench such that a deposition rate on the semiconductor substrate which is a bottom surface of the trench and exposed between the spacers is higher than that on a surface of the space; and forming a second insulating layer on the first insulating layer so as to fill the trench with the second insulating layer. An O3-TEOS layer on the exposed semiconductor substrate which is a bottom surface of the trench is grown faster than that on a surface of the spacer formed of an oxide layer or a nitride layer to prevent the O3-TEOS layers grown on the side walls from coming into contact with each other, and so it is possible to inhibit a generation of a seam and to enhance a gap-filling characteristic for the trench.
摘要翻译：本发明公开了一种在半导体器件中形成隔离层的方法。特别地，本发明的半导体器件中形成隔离层的方法包括以下步骤：提供其上形成有沟槽的半导体衬底; 在沟槽的侧壁上形成间隔物; 形成第一绝缘层以填充所述沟槽的一部分，使得作为所述沟槽的底表面并暴露在所述间隔物之间的所述半导体衬底上的沉积速率高于所述空间的表面上的沉积速率; 以及在所述第一绝缘层上形成第二绝缘层以便用所述第二绝缘层填充所述沟槽。作为沟槽底面的暴露的半导体衬底上的O 3 -TOS层比由氧化物层或氮化物层形成的间隔物的表面上生长得快，以防止O 在侧壁上生长的3层以上的层彼此接触，因此可以抑制接缝的产生并且增强沟槽的间隙填充特性。

2. 发明授权

US07977205B2 Method of forming isolation layer of semiconductor device 失效
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US07977205B2
公开(公告)日：2011-07-12
申请号：US12815317
申请日：2010-06-14
申请人： Cha Deok Dong , Whee Won Cho , Jung Geun Kim , Cheol Mo Jeong , Suk Joong Kim , Jung Gu Lee
发明人： Cha Deok Dong , Whee Won Cho , Jung Geun Kim , Cheol Mo Jeong , Suk Joong Kim , Jung Gu Lee
IPC分类号： H01L21/76
CPC分类号： H01L27/11521 , H01L21/76232
摘要： A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. Sidewalls and a bottom surface of each of the first trenches are oxidized by a radical oxidization process to form a first oxide layer. An oxidization-prevention spacer is formed on the sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches, wherein each second trench is narrower and deeper than the corresponding first trench. The second trenches are filled with a second oxide layer. The first trenches are filled with an insulating layer.
摘要翻译：形成半导体器件的隔离层的方法包括在半导体衬底的隔离区域中形成第一沟槽。每个第一沟槽的侧壁和底表面被自由基氧化过程氧化以形成第一氧化物层。在每个第一沟槽的侧壁上形成防氧化间隔物。第二沟槽形成在对应的第一沟槽下方的隔离区域中，其中每个第二沟槽比相应的第一沟槽更窄和更深。第二沟槽填充有第二氧化物层。第一沟槽填充有绝缘层。

3. 发明授权

US07736991B2 Method of forming isolation layer of semiconductor device 失效
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US07736991B2
公开(公告)日：2010-06-15
申请号：US11617690
申请日：2006-12-28
申请人： Cha Deok Dong , Whee Won Cho , Jung Geun Kim , Cheol Mo Jeong , Suk Joong Kim , Jung Gu Lee
发明人： Cha Deok Dong , Whee Won Cho , Jung Geun Kim , Cheol Mo Jeong , Suk Joong Kim , Jung Gu Lee
IPC分类号： H01L21/76
CPC分类号： H01L27/11521 , H01L21/76232
摘要： A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. A spacer is formed on sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches. Each second trench is narrower and deeper than the corresponding first trench. A first oxide layer is formed on sidewalls and a bottom surface of each of the second trenches. The first trench is filled with an insulating layer.
摘要翻译：形成半导体器件的隔离层的方法包括在半导体衬底的隔离区域中形成第一沟槽。间隔件形成在每个第一沟槽的侧壁上。第二沟槽形成在对应的第一沟槽下方的隔离区域中。每个第二沟槽比相应的第一沟槽更窄和更深。第一氧化物层形成在每个第二沟槽的侧壁和底表面上。第一沟槽填充有绝缘层。

4. 发明申请

US20100304549A1 METHOD OF FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE 失效
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US20100304549A1
公开(公告)日：2010-12-02
申请号：US12815317
申请日：2010-06-14
申请人： Cha Deok DONG , Whee Won Cho , Jung Geun Kim , Cheol Mo Jeong , Suk Joong Kim , Jung Gu Lee
发明人： Cha Deok DONG , Whee Won Cho , Jung Geun Kim , Cheol Mo Jeong , Suk Joong Kim , Jung Gu Lee
IPC分类号： H01L21/76
CPC分类号： H01L27/11521 , H01L21/76232
摘要： A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. Sidewalls and a bottom surface of each of the first trenches are oxidized by a radical oxidization process to form a first oxide layer. An oxidization-prevention spacer is formed on the sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches, wherein each second trench is narrower and deeper than the corresponding first trench. The second trenches are filled with a second oxide layer. The first trenches are filled with an insulating layer.
摘要翻译：形成半导体器件的隔离层的方法包括在半导体衬底的隔离区域中形成第一沟槽。每个第一沟槽的侧壁和底表面被自由基氧化过程氧化以形成第一氧化物层。在每个第一沟槽的侧壁上形成防氧化间隔物。第二沟槽形成在对应的第一沟槽下方的隔离区域中，其中每个第二沟槽比相应的第一沟槽更窄和更深。第二沟槽填充有第二氧化物层。第一沟槽填充有绝缘层。

5. 发明申请

US20080102579A1 METHOD OF FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE 失效
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US20080102579A1
公开(公告)日：2008-05-01
申请号：US11617690
申请日：2006-12-28
申请人： Cha Deok Dong , Whee Won Cho , Jung Geun Kim , Cheol Mo Jeong , Suk Joong Kim , Jung Gu Lee
发明人： Cha Deok Dong , Whee Won Cho , Jung Geun Kim , Cheol Mo Jeong , Suk Joong Kim , Jung Gu Lee
IPC分类号： H01L21/8242
CPC分类号： H01L27/11521 , H01L21/76232
摘要： A method of forming an isolation layer of a semiconductor device includes forming first trenches in an isolation region of a semiconductor substrate. A spacer is formed on sidewalls of each of the first trenches. Second trenches are formed in the isolation region below the corresponding first trenches. Each second trench is narrower and deeper than the corresponding first trench. A first oxide layer is formed on sidewalls and a bottom surface of each of the second trenches. The first trench is filled with an insulating layer.
摘要翻译：形成半导体器件的隔离层的方法包括在半导体衬底的隔离区域中形成第一沟槽。间隔件形成在每个第一沟槽的侧壁上。第二沟槽形成在对应的第一沟槽下方的隔离区域中。每个第二沟槽比相应的第一沟槽更窄和更深。第一氧化物层形成在每个第二沟槽的侧壁和底表面上。第一沟槽填充有绝缘层。

6. 发明申请

US20080003823A1 Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20080003823A1
公开(公告)日：2008-01-03
申请号：US11647765
申请日：2006-12-29
申请人： Whee Won Cho , Seung Hee Hong , Suk Joong Kim , Cheol Mo Jeong
发明人： Whee Won Cho , Seung Hee Hong , Suk Joong Kim , Cheol Mo Jeong
IPC分类号： H01L21/44 , H01L21/465
CPC分类号： H01L21/76829 , H01L21/76802 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device includes the steps of forming an interlayer insulating layer and an etch-stop nitride layer over a semiconductor substrate, etching the etch-stop nitride layer and the interlayer insulating layer to form contact holes, forming contacts in the contact holes, forming an oxide layer on the entire surface including the contacts, etching the oxide layer using the etch-stop nitride layer as a target, thus forming trenches through which the contacts and the etch-stop nitride layer adjacent to the contacts are exposed, and forming bit lines in the trenches.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成层间绝缘层和蚀刻停止氮化物层，蚀刻蚀刻停止氮化物层和层间绝缘层以形成接触孔，在触点中形成触点在包括触点的整个表面上形成氧化物层，使用蚀刻 - 停留氮化物层作为靶蚀刻氧化层，从而形成沟槽，触点和与触点相邻的蚀刻 - 停止氮化物层通过该沟槽暴露，并在沟槽中形成位线。

7. 发明申请

US20090029522A1 Method of Forming Isolation Layer of Semiconductor Device 审中-公开
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US20090029522A1
公开(公告)日：2009-01-29
申请号：US11954470
申请日：2007-12-12
申请人： Whee Won Cho , Seung Hee Hong , Suk Joong Kim , Jong Hye Cho
发明人： Whee Won Cho , Seung Hee Hong , Suk Joong Kim , Jong Hye Cho
IPC分类号： H01L21/762
CPC分类号： H01L21/76232 , H01L21/31116
摘要： A method of forming isolation layers of a semiconductor device including forming a first insulating layer on a semiconductor substrate including trenches formed in the semiconductor substrate, substituting a top surface of the first insulating layer with salt, removing the salt to expand a space between sidewalls of the first insulating layer, and forming a second insulating layer on the first insulating layer so that the trenches are gap-filled. Thus, trenches can be easily gap-filled with an insulating material.
摘要翻译：一种形成半导体器件的隔离层的方法，包括在半导体衬底上形成第一绝缘层，该半导体衬底包括在半导体衬底中形成的沟槽，用盐代替第一绝缘层的顶表面，除去盐以扩大第二绝缘层的侧壁之间的空间第一绝缘层，并且在第一绝缘层上形成第二绝缘层，使得沟槽间隙填充。因此，沟槽可以容易地用绝缘材料间隙填充。

8. 发明申请

US20070264790A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20070264790A1
公开(公告)日：2007-11-15
申请号：US11557885
申请日：2006-11-08
申请人： Whee Won Cho , Jung Geun Kim , Suk Joong Kim
发明人： Whee Won Cho , Jung Geun Kim , Suk Joong Kim
IPC分类号： H01L21/762
CPC分类号： H01L21/76232
摘要： A method of manufacturing semiconductor devices includes forming a trench in a predetermined region of a substrate. A first insulating layer and a second insulating layer are formed on a entire surface so that the trench is gap-filled. The first and second insulating layers are polished until a top surface of the substrate is exposed. A wet etch process of a low selectivity is performed, so that a portion of the first insulating layer remains on sides of the trench while stripping the second insulating layer. A third insulating layer is formed on the entire surface, so that the trench is gap-filled, thereby forming an isolation structure.
摘要翻译：制造半导体器件的方法包括在衬底的预定区域中形成沟槽。在整个表面上形成第一绝缘层和第二绝缘层，使得沟槽间隙填充。第一绝缘层和第二绝缘层被抛光直到基板的顶表面露出。执行低选择性的湿蚀刻工艺，使得第一绝缘层的一部分保留在沟槽的侧面，同时剥离第二绝缘层。在整个表面上形成第三绝缘层，使得沟槽间隙填充，从而形成隔离结构。

9. 发明申请

US20080268608A1 METHOD OF FABRICATING A FLASH MEMORY DEVICE 审中-公开
标题翻译：制造闪速存储器件的方法
公开(公告)号：US20080268608A1
公开(公告)日：2008-10-30
申请号：US11951926
申请日：2007-12-06
申请人： Suk Joong Kim , Whee Won Cho , Jung Geun Kim , Seong Hwan Myung
发明人： Suk Joong Kim , Whee Won Cho , Jung Geun Kim , Seong Hwan Myung
IPC分类号： H01L21/76
CPC分类号： H01L27/11521
摘要： In a method of fabricating a flash memory device, after an isolation trench is formed, a bottom surface and sidewalls of the trench are gap-filled with a HARP film having a favorable step coverage. A wet etch process is performed such that the HARP film remains on the sidewalls of a tunnel dielectric layer, thereby forming a wing spacer. Accordingly, the tunnel dielectric layer can be protected and an interference phenomenon can be reduced because a control gate to be formed subsequently is located between floating gates.
摘要翻译：在制造闪速存储器件的方法中，在形成隔离沟槽之后，沟槽的底表面和侧壁间隙填充有具有良好阶梯覆盖率的HARP膜。执行湿蚀刻工艺，使得HARP膜保留在隧道介电层的侧壁上，从而形成翼间隔物。因此，由于随后要形成的控制栅极位于浮置栅极之间，所以可以保护隧道介质层并且可以减小干扰现象。

10. 发明申请

US20080220605A1 METHOD OF MANUFACTURING FLASH MEMORY DEVICE 审中-公开
标题翻译：制造闪存存储器件的方法
公开(公告)号：US20080220605A1
公开(公告)日：2008-09-11
申请号：US11955836
申请日：2007-12-13
申请人： Jung Gu Lee , Whee Won Cho , Seong Hwan Myung , Suk Joong Kim
发明人： Jung Gu Lee , Whee Won Cho , Seong Hwan Myung , Suk Joong Kim
IPC分类号： H01L21/283
CPC分类号： H01L27/11521 , H01L27/115
摘要： The present invention discloses a method of manufacturing a flash memory device comprising the steps of forming a first insulating layer and a first conductive layer on a semiconductor substrate; etching the first conductive layer, the first insulating layer and the semiconductor substrate to form a trench; forming an isolation layer on a region on which the trench is formed; forming a second conductive layer to make the second conductive layer contact with the first conductive layer; and removing the second conductive layer formed on the isolation layer.
摘要翻译：本发明公开了一种制造闪速存储器件的方法，包括以下步骤：在半导体衬底上形成第一绝缘层和第一导电层; 蚀刻第一导电层，第一绝缘层和半导体衬底以形成沟槽; 在形成有沟槽的区域上形成隔离层; 形成第二导电层以使第二导电层与第一导电层接触; 以及去除形成在隔离层上的第二导电层。

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