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    • 7. 发明授权
    • Low resistance contact between circuit metal levels
    • 电路金属电平之间的低电阻接触
    • US6023102A
    • 2000-02-08
    • US169084
    • 1998-10-08
    • Tue NguyenSheng Teng Hsu
    • Tue NguyenSheng Teng Hsu
    • H01L21/28H01L21/285H01L21/768H01L23/522H01L23/48
    • H01L21/76844H01L21/76801H01L21/76807H01L21/76831H01L21/76865H01L23/5226H01L21/28568H01L21/76838H01L2924/0002H01L2924/3011
    • A method of forming a direct, copper-to-copper, connection between levels in an IC is disclosed. The method involves the IC processes of conformal deposition and anisotropic etching. A via interconnection is formed by isotropically depositing a barrier material in a via through an insulator to a lower copper level, and then anisotropically etching the via to remove the barrier material covering the lower copper level. The anisotropic etch leaves the barrier material lining the via through the insulator. The subsequently deposited upper metal level then directly contacts the lower copper level when the via is filled. A dual damascene interconnection is formed by anisotropically depositing a non-conductive barrier material in the trench bottom. Then a via is formed with a conductive barrier lining the via sidewalls. An IC via interconnection structure and a dual damascene interconnection structure, made in accordance with the above described methods, are also provided.
    • 公开了一种在IC中形成直接铜铜铜连接电平的方法。 该方法涉及共形沉积和各向异性蚀刻的IC工艺。 通过互连形成通过绝缘体将通孔绝缘体上的阻挡材料各向同性地沉积到较低的铜电平,然后各向异性地蚀刻通孔以除去覆盖较低铜层的阻挡材料。 各向异性蚀刻离开通过绝缘体衬套通孔的阻挡材料。 随后沉积的上层金属层,当通孔填充时,直接接触下铜层。 通过在沟槽底部中各向异性地沉积非导电阻挡材料来形成双镶嵌互连。 然后,通孔形成有衬套通孔侧壁的导电阻挡层。 还提供了根据上述方法制造的通过互连结构和双镶嵌互连结构的IC。