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1. 发明授权

US06785829B1 Multiple operating frequencies in a processor 有权
标题翻译：处理器中的多个工作频率
公开(公告)号：US06785829B1
公开(公告)日：2004-08-31
申请号：US09608160
申请日：2000-06-30
申请人： Varghese George , Robert L. Farrell
发明人： Varghese George , Robert L. Farrell
IPC分类号： G06F132
CPC分类号： G06F1/3296 , G06F1/08 , G06F1/26 , G06F1/3203 , G06F1/324 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： A power control circuit an corresponding technique for adjusting operating frequency and/or supply voltage in sections of a single electronic device while maintaining substantially constant operating frequency and/or supply voltage in the other sections in the electronic device. Such control is based on the operating environment of the hardware product employing the electronic device by determining whether the hardware product is connected to an external power source. As a result, the electronic device in the hardware product is able to operate at full frequency and voltage during certain situations and to operate at a reduced frequency and/or voltage in some sections of the processor and not in the other sections during other situations.
摘要翻译：一种功率控制电路，用于在单个电子设备的部分中调节工作频率和/或电源电压，同时在电子设备中的其它部分保持基本恒定的工作频率和/或电源电压的相应技术。这种控制是基于通过确定硬件产品是否连接到外部电源的采用电子设备的硬件产品的操作环境。结果，硬件产品中的电子设备能够在某些情况下以全频率和电压工作，并且在处理器的某些部分中以不降低的频率和/或电压工作，而在其他情况下不在其他部分。

2. 发明授权

US06988211B2 System and method for selecting a frequency and voltage combination from a table using a selection field and a read-only limit field 失效
标题翻译：使用选择字段和只读限制字段从表格中选择频率和电压组合的系统和方法
公开(公告)号：US06988211B2
公开(公告)日：2006-01-17
申请号：US09751528
申请日：2000-12-29
申请人： Leslie E. Cline , Xia Dai , Varghese George , Robert L. Farrell
发明人： Leslie E. Cline , Xia Dai , Varghese George , Robert L. Farrell
IPC分类号： G06F1/26
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A selectable control over multiple clock frequency/voltage level combinations that can be activated in a processor. A table can be placed in hardware that defines multiple combinations of CPU clock frequency and CPU operating voltage. By placing the table in hardware, it can be assured that all the various combinations will work for the particular processor device. Software can then be used to select a combination from this table, to control the actual frequency/voltage combination that is being implemented at a given time. This allows dynamic control over the power/performance tradeoff, so that the system can see maximum power savings consistent with acceptable performance, as operating and environmental considerations continue to change the most desirable selections.
摘要翻译：可以在处理器中激活的多个时钟频率/电压电平组合的可选择控制。一个表可以放置在硬件中，定义了CPU时钟频率和CPU工作电压的多种组合。通过将表放置在硬件中，可以确保所有各种组合都适用于特定的处理器设备。然后可以使用软件从该表中选择组合，以控制在给定时间正在实施的实际频率/电压组合。这允许对功率/性能的权衡进行动态控制，使得系统可以看到与可接受的性能一致的最大功率节省，因为操作和环境考虑继续改变最理想的选择。

3. 发明授权

US09727388B2 Migrating threads between asymmetric cores in a multiple core processor 有权
公开(公告)号：US09727388B2
公开(公告)日：2017-08-08
申请号：US13995340
申请日：2011-12-29
申请人： Sanjeev S. Jahagirdar , Varghese George , Inder Sodhi
发明人： Sanjeev S. Jahagirdar , Varghese George , Inder Sodhi
IPC分类号： G06F9/50 , G06F9/30 , G06F9/48
CPC分类号： G06F9/5083 , G06F9/30003 , G06F9/4856
摘要： Some implementations provide techniques and arrangements to migrate threads from a first core of a processor to a second core of the processor. For example, some implementations may identify one or more threads scheduled for execution at a processor. The processor may include a plurality of cores, including a first core having a first characteristic and a second core have a second characteristic that is different than the first characteristic. Execution of the one or more threads by the first core may be initiated. A determination may be made whether to apply a migration policy. In response to determining to apply the migration policy, migration of the one or more threads from the first core to the second core may be initiated.

4. 发明授权

US08892861B2 Method and apparatus for establishing safe processor operating points 有权
公开(公告)号：US08892861B2
公开(公告)日：2014-11-18
申请号：US13365096
申请日：2012-02-02
申请人： Stephen Anthony Fischer , Varghese George , Sanjeev Jahagirdar , Stephen H. Gunther
发明人： Stephen Anthony Fischer , Varghese George , Sanjeev Jahagirdar , Stephen H. Gunther
IPC分类号： G06F1/24 , G06F21/57 , G06F21/70
CPC分类号： G06F21/57 , G06F1/324 , G06F1/3296 , G06F21/575 , G06F21/70 , G06F21/81 , G06F2221/2101 , Y02D10/126
摘要： A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more operating points of an adjustable processor operating parameter. Some embodiments may further include an element to determine what the current processor operating point is of the operating parameter, and an element to compare the current operating point of the operating parameter with the stored information.

5. 发明授权

US08707062B2 Method and apparatus for powered off processor core mode 有权
标题翻译：关闭处理器核心模式的方法和设备
公开(公告)号：US08707062B2
公开(公告)日：2014-04-22
申请号：US12706631
申请日：2010-02-16
申请人： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
发明人： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
IPC分类号： G06F1/00 , G06F1/26 , G06F12/00 , G06F15/00 , G06F11/00 , G06F9/46
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
摘要： For one disclosed embodiment, a processor comprises a first processor core, a second processor core, and a cache memory. The first processor core is to save a state of the first processor core and to enter a mode in which the first processor core is powered off. The second processor core is to save a state of the second processor core and to enter a mode in which the second processor core is powered off. The cache memory is to be powered when the first processor core is powered off. The first processor core is to restore the saved state of the first processor core in response to the first processor core transitioning to a mode in which the first processor core is powered. The second processor core is to restore the saved state of the second processor core in response to the second processor core transitioning to a mode in which the second processor core is powered. Other embodiments are also disclosed.
摘要翻译：对于一个公开的实施例，处理器包括第一处理器核心，第二处理器核心和高速缓冲存储器。第一处理器核心是保存第一处理器核心的状态并进入第一处理器核心断电的模式。第二处理器核心是保存第二处理器核心的状态并进入其中第二处理器核心断电的模式。当第一个处理器内核关闭电源时，缓存内存将被供电。第一处理器核心是响应于第一处理器核心转换到第一处理器核心供电的模式来恢复第一处理器核心的保存状态。第二处理器核心是响应于第二处理器核心转换到第二处理器核心供电的模式来恢复第二处理器核心的保存状态。还公开了其他实施例。

6. 发明申请

US20140032950A1 METHOD, APPARATUS, AND SYSTEM FOR OPTIMIZING FREQUENCY AND PERFORMANCE IN A MULTIDIE MICROPROCESSOR 有权
公开(公告)号：US20140032950A1
公开(公告)日：2014-01-30
申请号：US14041688
申请日：2013-09-30
申请人： Jose P. Allarey , Varghese George , Sanjeev S. Jahagirdar , Oren Lamdan , Ofer Nathan , Tomer Ziv
发明人： Jose P. Allarey , Varghese George , Sanjeev S. Jahagirdar , Oren Lamdan , Ofer Nathan , Tomer Ziv
IPC分类号： G06F1/20
CPC分类号： G06F15/82 , G06F1/08 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F9/06 , G06F9/30145 , G06F15/76 , Y02D10/126 , Y02D10/16
摘要： With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status.

7. 发明申请

US20130013909A1 METHOD AND APPARATUS FOR ESTABLISHING SAFE PROCESSOR OPERATING POINTS 有权
标题翻译：建立安全处理器操作要点的方法和装置
公开(公告)号：US20130013909A1
公开(公告)日：2013-01-10
申请号：US13620119
申请日：2012-09-14
申请人： Stephen Anthony Fischer , Varghese George , Sanjeev Jahagirdar , Stephen H. Gunther
发明人： Stephen Anthony Fischer , Varghese George , Sanjeev Jahagirdar , Stephen H. Gunther
IPC分类号： G06F1/28 , G06F9/00
CPC分类号： G06F21/57 , G06F1/324 , G06F1/3296 , G06F21/575 , G06F21/70 , G06F21/81 , G06F2221/2101 , Y02D10/126
摘要： A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more operating points of an adjustable processor operating parameter. Some embodiments may further include an element to determine what the current processor operating point is of the operating parameter, and an element to compare the current operating point of the operating parameter with the stored information.
摘要翻译：提供了一种用于建立安全处理器工作点的系统和方法。一些实施例可以包括防篡改存储元件，其存储关于可调节处理器操作参数的一个或多个操作点的信息。一些实施例可以进一步包括用于确定当前处理器工作点是操作参数的元件，以及将操作参数的当前操作点与存储的信息进行比较的元件。

8. 发明申请

US20120198207A1 ASYMMETRIC PERFORMANCE MULTICORE ARCHITECTURE WITH SAME INSTRUCTION SET ARCHITECTURE 有权
标题翻译：具有相同指令集架构的不对称性能多体建筑
公开(公告)号：US20120198207A1
公开(公告)日：2012-08-02
申请号：US13335257
申请日：2011-12-22
申请人： Varghese George , Sanjeev S. Jahagirdar , Deborah T. Marr
发明人： Varghese George , Sanjeev S. Jahagirdar , Deborah T. Marr
IPC分类号： G06F15/76
CPC分类号： G06F15/80 , G06F1/3206 , G06F1/3293 , G06F1/3296 , G06F9/5094 , G06F13/4022 , Y02D10/122 , Y02D10/151 , Y02D10/22
摘要： A method is described that entails operating enabled cores of a multi-core processor such that both cores support respective software routines with a same instruction set, a first core being higher performance and consuming more power than a second core under a same set of applied supply voltage and operating frequency.
摘要翻译：描述了一种方法，其涉及多核处理器的操作使能的核，使得两个核以相同的指令集支持相应的软件例程，第一核具有更高的性能并且在相同的一组应用供给下消耗比第二个核的更多的功率电压和工作频率。

9. 发明申请

US20110179295A1 METHOD, APPARATUS AND SYSTEM TO DYNAMICALLY CHOOSE AN OPTIMUM POWER STATE 有权
标题翻译：方法，装置和系统动态选择最佳电源状态
公开(公告)号：US20110179295A1
公开(公告)日：2011-07-21
申请号：US13074871
申请日：2011-03-29
申请人： Sanjeev Jahagirdar , Varghese George , Jose Allarey , Eric Heit
发明人： Sanjeev Jahagirdar , Varghese George , Jose Allarey , Eric Heit
IPC分类号： G06F1/32
CPC分类号： G06F1/3203
摘要： Some embodiments of the invention include an apparatus and method for dynamically choosing an optimum power state. In some embodiments, the optimum power state may be determined from historical information about the various power states that any of the embodiments of the apparatus or a system equipped with embodiments of the apparatus or operating embodiments of the method may encounter. Some embodiments may generate registers to maintain information regarding the various power states. In some embodiments, power management logic may determine the optimum power state based upon this information. Other embodiments are described.
摘要翻译：本发明的一些实施例包括用于动态选择最佳功率状态的装置和方法。在一些实施例中，最佳功率状态可以根据关于各种功率状态的历史信息来确定，该装置或装置的任何实施例装备有该方法的装置或操作实施例的实施例可能会遇到。一些实施例可以生成寄存器来维护关于各种功率状态的信息。在一些实施例中，功率管理逻辑可以基于该信息来确定最佳功率状态。描述其他实施例。

10. 发明授权

US07516342B2 Method, apparatus and system to dynamically choose an optimum power state 有权
标题翻译：方法，装置和系统动态选择最佳功率状态
公开(公告)号：US07516342B2
公开(公告)日：2009-04-07
申请号：US11322606
申请日：2005-12-30
申请人： Sanjeev Jahagirdar , Varghese George , Jose Allarey , Eric Heit
发明人： Sanjeev Jahagirdar , Varghese George , Jose Allarey , Eric Heit
IPC分类号： G06F1/26 , G06F1/00
CPC分类号： G06F1/3203
摘要： Some embodiments of the invention include an apparatus and method for dynamically choosing an optimum power state. In some embodiments, the optimum power state may be determined from historical information about the various power states that any of the embodiments of the apparatus or a system equipped with embodiments of the apparatus or operating embodiments of the method may encounter. Some embodiments may generate registers to maintain information regarding the various power states. In some embodiments, power management logic may determine the optimum power state based upon this information. Other embodiments are described.
摘要翻译：本发明的一些实施例包括用于动态选择最佳功率状态的装置和方法。在一些实施例中，最佳功率状态可以根据关于各种功率状态的历史信息来确定，该装置或装置的任何实施例装备有该方法的装置或操作实施例的实施例可能会遇到。一些实施例可以生成寄存器来维护关于各种功率状态的信息。在一些实施例中，功率管理逻辑可以基于该信息来确定最佳功率状态。描述其他实施例。

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