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1. 发明授权

US08427355B2 Time-interleaved pipelined-SAR analog to digital converter with low power consumption 有权
标题翻译：时间交错流水线SAR模数转换器，功耗低
公开(公告)号：US08427355B2
公开(公告)日：2013-04-23
申请号：US13232442
申请日：2011-09-14
申请人： Sai-Weng Sin , Li Ding , Yan Zhu , He-Gong Wei , Chi-Hang Chan , U-Fat Chio , Seng-Pan U , Rui Paulo da Silva Martins , Franco Maloberti
发明人： Sai-Weng Sin , Li Ding , Yan Zhu , He-Gong Wei , Chi-Hang Chan , U-Fat Chio , Seng-Pan U , Rui Paulo da Silva Martins , Franco Maloberti
IPC分类号： H03M1/38
CPC分类号： H03M1/1225 , H03M1/0695 , H03M1/1215 , H03M1/164 , H03M1/468
摘要： An analog-to-digital converter (ADC) circuit comprising two time-interleaved successive approximation register (SAR) ADCs. Each of the two time-interleaved SAR ADCs comprises a first stage SAR sub-ADC, a residue amplifier, a second stage SAR sub-ADC and a digital error correction logic. The residue amplifier is shared between the time-interleaved paths, has a reduced gain and operates in sub-threshold to achieve power effective design.
摘要翻译：包括两个时间交错的逐次逼近寄存器（SAR）ADC的模数转换器（ADC）电路。两个时间交织的SAR ADC中的每一个包括第一级SAR子ADC，残差放大器，第二级SAR子ADC和数字纠错逻辑。剩余放大器在时间交织路径之间共享，具有减小的增益并且在子阈值中操作以实现功率有效设计。

2. 发明申请

US20120194364A1 ANALOG-TO-DIGITAL CONVERTING SYSTEM 有权
标题翻译：模拟数字转换系统
公开(公告)号：US20120194364A1
公开(公告)日：2012-08-02
申请号：US13198856
申请日：2011-08-05
申请人： U-Fat CHIO , He-Gong Wei , Yan Zhu , Sai-Weng Sin , Seng-Pan U , Rui Paulo da Silva Martins , Franco Maloberti
发明人： U-Fat CHIO , He-Gong Wei , Yan Zhu , Sai-Weng Sin , Seng-Pan U , Rui Paulo da Silva Martins , Franco Maloberti
IPC分类号： H03M1/12
CPC分类号： H03M1/145 , H03M1/0695 , H03M1/365 , H03M1/46
摘要： A novel analog-to-digital converter (ADC) system using a two-step conversion is disclosed. The ADC system is capable of achieving high sampling rate, low power consumption and low complexity. The new proposed ADC is formed by cascading a flash ADC having high sampling rate and low resolution with a successive approximation (SA) ADC having low power consumption and low sampling rate.
摘要翻译：公开了一种使用两步转换的新型模 - 数转换器（ADC）系统。 ADC系统能够实现高采样率，低功耗和低复杂度。新提出的ADC是通过使用具有低功耗和低采样率的逐次逼近（SA）ADC级联具有高采样率和低分辨率的闪存ADC来形成的。

3. 发明授权

US08466823B2 Cascade analog-to-digital converting system 有权
标题翻译：级联模数转换系统
公开(公告)号：US08466823B2
公开(公告)日：2013-06-18
申请号：US13198856
申请日：2011-08-05
申请人： U-Fat Chio , He-Gong Wei , Yan Zhu , Sai-Weng Sin , Seng-Pan U , Rui Paulo da Silva Martins , Franco Maloberti
发明人： U-Fat Chio , He-Gong Wei , Yan Zhu , Sai-Weng Sin , Seng-Pan U , Rui Paulo da Silva Martins , Franco Maloberti
IPC分类号： H03M1/12
CPC分类号： H03M1/145 , H03M1/0695 , H03M1/365 , H03M1/46
摘要： A novel analog-to-digital converter (ADC) system using a two-step conversion is disclosed. The ADC system is capable of achieving high sampling rate, low power consumption and low complexity. The new proposed ADC is formed by cascading a flash ADC having high sampling rate and low resolution with a successive approximation (SA) ADC having low power consumption and low sampling rate.
摘要翻译：公开了一种使用两步转换的新型模 - 数转换器（ADC）系统。 ADC系统能够实现高采样率，低功耗和低复杂度。新提出的ADC是通过使用具有低功耗和低采样率的逐次逼近（SA）ADC级联具有高采样率和低分辨率的闪存ADC来形成的。

4. 发明授权

US08344931B2 N-bits successive approximation register analog-to-digital converting circuit 有权
标题翻译： N位逐次逼近寄存器模数转换电路
公开(公告)号：US08344931B2
公开(公告)日：2013-01-01
申请号：US13150508
申请日：2011-06-01
申请人： Yan Zhu , Chi-Hang Chan , U-Fat Chio , Sai-Weng Sin , Seng-Pan U , Rui Paulo Da Silva Martins , Franco Maloberti
发明人： Yan Zhu , Chi-Hang Chan , U-Fat Chio , Sai-Weng Sin , Seng-Pan U , Rui Paulo Da Silva Martins , Franco Maloberti
IPC分类号： H03M1/12
CPC分类号： H03M1/002 , H03M1/466
摘要： The present invention provides an n-bits successive approximation register (SAR) analog-to-digital converting (ADC) circuit, comprising: an n-bits SAR control logic, a p-type capacitor network including a DACp array and a sampling capacitor CSp, an n-type capacitor network including a DACn array and a sampling capacitor CSn; and a comparator for comparing outputs from the p-type capacitor network and the n-type capacitor network, wherein a power supply and ground are directly connected to the p-type capacitor network and the n-type capacitor network without using reference voltages produced by a reference voltage generator. The n-bits SAR control logic comprises n shift registers, n bit registers, and a switching logic. The comparator comprises a first pre-amplifier, a second pre-amplifier and a dynamic latch. Alternative, the comparator comprises a four-input pre-amplifier and a dynamic latch.
摘要翻译：本发明提供一种n位逐次逼近寄存器（SAR）模数转换（ADC）电路，包括：n位SAR控制逻辑，包括DACp阵列和采样电容器CSp的p型电容器网络包括DACn阵列和采样电容器CSn的n型电容器网络; 以及用于比较来自p型电容器网络和n型电容器网络的输出的比较器，其中电源和接地直接连接到p型电容器网络和n型电容器网络，而不使用由p型电容器网络和n型电容器网络产生的参考电压参考电压发生器。 n位SAR控制逻辑包括n个移位寄存器，n个位寄存器和一个开关逻辑。比较器包括第一前置放大器，第二前置放大器和动态锁存器。替代方案，比较器包括四输入前置放大器和动态锁存器。

5. 发明授权

US07385536B2 Methods and circuits for output of sample-and-hold in pipelined ADC 有权
标题翻译：流水线ADC中采样和保持输出的方法和电路
公开(公告)号：US07385536B2
公开(公告)日：2008-06-10
申请号：US11012015
申请日：2004-12-14
申请人： Martin Kithinji Kinyua , Franco Maloberti
发明人： Martin Kithinji Kinyua , Franco Maloberti
IPC分类号： H03M1/00
CPC分类号： G11C27/026 , H03M1/1245 , H03M1/164 , H03M1/442
摘要： Methods and circuit embodiments are disclosed for implementing an improved signal path for a sample-and-hold output. In exemplary embodiments, a sample-and-hold signal path for use in a pipelined ADC includes a sample-and-hold circuit configured to operate in two distinct phases. The sample-and-hold circuit includes an input node, an output node, and a power supply node. The power supply node is configured to power down the op amp during one phase and power up the op amp during the other phase. The sample-and-hold stage is configured to provide output during one phase only. Other aspects of the invention include embodiments in which a sample-and-hold stage signal path in a pipelined analog-to-digital converter is configured to accommodate a plurality of parallel outputs.
摘要翻译：公开了实现用于采样和保持输出的改进的信号路径的方法和电路实施例。在示例性实施例中，用于流水线式ADC的采样和保持信号路径包括被配置为在两个不同阶段中操作的采样和保持电路。采样和保持电路包括输入节点，输出节点和电源节点。电源节点配置为在一个阶段关闭运算放大器，并在另一阶段加电运算放大器。采样和保持级配置为仅在一个阶段提供输出。本发明的其它方面包括其中流水线模数转换器中的采样保持级信号路径被配置为容纳多个并行输出的实施例。

6. 发明授权

US07230452B2 Driver circuit 有权
标题翻译：驱动电路
公开(公告)号：US07230452B2
公开(公告)日：2007-06-12
申请号：US11112267
申请日：2005-04-22
申请人： Siew Kuok Hoon , Franco Maloberti , Jun Chen
发明人： Siew Kuok Hoon , Franco Maloberti , Jun Chen
IPC分类号： H03K19/0175
CPC分类号： H03K17/0822 , H03K17/04206 , H03K17/165
摘要： A driver circuit includes a first transistor coupled between an input supply node and an output node. The first transistor operates in one of a conductive state to couple the output node with the input supply node and non-conductive state according to cooperative operation of a second transistor and a third transistor. The second transistor is coupled to provide a control input to drive the first transistor to the conductive state thereof in response a first input signal provided at a control input of the second transistor. The third transistor is coupled to provide an output at the output node in response to a second input signal provided at a control input of the third transistor, the first and second input signals being out of phase with each other. Circuitry is coupled between the input supply node and the control input of the first transistor to provide reduced impedance at the control input of the first transistor according to operation of the second transistor.
摘要翻译：驱动电路包括耦合在输入电源节点和输出节点之间的第一晶体管。第一晶体管根据第二晶体管和第三晶体管的协同操作，以导通状态中的一个工作，以将输出节点与输入电源节点耦合和非导通状态。第二晶体管被耦合以提供控制输入，以响应于提供在第二晶体管的控制输入处的第一输入信号而将第一晶体管驱动到其导电状态。第三晶体管被耦合以响应于在第三晶体管的控制输入处提供的第二输入信号在输出节点处提供输出，第一和第二输入信号彼此不同相。电路耦合在输入电源节点和第一晶体管的控制输入之间，以根据第二晶体管的操作在第一晶体管的控制输入处提供降低的阻抗。

7. 发明申请

US20050140433A1 Switched-capacitor circuits with reduced finite-gain effect 有权
标题翻译：开关电容电路具有减小的有限增益效应
公开(公告)号：US20050140433A1
公开(公告)日：2005-06-30
申请号：US10750508
申请日：2003-12-31
申请人： Franco Maloberti , Martin Kinyua
发明人： Franco Maloberti , Martin Kinyua
IPC分类号： H03F3/00 , H03F3/45 , H03F1/02
CPC分类号： H03F3/45977 , H03F3/005
摘要： Operational amplifier circuits (20, 30) including error capacitors (C3, C13) for storing finite gain effect error voltages for correction of output voltages of the circuits (20, 30), are disclosed. The circuits (20, 30) are operated in a sample clock phase to produce an approximation of the output voltage, using negative polarity versions of the input voltages to the circuit. The approximate output voltage is used to produce and store an error voltage, corresponding to the differential voltage at the input of the operational amplifier (15, 25), relative to virtual ground. This error voltage is then subtracted from the input voltage applied in the operate clock phase, to correct for the finite gain effect. A pipelined analog-to-digital converter (50) using the disclosed operational amplifier circuits (20, 30) is also disclosed.
摘要翻译：公开了用于存储用于校正电路（20,30）的输出电压的有限增益效应误差电压的运算放大器电路（20,30），其包括误差电容器（C 3，C 13）。电路（20,30）在采样时钟相位下工作，以使用对电路的输入电压的负极性版本来产生输出电压的近似。近似输出电压用于产生和存储对应于运算放大器（15,25）的输入处的差分电压相对于虚拟接地的误差电压。然后从施加在操作时钟相位的输入电压中减去该误差电压，以校正有限增益效应。还公开了使用所公开的运算放大器电路（20,30）的流水线模数转换器（50）。

8. 发明申请

US20050137802A1 Continuous digital background calibration in pipelined ADC architecture 有权
标题翻译：流水线ADC结构中的连续数字背景校准
公开(公告)号：US20050137802A1
公开(公告)日：2005-06-23
申请号：US10738751
申请日：2003-12-17
申请人： Franco Maloberti , Martin Kinyua
发明人： Franco Maloberti , Martin Kinyua
IPC分类号： G06F19/00 , H03M1/10 , H03M1/14
CPC分类号： H03M1/1004 , H03M1/145
摘要： Disclosed are new methods and systems for achieving calibration in a pipelined ADC system. The methods and systems may be used to provide continuous digital background calibration in a pipelined ADC. Component mismatch error from each DAC in the pipeline is tabulated to provide an integral nonlinearity profile, which is subtracted from the ADC transfer characteristic.
摘要翻译：公开了用于在流水线ADC系统中实现校准的新方法和系统。方法和系统可用于在流水线ADC中提供连续数字背景校准。流水线中每个DAC的组件不匹配错误列表，以提供从ADC传输特性中减去的积分非线性配置文件。

9. 发明授权

US5146777A Device for detecting pinking, cylinder by cylinder, in a multi-cylinder otto engine 失效
标题翻译：用于在多缸发动机中检测气缸，缸体的缸体的装置
公开(公告)号：US5146777A
公开(公告)日：1992-09-15
申请号：US592401
申请日：1990-10-03
申请人： Gino Polito , Franco Maloberti , Franco Salerno
发明人： Gino Polito , Franco Maloberti , Franco Salerno
IPC分类号： F02D45/00 , F02B1/04 , F02P5/152 , G01L23/22
CPC分类号： G01L23/225 , F02P5/1522 , F02B1/04 , Y02T10/46
摘要： The device includes two channels for detecting and processing the signal provided by an accelerometric sensor, operating in two frequency bands in which peaks indicative of pinking (knocking) may occur. In each combustion phase, a third channel, also connected to the sensor, provides a signal representative of the noise component of the signal from the sensor, in a frequency band in which the peaks do not occur. The signals provided by the first and second channels are integrated and then compared with a reference signal generated in dependence on the noise component detected cylinder by cylinder. The device thus enables pinking to be detected cylinder by cylinder.

10. 发明授权

US4994730A Current source circuit with complementary current mirrors 失效
标题翻译：具有互补电流镜的电流源电路
公开(公告)号：US4994730A
公开(公告)日：1991-02-19
申请号：US448498
申请日：1989-12-11
申请人： Domenico Rossi , Ermes Viani , Guido Torelli , Franco Maloberti , Carla Vacchi
发明人： Domenico Rossi , Ermes Viani , Guido Torelli , Franco Maloberti , Carla Vacchi
IPC分类号： G05F3/24 , G05F3/26
CPC分类号： G05F3/262
摘要： A current source circuit capable of generating two currents of opposite polarities. In order to generate the two currents, the circuit comprises a current source stage including a current mirror and feeding a first output current and an inverter stage connected to the source stage and generating a second output current with opposite polarity with respect to the first. The inverter stage comprises a current mirror and a variable current source defining a control electrode. In order to eliminate the differences in the amplitude of the output currents, the inverter stage comprises a memory element connected to the control electrode so as to store an electrode controlling signal. Switch elements are furthermore interposed between the first output and the second output so as to short-circuit them during the trimming step so that the two output currents are equal to one another while the memory element memorizes the control signal. This signal remains stored during the normal operation of the circuit.

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