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1. 发明授权

US5034885A Cache memory device with fast data-write capacity 失效
标题翻译：具有快速数据写入能力的缓存存储器件
公开(公告)号：US5034885A
公开(公告)日：1991-07-23
申请号：US321398
申请日：1989-03-10
申请人： Tsukasa Matoba , Takeshi Aikawa , Mitsuyoshi Okamura , Kenichi Maeda
发明人： Tsukasa Matoba , Takeshi Aikawa , Mitsuyoshi Okamura , Kenichi Maeda
IPC分类号： G06F12/08
CPC分类号： G06F12/0855
摘要： A copy-back type cache memory device using a delayed wait method capable of completing a data-write process in one process cycle. The device includes single word memory means for storing the single word of the selected data in a data memory means when an access for a data-write is made, the single word being located at the address in the data memory means corresponding to the processor address; and copy-back memory means for restoring the superseded data along with other data together with which the superseded data forms a block, so that the block can be reorganized in its original state before the data-write process takes place. The device may alternatively include an address latch means for delaying transmission of a processor address from the processor to the data memory means by a predetermined number of process cycles when access by the processor is for a data-write process; and a data latch means for delaying transmission of a processor data from the processor to the data memory means by the predetermined number of process cycles when access by the processor is for a data-write process.
摘要翻译：使用能够在一个处理周期中完成数据写入处理的延迟等待方法的复制型高速缓冲存储器件。该装置包括单字存储装置，用于当进行数据写入的存取时，在数据存储装置中存储所选数据的单字，该单字位于与处理器地址对应的数据存储装置中的地址处 ; 以及复制存储器装置，用于将取代的数据与其他数据一起恢复，取代的数据与其一起形成一个块，使得该块可以在数据写入过程发生之前被重新组织成其初始状态。该设备可以替代地包括地址锁存装置，用于当由处理器访问用于数据写入处理时，延迟处理器地址从处理器传输到数据存储器装置预定数量的处理周期; 以及数据锁存装置，用于当由处理器访问用于数据写入处理时，将处理器数据从处理器传输到数据存储器装置预定数量的处理周期。

2. 发明授权

US4992977A Cache memory device constituting a memory device used in a computer 失效
标题翻译：构成计算机中使用的存储装置的高速缓存存储装置
公开(公告)号：US4992977A
公开(公告)日：1991-02-12
申请号：US173296
申请日：1988-03-25
申请人： Tsukasa Matoba , Takeshi Aikawa , Ken-ichi Maeda , Mitsuo Saito , Mitsuyoshi Okamura
发明人： Tsukasa Matoba , Takeshi Aikawa , Ken-ichi Maeda , Mitsuo Saito , Mitsuyoshi Okamura
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3812 , G06F12/0804 , G06F12/0848
摘要： A cache memory device comprises a data cache memory, an instruction cache memory, an instruction code area change detector, and an instruction code change processor. The instruction code area change detector decides whether writing access to the data cache memory by the processor is to a data area or to an instruction area of a main memory. The instruction code change processor passes the data cache memory to perform direct writing into the main memory when the writing access is to the instruction area, and, when data for a processor address is cached in a tag section of the instruction cache memory, invalidates the effective flag of the tag section.
摘要翻译：高速缓冲存储器装置包括数据高速缓存存储器，指令高速缓存存储器，指令代码区域改变检测器和指令代码改变处理器。指令代码区域改变检测器决定处理器对数据高速缓冲存储器的写入写入是到数据区还是主存储器的指令区。当写入访问指令区时，指令代码变更处理器通过数据高速缓冲存储器来执行直接写入主存储器，并且当处理器地址的数据被缓存在指令高速缓存存储器的标签部分中时，使标签部分的有效标志。

3. 发明授权

US5021993A Device for saving and restoring register information 失效
标题翻译：保存和恢复注册信息的设备
公开(公告)号：US5021993A
公开(公告)日：1991-06-04
申请号：US175224
申请日：1988-03-30
申请人： Tsukasa Matoba , Takeshi Aikawa , Mitsuyoshi Okamura , Ken-ichi Maeda , Mitsuo Saito
发明人： Tsukasa Matoba , Takeshi Aikawa , Mitsuyoshi Okamura , Ken-ichi Maeda , Mitsuo Saito
IPC分类号： G06F9/30 , G06F9/38 , G06F9/42 , G06F9/46 , G06F9/48 , G11C7/10
CPC分类号： G06F9/30189 , G06F9/30116 , G06F9/30123 , G06F9/4426 , G06F9/462 , G11C7/1006
摘要： Each register of an internal register unit of a microprocessor has a pair of register cells consisting of first and second cells having the same register address. When one of these cells is selected, the other cell non-selected serves as a "back-up cell" for the selected cell. Each register of the register unit has a flag bit for storing a selector flag representing which cell of the pair of cells of the register is currently selected, and a flag bit for storing a change flag representing whether register information of the register is rewritten after a selected cell is changed between the first and second cells of the register. When the register information is stored in one of the pair of cells currently being selected of a certain register and is to be rewritten with another new information, the other cell of the register is selected to store the new information therein. The original register information is held in the first cell, thereby eliminating necessity of saving the original register information to a main memory at this stage. When the original register information is required again, the original register information can be rapidly restored, by only selecting the first cell again, in the corresponding register without executing save/restore processing between the register unit and the main memory.

4. 发明授权

US4945510A Register device 失效
标题翻译：注册设备
公开(公告)号：US4945510A
公开(公告)日：1990-07-31
申请号：US133737
申请日：1987-12-16
申请人： Ken-ichi Maeda , Mitsuo Saito , Takeshi Aikawa , Tsukasa Matoba , Mitsuyoshi Okamura
发明人： Ken-ichi Maeda , Mitsuo Saito , Takeshi Aikawa , Tsukasa Matoba , Mitsuyoshi Okamura
IPC分类号： G06F9/34 , G06F9/42 , G06F9/46
CPC分类号： G06F9/30116 , G06F9/4426 , G06F9/462
摘要： A register device includes a register set group, a switching control unit, a write control unit, a write flag memory unit, and a read control unit. The register set group consists of a plurality of register sets each constituted by a plurality of registers. The switching control unit selects a register set to be used in processing from the register set group in response to a saving/recovery instruction. The write control unit writes data in registers of the register set selected by the switching control unit in response to a write instruction. A write flag representing whether data is written in each of the registers is held by the write flag memory unit. The read control unit determines, in response to a read instruction, a register in which data is written most recently of a plurality of registers corresponding to each other between the register sets with reference to the write flags, thereby reading out data from the register.

5. 发明授权

US5594884A Cache memory system having a plurality of ports 失效
标题翻译：具有多个端口的高速缓冲存储器系统
公开(公告)号：US5594884A
公开(公告)日：1997-01-14
申请号：US170766
申请日：1993-12-21
申请人： Tsukasa Matoba , Hiroyuki Satou
发明人： Tsukasa Matoba , Hiroyuki Satou
IPC分类号： G06F9/32 , G06F9/38 , G06F12/08
CPC分类号： G06F9/3804 , G06F12/0853 , G06F12/0859
摘要： An instruction cache and a data cache are formed with a 2-port structure, the first port of the instruction cache is exclusively used for readout of the contiguous instruction, and the second port thereof is exclusively used for readout of the branched instruction when the conditional branch instruction is executed. With this construction, two instructions which may be executed can be simultaneously fetched irrespective of whether the branch of the conditional branch instruction is taken or untaken, thereby making it possible to enhance the CPU performance. Further, in the 2-port data cache, time for the cache refill process can be reduced by means of the contiguous data transfer and non-cacheable access.
摘要翻译：以2端口结构形成指令高速缓存和数据高速缓存，指令高速缓存的第一端口专用于连续指令的读出，其第二端口专门用于当有条件的分支指令被执行。利用这种结构，可以同时取出可以执行的两个指令，而不管采取或不采取条件转移指令的分支，从而可以提高CPU性能。此外，在2端口数据高速缓存中，可以通过连续数据传输和不可缓存访问来减少高速缓存重新填充处理的时间。

6. 发明授权

US5918069A System for simultaneously writing back cached data via first bus and transferring cached data to second bus when read request is cached and dirty 失效
标题翻译：用于通过第一总线同时写回缓存数据的系统，并且读取请求被缓存并脏时将缓存数据传送到第二总线
公开(公告)号：US5918069A
公开(公告)日：1999-06-29
申请号：US806686
申请日：1997-02-26
申请人： Tsukasa Matoba
发明人： Tsukasa Matoba
IPC分类号： G06F13/36 , G06F12/08 , G06F13/16
CPC分类号： G06F12/0835
摘要： A bus bridge mutually connects a CPU bus to which a CPU and a corresponding cache memory having a write-back scheme are coupled, an I/O bus to which a bus master is coupled, and a main memory which is commonly accessed through the CPU bus or I/O bus. In response to an access request from the bus master to the main memory, a cache snooping section snoops a cache memory to see whether an address in the access request satisfies a cache hit or miss, and data corresponding to the address is dirty or clear. In response to a snooping result by the cache snooping section indicating that the cache hit has occurred and the data is dirty, a write-back control section writes back the data from the cache memory in the main memory. In the case where the access request indicates a read request, a data bypass section directly transfers the data from the cache memory onto the I/O bus while the write-back control section performs writing back. With this processing, data read processing from the main memory need not wait for completion of write-back processing with respect to the main memory. Therefore, even if a cache write-back operation is performed in response to a main memory access request from the bus master, the main memory access operation can be performed at a high speed.
摘要翻译：一个总线桥连接一个CPU总线，一个CPU和一个具有回写方案的对应高速缓冲存储器被耦合到一个总线主机耦合的I / O总线，以及一个通过CPU共同访问的主存储器总线或I / O总线。响应于从总线主机到主存储器的访问请求，高速缓存监听部分窥探缓存存储器以查看访问请求中的地址是否满足高速缓存命中或丢失，并且对应于该地址的数据是脏的或清除的。响应于高速缓存窥探部分的窥探结果指示高速缓存命中已经发生并且数据是脏的，回写控制部分将来自高速缓冲存储器的数据写回到主存储器中。在访问请求指示读取请求的情况下，数据旁路部分在写回控制部分执行写回时将数据从高速缓冲存储器直接传送到I / O总线。通过该处理，来自主存储器的数据读取处理不需要等待相对于主存储器的回写处理的完成。因此，即使响应于来自总线主机的主存储器访问请求执行高速缓存回写操作，也可以高速执行主存储器访问操作。

7. 发明申请

US20120329392A1 CONTENT DATA DISTRIBUTION SYSTEM, CONTENT DATA DELIVERY METHOD, AND SEMICONDUCTOR DEVICE 有权
标题翻译：内容数据分发系统，内容数据传送方法和半导体器件
公开(公告)号：US20120329392A1
公开(公告)日：2012-12-27
申请号：US13425919
申请日：2012-03-21
申请人： Tsukasa Matoba , Shinichi Matsukawa , Akihiro Kasahara , Hiroyuki Sakamoto
发明人： Tsukasa Matoba , Shinichi Matsukawa , Akihiro Kasahara , Hiroyuki Sakamoto
IPC分类号： H04B5/00
CPC分类号： H04B5/02 , H04B5/0056
摘要： In this content data delivery method, content data is transmitted from a content server to a first semiconductor device through a network. Then, the content data, content ID identifying the content data, and route data showing a route through which the content data is transmitted are transmitted from the first semiconductor device to a second semiconductor device using close-proximity wireless communication. Thereafter, the content ID and the route data are transmitted from the second semiconductor device to the content server. In addition, based on the route data, a reward corresponding to the content ID is calculated for the first semiconductor device, and the reward is provided to the first semiconductor device.
摘要翻译：在该内容数据传送方法中，内容数据通过网络从内容服务器发送到第一半导体装置。然后，使用近距离无线通信，将从内容数据，识别内容数据的内容ID和表示通过其发送内容数据的路径的路线数据从第一半导体装置发送到第二半导体装置。此后，将内容ID和路线数据从第二半导体装置发送到内容服务器。此外，基于路线数据，计算与第一半导体装置对应的内容ID的奖励，并向第一半导体装置提供奖励。

8. 发明授权

US06678841B1 Function test support system and function test support method and hardware description model 失效
标题翻译：功能测试支持系统和功能测试支持方法和硬件描述模型
公开(公告)号：US06678841B1
公开(公告)日：2004-01-13
申请号：US09662229
申请日：2000-09-14
申请人： Yuuichi Kurosawa , Naohiko Okamoto , Koichi Nishide , Tsukasa Matoba
发明人： Yuuichi Kurosawa , Naohiko Okamoto , Koichi Nishide , Tsukasa Matoba
IPC分类号： G06F1100
CPC分类号： G06F11/261 , G06F17/5022
摘要： A statement is embedded in a description of a circuit for design in hardware description language stored in a function description storage section, the above statement outputting messages that test items have been tested according to a procedure stored in a package storage section. A function simulation executing section executes simulations to store the above messages in a message storage section. A report output section determines every test whether all the test items have been tested or not, based on messages stored in a message storage section, and data denoting a correspondence relationship between test vector names stored in a test data storage section and test items which are tested according to the above messages and outputs report of the determination results.
摘要翻译：在存储在功能描述存储部分中的硬件描述语言的设计用电路的描述中嵌入了语句，上述语句输出已经根据存储在包存储部分中的过程来测试测试项目的消息。功能模拟执行部执行模拟以将上述消息存储在消息存储部中。报告输出部分基于存储在消息存储部分中的消息，以及表示存储在测试数据存储部分中的测试向量名称与测试项目之间的对应关系的数据，确定每个测试是否已经测试了所有测试项目根据上述消息进行测试，并输出确定结果的报告。

9. 发明授权

US5906000A Computer with a cache controller and cache memory with a priority table and priority levels 失效
标题翻译：具有高速缓存控制器和具有优先级和优先级的高速缓存的计算机
公开(公告)号：US5906000A
公开(公告)日：1999-05-18
申请号：US802840
申请日：1997-02-18
申请人： Yuichi Abe , Tsukasa Matoba
发明人： Yuichi Abe , Tsukasa Matoba
IPC分类号： G06F12/08 , G06F12/12 , G06F12/00
CPC分类号： G06F12/122 , G06F12/0888 , G06F12/126
摘要： A computer system according to the present invention comprises a processor, a priority table for storing an address indicative of the original location of each of data items to be read by the processor, and a priority corresponding to the frequency of access by the processor to read each of the data items, a cache memory for storing, in units of cache blocks, part of the data items to be read by the processor, the cache memory having a tag which stores an address and a priority corresponding to each of the data items, and a controller including means for obtaining, when a cache miss has occurred, a priority corresponding to data whose reading is requested by the processor, by referring to the priority table and using an address included in the data-reading request of the processor, and means for comparing the obtained priority with a priority of data stored in a predetermined cache block in the cache memory, thereby to determine whether or not data replacement should be performed in the predetermined cache block.
摘要翻译：根据本发明的计算机系统包括处理器，用于存储指示要由处理器读取的每个数据项的原始位置的地址的优先级表以及处理器读取的访问频率的优先级每个数据项，用于以高速缓存块为单位存储由处理器读取的一部分数据项的高速缓冲存储器，高速缓冲存储器具有存储与每个数据项对应的地址和优先级的标签以及控制器，包括用于当发生高速缓存未命中时，通过参考优先级表并使用包括在处理器的数据读取请求中的地址来获得与由处理器请求读取的数据相对应的优先级的装置，以及用于将所获得的优先级与存储在高速缓存存储器中的预定高速缓存块中的数据的优先级进行比较的装置，从而确定是否应在th中执行数据替换 e预定的高速缓存块。

10. 发明授权

US5878251A Computer system and stop clock signal control method for use in the system 失效
标题翻译：系统中使用的计算机系统和停止时钟信号控制方法
公开(公告)号：US5878251A
公开(公告)日：1999-03-02
申请号：US808415
申请日：1997-02-28
申请人： Yuko Hagiwara , Tsukasa Matoba
发明人： Yuko Hagiwara , Tsukasa Matoba
IPC分类号： G06F15/02 , G06F1/04 , G06F1/32
CPC分类号： G06F1/3237 , G06F1/3203 , Y02B60/1221
摘要： In the interval stop clock mode, the stop clock generating circuit in the system controller generates a stop clock signal that alternates between the active state and the inactive state and supplies the signal to the CPU. This causes the CPU to alternate between a state where the CPU is stopped from executing an instruction and an instruction executable state. In such a computer system, an interrupt type sensing circuit senses various interrupt request signals generated in the system and determines the type of each interrupt request. A stop clock temporary stopping circuit controls the stop clock generating circuit so as to bring the stop clock signal in the inactive state for the period of time specified by the timer value stored in the register corresponding to the determined type of the interrupt request. With this configuration, the performance of the CPU is prevented from falling off in a case where a load is exerted on the CPU as a result of a hardware interrupt to the CPU having occurred in the interval stop clock mode.
摘要翻译：在间隔停止时钟模式中，系统控制器中的停止时钟产生电路产生在活动状态和非活动状态之间交替的停止时钟信号，并将信号提供给CPU。这使得CPU在CPU停止执行指令的状态和指令可执行状态之间交替。在这种计算机系统中，中断型感测电路感测在系统中产生的各种中断请求信号，并确定每个中断请求的类型。停止时钟暂停电路控制停止时钟产生电路，以使停止时钟信号处于非活动状态，该时间段由存储在对应于所确定的中断请求类型的寄存器中的定时器值指定的时间段内。通过这种配置，由于在间隔停止时钟模式中发生CPU的硬件中断，在CPU上施加负载的情况下，防止CPU的性能下降。

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