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1. 发明授权

US4665482A Data multiplex control facility 失效
标题翻译：数据复用控制设备
公开(公告)号：US4665482A
公开(公告)日：1987-05-12
申请号：US503963
申请日：1983-06-13
申请人： Thomas L. Murray, Jr. , James W. Stonier , Gary J. Goss , Thomas O. Holtey
发明人： Thomas L. Murray, Jr. , James W. Stonier , Gary J. Goss , Thomas O. Holtey
IPC分类号： G06F13/28 , G06F15/167 , G06F3/00 , G06F13/00
CPC分类号： G06F15/167 , G06F13/285
摘要： A data processing system includes a central processing unit (CPU), an input/output microprocessor, a main memory and a number of mass storage controllers. A block of information is transferred between one of the mass storage controllers and main memory during data multiplex control (DMC) cycles. The CPU includes registers which store the address of main memory into which the next data byte is written or read from and the range indicating the number of data bytes remaining to be transferred. Prior to a DMC cycle the CPU stores address and range information in a mailbox location in an I/O RAM and the I/O microprocessor transfers that information to channel table locations in the I/O RAM. For a DMC operation, the I/O microprocessor transfers the address and range information to the mailbox location and transfers the mass storage information to the mass storage controller. It signals a CPU interrupt and issues a read or write order to the mass storage controller. The CPU then retrieves the address and range information from the mailbox location and initiates a DMC cycle.
摘要翻译：数据处理系统包括中央处理单元（CPU），输入/输出微处理器，主存储器和多个大容量存储控制器。在数据多路复用控制（DMC）周期期间，一块信息在大容量存储控制器和主存储器之间传送。 CPU包括存储下一个数据字节被写入或读取的主存储器的地址的寄存器以及指示待传送的数据字节数的范围。在DMC循环之前，CPU将地址和范围信息存储在I / O RAM中的邮箱位置，I / O微处理器将该信息传输到I / O RAM中的通道表位置。对于DMC操作，I / O微处理器将地址和范围信息传送到邮箱位置，并将大容量存储信息传输到大容量存储控制器。它发出CPU中断信号，向大容量存储控制器发出读或写命令。 CPU然后从邮箱位置检索地址和范围信息，并启动DMC循环。

2. 发明授权

US4665481A Speeding up the response time of the direct multiplex control transfer facility 失效
标题翻译：加快直接多路复用控制传输设施的响应时间
公开(公告)号：US4665481A
公开(公告)日：1987-05-12
申请号：US503962
申请日：1983-06-13
申请人： James W. Stonier , Thomas L. Murray, Jr. , Gary J. Goss , Thomas O. Holtey
发明人： James W. Stonier , Thomas L. Murray, Jr. , Gary J. Goss , Thomas O. Holtey
IPC分类号： G06F13/28 , G06F3/00 , G06F13/00
CPC分类号： G06F13/285
摘要： A microprogrammed data processing system includes a central processing unit (CPU), a main memory and a number of mass storage controllers. A block of information is transferred between main memory and one of the mass storage controllers during data multiplex control (DMC) cycles. The main memory stores 2 data bytes in each word location. An input/output RAM stores channel number signals for identifying mass storage controllers. An I/O microprocessor addresses the I/O RAM to read the channel number signals onto the system bus, and a mass storage controller coupled to the system bus responds to the channel number signals to generate a read/write signal. The system responds to a request signal, the read/write signal and a signal indicative of a left or right bit of an addressed location in main memory to generate a plurality of data request signals. A read only memory is addressed in response to the data request signals to read out a plurality of microprograms for processing the data.
摘要翻译：微程序数据处理系统包括中央处理单元（CPU），主存储器和多个大容量存储控制器。在数据多路复用控制（DMC）周期期间，一块信息在主存储器和大容量存储控制器之一之间传送。主存储器在每个字位置存储2个数据字节。输入/输出RAM存储用于识别大容量存储控制器的通道号信号。 I / O微处理器将I / O RAM寻址到系统总线上的通道号信号，耦合到系统总线的大容量存储控制器响应信道号信号以产生读/写信号。系统响应请求信号，读/写信号和指示主存储器中寻址位置的左或右位的信号，以产生多个数据请求信号。响应于数据请求信号寻址只读存储器以读出用于处理数据的多个微程序。

3. 发明授权

US4799145A Facility for passing data used by one operating system to a replacement operating system 失效
标题翻译：将一个操作系统使用的数据传递到更换操作系统的设施
公开(公告)号：US4799145A
公开(公告)日：1989-01-17
申请号：US099698
申请日：1987-09-21
申请人： Gary J. Goss , Thomas S. Hirsch , Thomas O. Holtey
发明人： Gary J. Goss , Thomas S. Hirsch , Thomas O. Holtey
IPC分类号： G06F9/445 , G06F9/46 , G06F9/48 , G06F15/00 , G06F9/00
CPC分类号： G06F9/4843 , G06F9/4406 , G06F9/54
摘要： A computer system includes a first processor with main memory, an input/output processor with associated memory and an archival memory. Prior to reloading a new operating system from archival memory into the main memory, information such as timer information is stored in the input/output memory. The input/output memory continues to update the timer information until the second operating system is bootstrap loaded into the main memory. The timer and other information may then be returned to the first processor and main memory for use by the second operating system.
摘要翻译：计算机系统包括具有主存储器的第一处理器，具有相关存储器的输入/输出处理器和档案存储器。在将新的操作系统从归档存储器重新加载到主存储器之前，诸如定时器信息的信息被存储在输入/输出存储器中。输入/输出存储器继续更新定时器信息，直到第二个操作系统被引导加载到主存储器中。然后可以将定时器和其他信息返回到第一处理器和主存储器以供第二操作系统使用。

4. 发明授权

US4703322A Variable loadable character generator 失效
标题翻译：可变负载字符发生器
公开(公告)号：US4703322A
公开(公告)日：1987-10-27
申请号：US946663
申请日：1987-01-05
申请人： Gary J. Goss , Thomas O. Holtey , James C. Siwik
发明人： Gary J. Goss , Thomas O. Holtey , James C. Siwik
IPC分类号： G09G5/22 , G09G1/16
CPC分类号： G09G5/225
摘要： A Loadable Character Generator whose operation can be changed to suit various needs, such as foreign language requirements, without hardware change and with minimum hardware. The character generator translates the character code of a character to be displayed to the dot pattern for that particular character, utilizing a minimum of hardware. The loadable character generator of the invention replaces the ROM/PROM by a RAM utilizing 2K and 8 RAM memories, a 4K by 8 memory, 4 MUX chips, and a Motorola 6845 CRT Controller with various registers and is loaded through the attribute buffer.
摘要翻译：一种可加载字符发生器，其操作可以根据不同的需求进行更改，如外语要求，无需硬件更换和最少的硬件。字符发生器使用最少的硬件将要显示的字符的字符代码转换为该特定字符的点阵图形。本发明的可加载字符发生器通过RAM利用2K和8RAM存储器，4K×8存储器，4MUX芯片和具有各种寄存器的Motorola 6845 CRT控制器来代替ROM / PROM，并通过属性缓冲器加载。

5. 发明授权

US4651329A Digital decode logic for converting successive binary zero pulses having opposite polarity to a stream of data pulses 失效
标题翻译：用于将具有相反极性的连续二进制零脉冲转换为数据脉冲流的数字解码逻辑
公开(公告)号：US4651329A
公开(公告)日：1987-03-17
申请号：US568933
申请日：1984-01-10
申请人： Gary J. Goss , Robert G. H. Moles , Randall D. Hinrichs , Thomas O. Holtey
发明人： Gary J. Goss , Robert G. H. Moles , Randall D. Hinrichs , Thomas O. Holtey
IPC分类号： H04L1/00 , H04L7/033 , H04L25/49 , H03K9/00
CPC分类号： H04L7/0331 , H04L1/0083 , H04L25/4925
摘要： An apparatus for decoding data wherein only binary ZEROs are received as electronic pulses, each pulse alternating in opposite directions and wherein binary ONEs require no pulse.The apparatus includes logic for receiving the negative and positive binary ZERO pulses, retiming the pulses and generating a positive pulse for each binary ZERO pulse. The positive pulse is retimed to a pair of complementary pulses and applied to a receiving device, typically a universal synchronous/asynchronous receiver transmitter (USART).
摘要翻译：一种用于解码数据的装置，其中仅二进制ZERO被接收为电子脉冲，每个脉冲在相反方向上交替，并且其中二进制1不需要脉冲。该装置包括用于接收负和正二进制ZERO脉冲的逻辑，重新定时脉冲并为每个二进制零脉冲产生正脉冲。正脉冲重新定时到一对互补脉冲，并施加到接收设备，通常是通用同步/异步接收机发射机（USART）。

6. 发明授权

US4757470A Pattern generation for a graphics display 失效
标题翻译：图形显示的图案生成
公开(公告)号：US4757470A
公开(公告)日：1988-07-12
申请号：US68701
申请日：1987-07-01
申请人： Kenneth E. Bruce , Thomas O. Holtey , Gary J. Goss
发明人： Kenneth E. Bruce , Thomas O. Holtey , Gary J. Goss
IPC分类号： G09G5/393 , G06F3/14
CPC分类号： G09G5/393
摘要： A display subsystem having a graphics capability includes a bit map memory for storing bits, each bit representing a displayed pixel. A read only memory stores words, each word representative of a pixel of a selected pattern which is used to fill out an area of the display thereby clearly identifying adjacent areas of the display to the operator. The selected patterns are displayed in a REPLACE, an OR or an EXCLUSIVE OR mode of operation.
摘要翻译：具有图形能力的显示子系统包括用于存储位的位图存储器，每个位表示显示的像素。只读存储器存储字，表示所选图案的像素的每个字用于填充显示区域，从而将显示器的相邻区域清楚地识别给操作者。选择的模式以更新，OR或EXCLUSIVE或操作模式显示。

7. 发明授权

US4683466A Multiple color generation on a display 失效
标题翻译：在显示器上进行多种颜色生成
公开(公告)号：US4683466A
公开(公告)日：1987-07-28
申请号：US681539
申请日：1984-12-14
申请人： Thomas O. Holtey , Kenneth E. Bruce , Gary J. Goss
发明人： Thomas O. Holtey , Kenneth E. Bruce , Gary J. Goss
IPC分类号： G09G5/02 , G09G1/16 , G09G1/28
CPC分类号： G09G5/022
摘要： A color display graphics system includes three bit map memories for storing bits representing red, green and blue colors respectively. Combinations of bits from the same address locations of each bit map memory display a pixel which could be any one of eight colors: black, blue, green, cyan, red, magenta, yellow or white. A read only memory (ROM) stores patterns made up of sixteen bits in a four-by-four matrix for each of the red, green and blue colors. The 16-bit matrices are stored in their respective bit map memories for subsequent color display. Combinations of matrices may be used to show shades of the above eight colors and the mixing of any of those shades.
摘要翻译：彩色显示图形系统包括三个位图存储器，用于分别存储表示红色，绿色和蓝色颜色的位。来自每个位图存储器的相同地址位置的位的组合显示可以是八种颜色中的任何一种的像素：黑色，蓝色，绿色，青色，红色，品红色，黄色或白色。只读存储器（ROM）存储由红色，绿色和蓝色颜色中的每一个的四乘四个矩阵组成的十六位的图案。 16位矩阵存储在其各自的位图存储器中用于随后的彩色显示。可以使用矩阵的组合来显示上述八种颜色的阴影和任何这些阴影的混合。

8. 发明授权

US4542517A Digital serial interface with encode logic for transmission 失效
标题翻译：数字串行接口，带编码逻辑传输
公开(公告)号：US4542517A
公开(公告)日：1985-09-17
申请号：US304755
申请日：1981-09-23
申请人： Gary J. Goss , Robert G. H. Moles , Randall D. Hinrichs , Thomas O. Holtey
发明人： Gary J. Goss , Robert G. H. Moles , Randall D. Hinrichs , Thomas O. Holtey
IPC分类号： G06F13/42 , H04L7/02 , H04L7/033 , H04L25/49
CPC分类号： H04L7/0066 , G06F13/4221 , H04L25/4925 , H04L7/0331
摘要： An apparatus for encoding data for serial transmission wherein only logic ZEROs are transmitted as electronic pulses, each pulse alternating in opposite direction and wherein logic ONEs require no pulse.
摘要翻译：一种用于串行传输的数据编码装置，其中只有逻辑ZERO作为电子脉冲发送，每个脉冲以相反方向交替，其中逻辑1不需要脉冲。

9. 发明授权

US4494186A Automatic data steering and data formatting mechanism 失效
标题翻译：自动数据转向和数据格式化机制
公开(公告)号：US4494186A
公开(公告)日：1985-01-15
申请号：US286444
申请日：1981-07-24
申请人： Gary J. Goss , Richard P. Kelly , Thomas L. Murray, Jr.
发明人： Gary J. Goss , Richard P. Kelly , Thomas L. Murray, Jr.
IPC分类号： G06F5/00 , G06F13/38 , G06F3/00
CPC分类号： G06F13/387 , G06F5/00
摘要： In a data processing system having a plurality of units coupled for the transfer of information therebetween over a common electrical bus or for transferring information via a communication channel to other data processing systems during asynchronously generated information bus transfer cycles, an apparatus exists for reformatting data for transfer over the common electrical bus or via the communication channel. The apparatus is comprised of an eight-way multiplexer responsive to control bits for selecting one of eight different formats during write or read operations to or from a memory. Additionally, during read operations, the apparatus transfers a return address from a unit requesting information to the address bus so that data read from memory may be transferred to the requesting device. The formatting control bit is similarly reformatted from the data bus to the address bus bit.
摘要翻译：在具有多个单元的数据处理系统中，所述多个单元耦合用于通过公共电气总线传递信息，或者用于在异步生成的信息总线传送周期期间经由通信信道将信息传送到其他数据处理系统，存在用于重新格式化数据的设备通过公共电气总线或通过通信信道进行传输。该装置包括一个八路复用器，响应于控制位，用于在从存储器写入或读取操作期间选择八种不同格式之一。此外，在读取操作期间，设备将请求信息的单元的返回地址传送到地址总线，从而可以将从存储器读取的数据传送到请求设备。格式控制位类似地从数据总线重新格式化为地址总线位。

10. 发明授权

US4312068A Parallel generation of serial cyclic redundancy check 失效
标题翻译：并行生成串行循环冗余校验
公开(公告)号：US4312068A
公开(公告)日：1982-01-19
申请号：US884465
申请日：1978-03-07
申请人： Gary J. Goss , Robert C. Miller
发明人： Gary J. Goss , Robert C. Miller
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： H03M13/09
摘要： A method and apparatus for assuring the accuracy of data received by any device in a computer system from any other device in the same computer system or from another computer system. The existing hardware of a computer system is utilized to generate a cyclic redundant check character each time a unit of data is transmitted. The cyclic redundant check character is concatenated to the right of such data transmitted. Each time that the particular data is received, the check character and the data with which it is associated, is again manipulated in the same manner as in generating the check character. If the data received is the same as the data transmitted, the result of such manipulation is zero.
摘要翻译：一种用于确保计算机系统中的任何设备从同一计算机系统中的任何其他设备或另一计算机系统接收的数据的准确性的方法和装置。每当发送数据单元时，利用计算机系统的现有硬件来生成循环冗余校验字符。循环冗余校验字符连接在发送的数据的右侧。每当接收到特定数据时，与生成检查字符相同的方式再次操作检查字符和与其相关联的数据。如果接收的数据与发送的数据相同，则这种操作的结果为零。

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