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1. 发明申请

US20070236276A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND SOURCE VOLTAGE/SUBSTRATE BIAS CONTROL CIRCUIT 失效
标题翻译：半导体集成电路和源极电压/基极偏置控制电路
公开(公告)号：US20070236276A1
公开(公告)日：2007-10-11
申请号：US11764605
申请日：2007-06-18
申请人： Tetsuya FUJITA , Mototsugu Hamada , Hiroyuki Hara
发明人： Tetsuya FUJITA , Mototsugu Hamada , Hiroyuki Hara
IPC分类号： H01L29/94
CPC分类号： G05F3/205
摘要： This disclosure concerns a semiconductor integrated circuit that includes a semiconductor substrate, a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other, a plurality of MOS transistors formed in the well regions and a substrate bias generator that applies substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.
摘要翻译：本公开涉及一种半导体集成电路，其包括半导体衬底，形成在半导体衬底的一个表面上并彼此电隔离的多个阱区，形成在阱区中的多个MOS晶体管和衬底偏置发生器，其应用基于实际测量的阈值电压下的MOS晶体管的工艺衍生方差，使各个MOS晶体管的阈值电压与正常阈值电压一致，从而将衬底偏置到各个阱区。

2. 发明申请

US20060198198A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20060198198A1
公开(公告)日：2006-09-07
申请号：US11342617
申请日：2006-01-31
申请人： Tetsuya Fujita , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara , Shinichiro Shiratake
发明人： Tetsuya Fujita , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara , Shinichiro Shiratake
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C5/147
摘要： According to the present invention, there is provided a semiconductor integrated circuit comprising: a power controller which outputs a voltage select signal for selecting one of at least two types of voltages; a power supply voltage controller which generates and outputs a power supply voltage at an arbitrary voltage change rate on the basis of the voltage select signal; and a circuit portion which receives the power supply voltage and performs processing, wherein said circuit portion keeps operating while said power supply voltage controller is outputting the power supply voltage generated at the arbitrary voltage change rate.
摘要翻译：根据本发明，提供了一种半导体集成电路，包括：功率控制器，其输出用于选择至少两种类型的电压中的一种的电压选择信号; 电源电压控制器，其基于所述电压选择信号生成并输出任意电压变化率的电源电压; 以及电路部分，其接收电源电压并执行处理，其中所述电路部分在所述电源电压控制器输出以任意电压变化率产生的电源电压的情况下保持操作。

3. 发明授权

US07551019B2 Semiconductor integrated circuit and source voltage/substrate bias control circuit 失效
标题翻译：半导体集成电路和源极电压/衬底偏置控制电路
公开(公告)号：US07551019B2
公开(公告)日：2009-06-23
申请号：US11764605
申请日：2007-06-18
申请人： Tetsuya Fujita , Mototsugu Hamada , Hiroyuki Hara
发明人： Tetsuya Fujita , Mototsugu Hamada , Hiroyuki Hara
IPC分类号： G05F3/16 , H03L1/00
CPC分类号： G05F3/205
摘要： This disclosure concerns a semiconductor integrated circuit that includes a semiconductor substrate, a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other, a plurality of MOS transistors formed in the well regions and a substrate bias generator that applies substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.
摘要翻译：本公开涉及一种半导体集成电路，其包括半导体衬底，形成在半导体衬底的一个表面上并彼此电隔离的多个阱区，形成在阱区中的多个MOS晶体管和衬底偏置发生器，其应用基于实际测量的阈值电压下的MOS晶体管的工艺衍生方差，使各个MOS晶体管的阈值电压与正常阈值电压一致，从而将衬底偏置到各个阱区。

4. 发明授权

US07417489B2 Semiconductor integrated circuit having controller controlling the change rate of power voltage 有权
标题翻译：具有控制器控制电源电压变化率的半导体集成电路
公开(公告)号：US07417489B2
公开(公告)日：2008-08-26
申请号：US11342617
申请日：2006-01-31
申请人： Tetsuya Fujita , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara , Shinichiro Shiratake
发明人： Tetsuya Fujita , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara , Shinichiro Shiratake
IPC分类号： G05F1/10
CPC分类号： G11C5/147
摘要： A semiconductor integrated circuit comprising: a power controller which outputs a voltage select signal for selecting one of at least two types of voltages; a power supply voltage controller which generates and outputs a power supply voltage at an arbitrary voltage change rate on the basis of the voltage select signal; and a circuit portion which receives the power supply voltage and performs processing, wherein said circuit portion keeps operating while said power supply voltage controller is outputting the power supply voltage generated at the arbitrary voltage change rate.
摘要翻译：一种半导体集成电路，包括：功率控制器，其输出用于选择至少两种类型的电压中的一种的电压选择信号; 电源电压控制器，其基于所述电压选择信号生成并输出任意电压变化率的电源电压; 以及电路部分，其接收电源电压并执行处理，其中所述电路部分在所述电源电压控制器输出以任意电压变化率产生的电源电压的情况下保持操作。

5. 发明申请

US20050093611A1 Semiconductor integrated circuit and source voltage/substrate bias control circuit 有权
标题翻译：半导体集成电路和源极电压/衬底偏置控制电路
公开(公告)号：US20050093611A1
公开(公告)日：2005-05-05
申请号：US10899004
申请日：2004-07-27
申请人： Tetsuya Fujita , Mototsugu Hamada , Hiroyuki Hara
发明人： Tetsuya Fujita , Mototsugu Hamada , Hiroyuki Hara
IPC分类号： H01L27/04 , G05F3/20 , H01L21/822 , H01L21/8238 , H01L27/092 , H03K3/01 , H03K17/00
CPC分类号： G05F3/205
摘要： A semiconductor integrated circuit comprises a semiconductor substrate; a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other; a plurality of MOS transistors formed in the well regions; and a substrate bias generating circuit applying substrate biases to individual said well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.
摘要翻译：半导体集成电路包括半导体衬底; 多个阱区，形成在所述半导体衬底的一个表面上并彼此电隔离; 形成在所述阱区中的多个MOS晶体管; 以及衬底偏置产生电路，其基于实际测量的阈值电压下的MOS晶体管的工艺衍生方差将单独的所述阱区域施加衬底偏置，以使各MOS晶体管的阈值电压与正常阈值电压一致。

6. 发明申请

US20060061401A1 Semiconductor device adapted to minimize clock skew 有权
标题翻译：半导体器件适合于最小化时钟偏移
公开(公告)号：US20060061401A1
公开(公告)日：2006-03-23
申请号：US10990537
申请日：2004-11-18
申请人： Shinichiro Shiratake , Yukihito Oowaki , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara
发明人： Shinichiro Shiratake , Yukihito Oowaki , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： A first logic circuit has its supply voltage controlled. A second logic circuit operates in response to an external clock signal. An adjustment circuit includes a first delay circuit supplied with the external clock signal, and a detection circuit which detects a skew between timing of a first clock signal output from the first logic circuit and a second clock signal output from the second logic circuit section. The adjustment circuit adjusts the delay time of the first delay circuit according to the result of the detection by the detection circuit and applies an output signal of the first delay circuit to the first logic circuit as a third clock signal.
摘要翻译：第一个逻辑电路的电源电压被控制。第二逻辑电路响应于外部时钟信号而工作。调整电路包括提供有外部时钟信号的第一延迟电路和检测电路，其检测从第一逻辑电路输出的第一时钟信号的定时与从第二逻辑电路部分输出的第二时钟信号之间的偏差。调整电路根据检测电路的检测结果来调整第一延迟电路的延迟时间，并将第一延迟电路的输出信号作为第三时钟信号施加到第一逻辑电路。

7. 发明授权

US07236035B2 Semiconductor device adapted to minimize clock skew 有权
标题翻译：半导体器件适合于最小化时钟偏移
公开(公告)号：US07236035B2
公开(公告)日：2007-06-26
申请号：US10990537
申请日：2004-11-18
申请人： Shinichiro Shiratake , Yukihito Oowaki , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara
发明人： Shinichiro Shiratake , Yukihito Oowaki , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： A first logic circuit has its supply voltage controlled. A second logic circuit operates in response to an external clock signal. An adjustment circuit includes a first delay circuit supplied with the external clock signal, and a detection circuit which detects a skew between timing of a first clock signal output from the first logic circuit and a second clock signal output from the second logic circuit section. The adjustment circuit adjusts the delay time of the first delay circuit according to the result of the detection by the detection circuit and applies an output signal of the first delay circuit to the first logic circuit as a third clock signal.
摘要翻译：第一个逻辑电路的电源电压被控制。第二逻辑电路响应于外部时钟信号而工作。调整电路包括提供有外部时钟信号的第一延迟电路和检测电路，其检测从第一逻辑电路输出的第一时钟信号的定时与从第二逻辑电路部分输出的第二时钟信号之间的偏差。调整电路根据检测电路的检测结果来调整第一延迟电路的延迟时间，并将第一延迟电路的输出信号作为第三时钟信号施加到第一逻辑电路。

8. 发明申请

US20060271799A1 Semiconductor device and system 有权
标题翻译：半导体器件和系统
公开(公告)号：US20060271799A1
公开(公告)日：2006-11-30
申请号：US11216018
申请日：2005-09-01
申请人： Shinichiro Shiratake , Yukihito Oowaki , Hiroyuki Hara , Tetsuya Fujita , Fumitoshi Hatori , Masataka Matsui
发明人： Shinichiro Shiratake , Yukihito Oowaki , Hiroyuki Hara , Tetsuya Fujita , Fumitoshi Hatori , Masataka Matsui
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： According to the present invention, there is provided a semiconductor device comprising: a power supply circuit which receives an external power supply voltage supplied, and outputs an internal power supply voltage not higher than the external power supply voltage; a system module which receives the internal power supply voltage, and performs a predetermined operation; and a performance monitor circuit which measures a processing speed of said system module when the internal power supply voltage is applied, and, on the basis of the processing speed, outputs a first control signal which requests to set the external power supply voltage at a first level, and a second control signal which requests said power supply circuit to set the internal power supply voltage at a second level, wherein said power supply circuit outputs the internal power supply voltage having the second level on the basis of the second control signal applied thereto.
摘要翻译：根据本发明，提供了一种半导体器件，包括：电源电路，接收所提供的外部电源电压，并输出不高于外部电源电压的内部电源电压; 接收内部电源电压并执行预定操作的系统模块; 以及性能监视电路，其在施加所述内部电源电压时测量所述系统模块的处理速度，并且基于所述处理速度，输出请求将所述外部电源电压设置为第一的第一控制信号电平和第二控制信号，其请求所述电源电路将内部电源电压设定在第二电平，其中所述电源电路基于施加到其的第二控制信号输出具有第二电平的内部电源电压。

9. 发明授权

US07487370B2 Semiconductor device and system 有权
标题翻译：半导体器件和系统
公开(公告)号：US07487370B2
公开(公告)日：2009-02-03
申请号：US11216018
申请日：2005-09-01
申请人： Shinichiro Shiratake , Yukihito Oowaki , Hiroyuki Hara , Tetsuya Fujita , Fumitoshi Hatori , Masataka Matsui
发明人： Shinichiro Shiratake , Yukihito Oowaki , Hiroyuki Hara , Tetsuya Fujita , Fumitoshi Hatori , Masataka Matsui
IPC分类号： G06F1/00
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： According to the present invention, there is provided a semiconductor device including a power supply circuit which receives an external power supply voltage supplied, and outputs an internal power supply voltage not higher than the external power supply voltage; a system module which receives the internal power supply voltage, and performs a predetermined operation; and a performance monitor circuit which measures a processing speed of said system module when the internal power supply voltage is applied, and, on the basis of the processing speed, outputs a first control signal which requests to set the external power supply voltage at a first level, and a second control signal which requests said power supply circuit to set the internal power supply voltage at a second level. The power supply circuit outputs the internal power supply voltage having the second level on the basis of the second control signal applied thereto.
摘要翻译：根据本发明，提供了一种半导体器件，包括：电源电路，接收所提供的外部电源电压，并输出不高于外部电源电压的内部电源电压; 接收内部电源电压并执行预定操作的系统模块; 以及性能监视电路，其在施加所述内部电源电压时测量所述系统模块的处理速度，并且基于所述处理速度，输出请求将所述外部电源电压设置为第一的第一控制信号电平和第二控制信号，其请求所述电源电路将内部电源电压设定在第二电平。电源电路基于施加到其上的第二控制信号输出具有第二电平的内部电源电压。

10. 发明授权

US07245177B2 Semiconductor integrated circuit and source voltage/substrate bias control circuit 有权
标题翻译：半导体集成电路和源极电压/衬底偏置控制电路
公开(公告)号：US07245177B2
公开(公告)日：2007-07-17
申请号：US10899004
申请日：2004-07-27
申请人： Tetsuya Fujita , Motosugu Hamada , Hiroyuki Hara
发明人： Tetsuya Fujita , Motosugu Hamada , Hiroyuki Hara
IPC分类号： G05F3/24
CPC分类号： G05F3/205
摘要： This disclosure concerns semiconductor integrated circuit includes a semiconductor substrate; a plurality of well regions formed on one surface of the semiconductor substrate and electrically isolated from each other; a plurality of MOS transistors formed in the well regions; and a substrate bias generator applying substrate biases to the individual well regions based on actually measured process-derived variance of the MOS transistors in threshold voltage to bring the threshold voltages of the respective MOS transistors into conformity with a normal threshold voltage.
摘要翻译：本公开涉及半导体集成电路包括半导体衬底; 多个阱区，形成在所述半导体衬底的一个表面上并彼此电隔离; 形成在所述阱区中的多个MOS晶体管; 以及衬底偏置发生器，其基于实际测量的阈值电压下的MOS晶体管的工艺导出方差，将衬底偏压到各个阱区域，以使各个MOS晶体管的阈值电压与正常阈值电压一致。

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