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1. 发明授权

US5862403A Continuous data server apparatus and data transfer scheme enabling multiple simultaneous data accesses 失效
标题翻译：连续数据服务器设备和数据传输方案支持多次同时访问数据
公开(公告)号：US5862403A
公开(公告)日：1999-01-19
申请号：US603759
申请日：1996-02-16
申请人： Tatsunori Kanai , Shigehiro Asano , Takeshi Aikawa , Shinya Amano
发明人： Tatsunori Kanai , Shigehiro Asano , Takeshi Aikawa , Shinya Amano
IPC分类号： G06F3/06 , G06F11/10 , H04L12/54 , H04L12/861 , H04L12/883 , G06F15/02
CPC分类号： H04L12/5693 , G06F11/1076 , G06F11/1088 , G06F3/0601 , H04L49/90 , H04L49/9021 , H04L49/9047 , H04L49/9073 , G06F2003/0692
摘要： A continuous data server apparatus incorporating a plurality of buffer memory units for storing the continuous data read out by the data memory control units and to be given to the communication control unit, at least one buffer memory unit being provided dedicatedly for each combination of one data memory control unit group formed by at least one data memory control unit and one communication control unit group formed by at least one communication control unit. The apparatus may further incorporate a plurality of calculation units connected in series, where each calculation unit is connected between corresponding one data memory control unit group and at least one buffer memory unit, and carrying out a prescribed calculation processing. The continuous data can be arranged over a plurality of data memory control units in word units, such that the data memory control units read out the continuous data in block units, the buffer memory units store the continuous data in block units, and the communication control unit transfers the continuous data obtained by reading out data the buffer memory units sequentially in word units.
摘要翻译：一种连续数据服务器装置，其包括多个缓冲存储器单元，用于存储由数据存储器控制单元读出的连续数据，并被提供给通信控制单元，至少一个缓冲存储器单元专门为一个数据的每个组合提供由至少一个数据存储器控制单元形成的存储器控制单元组和由至少一个通信控制单元形成的一个通信控制单元组。该装置还可以包括串联连接的多个计算单元，其中每个计算单元连接在相应的一个数据存储器控制单元组和至少一个缓冲存储器单元之间，并执行规定的计算处理。连续数据可以以单位单位布置在多个数据存储器控制单元上，使得数据存储器控制单元以块为单位读出连续数据，缓冲存储器单元以块为单位存储连续数据，并且通信控制单元通过以字为单位顺序地读出缓冲存储器单元的数据而获得的连续数据。

2. 发明授权

US06611870B1 Server device and communication connection scheme using network interface processors 失效
标题翻译：使用网络接口处理器的服务器设备和通信连接方案
公开(公告)号：US06611870B1
公开(公告)日：2003-08-26
申请号：US09136513
申请日：1998-08-19
申请人： Shigehiro Asano , Tatsunori Kanai , Shinichi Kanno , Seiji Maeda
发明人： Shigehiro Asano , Tatsunori Kanai , Shinichi Kanno , Seiji Maeda
IPC分类号： G06F1516
CPC分类号： G06F13/385
摘要： A server device and a communication connection scheme capable of expanding the memory bandwidth and thereby expanding the power to transmit Web data to the network are disclosed. Network cards are detachably attached to a host machine (main machine). Each network card contains a processor, a memory, and a network interface unit, where data are transmitted to the network from a memory on the network card and the memory bandwidth expansion is realized by the presence of a plurality of network cards. In addition, using a memory of the network card as a cache, the load on the host machine is reduced by transmitting data from this memory to the network when the data exists on the memory and a certain condition is satisfied.
摘要翻译：公开了能够扩展存储器带宽并由此扩展将网络数据传输到网络的功能的服务器设备和通信连接方案。网卡可拆卸地连接到主机（主机）。每个网卡包含处理器，存储器和网络接口单元，其中数据从网卡上的存储器发送到网络，并且通过存在多个网卡来实现存储器带宽扩展。此外，使用网卡的存储器作为缓存，当数据存在于存储器上并且满足一定条件时，通过从该存储器向网络发送数据来减少主机上的负载。

3. 发明授权

US06327614B1 Network server device and file management system using cache associated with network interface processors for redirecting requested information between connection networks 失效
标题翻译：使用与网络接口处理器相关联的缓存的网络服务器设备和文件管理系统在连接网络之间重定向所请求的信息
公开(公告)号：US06327614B1
公开(公告)日：2001-12-04
申请号：US09154031
申请日：1998-09-16
申请人： Shigehiro Asano , Tatsunori Kanai , Shinichi Kanno , Seiji Maeda
发明人： Shigehiro Asano , Tatsunori Kanai , Shinichi Kanno , Seiji Maeda
IPC分类号： G06F15167
CPC分类号： G06F3/061 , G06F3/0658 , G06F3/0659 , G06F3/067 , H04L67/02 , H04L67/28 , H04L67/2814 , H04L67/2842 , H04L67/2895
摘要： A server device is formed by a plurality of network interface processors connected to a network, each network interface processor having a network interface local memory functioning as a cache memory for storing a part of server data and a network interface local processor, at least one storage interface processor connected with a storage device for storing the server data, and a connection network for connecting the network interface processors and the storage interface processor. In this server device, the network interface local processor of one network interface processor carries out a control processing such that a requested data stored In the network interface local memory of the one network Interface processor is transmitted to the network when a request received from the network at the one network interface processor satisfies a prescribed first condition, and the request is given to the storage interface processor via the connection network when the request satisfies a prescribed second condition and the requested data is transmitted to the network upon receiving the requested data returned from the storage interface processor to the one network interface processor via the connection network in response to the request.
摘要翻译：服务器设备由连接到网络的多个网络接口处理器形成，每个网络接口处理器具有用作存储服务器数据的一部分的高速缓存存储器的网络接口本地存储器和网络接口本地处理器，至少一个存储器与用于存储服务器数据的存储设备连接的接口处理器，以及用于连接网络接口处理器和存储接口处理器的连接网络。在该服务器装置中，一个网络接口处理器的网络接口本地处理器执行控制处理，使得当从网络接收到请求时，将存储在一个网络接口处理器的网络接口本地存储器中的所请求数据发送到网络在一个网络接口处理器满足规定的第一条件，并且当请求满足规定的第二条件时，经由连接网络将该请求提供给存储接口处理器，并且在接收到从所请求的数据返回时请求的数据被发送到网络所述存储接口处理器响应于所述请求经由所述连接网络连接到所述一个网络接口处理器。

4. 发明授权

US5996014A Distribution multimedia server system using shared disk arrays connected in a chain and having two ports each that are striped with digitalized video data 失效
标题翻译：分发多媒体服务器系统使用连接在链中的共享磁盘阵列，并具有两个端口，每个端口都带有数字化视频数据
公开(公告)号：US5996014A
公开(公告)日：1999-11-30
申请号：US959844
申请日：1997-10-29
申请人： Ikuo Uchihori , Shigehiro Asano , Masayuki Takakuwa , Tatsunori Kanai
发明人： Ikuo Uchihori , Shigehiro Asano , Masayuki Takakuwa , Tatsunori Kanai
IPC分类号： G06F3/06 , G06F13/00 , G06F15/16 , G11B19/02 , H04N21/218 , H04N21/2315
CPC分类号： H04N21/2182 , H04N21/222
摘要： The shared disk array which incorporates a plurality of disk apparatus storing the contents including the digitized video data and a plurality of element servers are connected to the shared channel network suitable for the multi-initiator architecture, whereby each of the element servers can physically share the shared disk array via the shared channel network. Further, each of the element servers is provided with the network interface suitable for the high-speed transmission and the band-width reservation, so that the contents stored in the shared disk array are read out in response to the request form the client, thus being output of the communication network via the network interface.
摘要翻译：包含存储包括数字化视频数据的内容的多个磁盘装置的共享磁盘阵列和多个元件服务器连接到适合于多启动器架构的共享信道网络，由此每个元件服务器可以物理共享共享磁盘阵列通过共享通道网络。此外，每个元件服务器设置有适于高速传输和带宽预留的网络接口，使得响应于客户端的请求读出存储在共享磁盘阵列中的内容，因此通过网络接口输出通信网络。

5. 发明申请

US20080162892A1 METHOD AND APPARATUS OF DISPLAYING BIT STREAM DATA, METHOD AND APPARATUS FOR GENERATING BIT STREAM DATA, AND STORAGE MEDIUM 失效
标题翻译：显示位流数据的方法和装置，用于生成位流数据的方法和装置以及存储介质
公开(公告)号：US20080162892A1
公开(公告)日：2008-07-03
申请号：US12041329
申请日：2008-03-03
申请人： Toru KAMBAYASHI , Tatsunori Kanai , Takeshi Saito , Hiroshi Yao , Shigeyasu Natsubori , Osamu Hori , Toshimitsu Kaneko , Toshihiro Morohoshi , Takahiro Harashima , Yoshinori Suzuki , Shigeru Oyanagi , Takeshi Aikawa
发明人： Toru KAMBAYASHI , Tatsunori Kanai , Takeshi Saito , Hiroshi Yao , Shigeyasu Natsubori , Osamu Hori , Toshimitsu Kaneko , Toshihiro Morohoshi , Takahiro Harashima , Yoshinori Suzuki , Shigeru Oyanagi , Takeshi Aikawa
IPC分类号： G06F9/30
CPC分类号： H04N21/262 , G06Q20/3678 , H04N5/4401 , H04N5/445 , H04N21/235 , H04N21/4305 , H04N21/4331 , H04N21/4334 , H04N21/4335 , H04N21/4348 , H04N21/435 , H04N21/4622 , H04N21/478 , H04N21/8166
摘要： According to a data display method, data having a program unit and instruction data for the program unit multiplexed on bit stream data is received. The program unit is extracted from the received data and is stored in a memory. The instruction data is extracted from the received data, and the program unit or part thereof specified by the instruction data is read from the memory and is executed. Then, the bit stream data and the execution result are displayed. This ensures smooth synchronization of reproduction of a bit stream with execution of an associated program and efficient use of resources.
摘要翻译：根据数据显示方法，接收具有程序单元的数据和用于在比特流数据上复用的程序单元的指令数据。从接收到的数据中提取程序单元并将其存储在存储器中。从接收的数据中提取指令数据，并且从存储器读取由指令数据指定的程序单元或其一部分，并执行。然后，显示比特流数据和执行结果。这确保了位流的再现与相关程序的执行和资源的有效利用的顺利同步。

6. 发明授权

US08006272B2 Method and apparatus of displaying bit stream data, method and apparatus for generating bit stream data, and storage medium 失效
标题翻译：显示比特流数据的方法和装置，用于产生比特流数据的方法和装置以及存储介质
公开(公告)号：US08006272B2
公开(公告)日：2011-08-23
申请号：US12041329
申请日：2008-03-03
申请人： Toru Kambayashi , Tatsunori Kanai , Takeshi Saito , Hiroshi Yao , Shigeyasu Natsubori , Osamu Hori , Toshimitsu Kaneko , Toshihiro Morohoshi , Takahiro Harashima , Yoshinori Suzuki , Shigeru Oyanagi , Takeshi Aikawa
发明人： Toru Kambayashi , Tatsunori Kanai , Takeshi Saito , Hiroshi Yao , Shigeyasu Natsubori , Osamu Hori , Toshimitsu Kaneko , Toshihiro Morohoshi , Takahiro Harashima , Yoshinori Suzuki , Shigeru Oyanagi , Takeshi Aikawa
IPC分类号： H04N7/20 , H04N7/16
CPC分类号： H04N21/262 , G06Q20/3678 , H04N5/4401 , H04N5/445 , H04N21/235 , H04N21/4305 , H04N21/4331 , H04N21/4334 , H04N21/4335 , H04N21/4348 , H04N21/435 , H04N21/4622 , H04N21/478 , H04N21/8166
摘要： According to a data display method, data having a program unit and instruction data for the program unit multiplexed on bit stream data is received. The program unit is extracted from the received data and is stored in a memory. The instruction data is extracted from the received data, and the program unit or part thereof specified by the instruction data is read from the memory and is executed. Then, the bit stream data and the execution result are displayed. This ensures smooth synchronization of reproduction of a bit stream with execution of an associated program and efficient use of resources.
摘要翻译：根据数据显示方法，接收具有程序单元的数据和用于在比特流数据上复用的程序单元的指令数据。从接收到的数据中提取程序单元并将其存储在存储器中。从接收的数据中提取指令数据，并且从存储器读取由指令数据指定的程序单元或其一部分，并执行。然后，显示比特流数据和执行结果。这确保了位流的再现与相关程序的执行和资源的有效利用的顺利同步。

7. 发明授权

US07458090B2 Method and apparatus of displaying bit stream data, method and apparatus for generating bit stream data, and storage medium 失效
标题翻译：显示比特流数据的方法和装置，用于产生比特流数据的方法和装置以及存储介质
公开(公告)号：US07458090B2
公开(公告)日：2008-11-25
申请号：US10247510
申请日：2002-09-20
申请人： Toru Kambayashi , Tatsunori Kanai , Takeshi Saito , Hiroshi Yao , Shigeyasu Natsubori , Osamu Hori , Toshimitsu Kaneko , Toshihiro Morohoshi , Takahiro Harashima , Yoshinori Suzuki , Shigeru Oyanagi , Takeshi Aikawa
发明人： Toru Kambayashi , Tatsunori Kanai , Takeshi Saito , Hiroshi Yao , Shigeyasu Natsubori , Osamu Hori , Toshimitsu Kaneko , Toshihiro Morohoshi , Takahiro Harashima , Yoshinori Suzuki , Shigeru Oyanagi , Takeshi Aikawa
IPC分类号： H04N7/20 , H04N7/16 , H04N7/00 , H04N5/92
CPC分类号： H04N21/262 , G06Q20/3678 , H04N5/4401 , H04N5/445 , H04N21/235 , H04N21/4305 , H04N21/4331 , H04N21/4334 , H04N21/4335 , H04N21/4348 , H04N21/435 , H04N21/4622 , H04N21/478 , H04N21/8166
摘要： According to a data display method, data having a program unit and instruction data for the program unit multiplexed on bit stream data is received. The program unit is extracted from the received data and is stored in a memory. The instruction data is extracted from the received data, and the program unit or part thereof specified by the instruction data is read from the memory and is executed. Then, the bit stream data and the execution result are displayed. This ensures smooth synchronization of reproduction of a bit stream with execution of an associated program and efficient use of resources.
摘要翻译：根据数据显示方法，接收具有程序单元的数据和用于在比特流数据上复用的程序单元的指令数据。从接收到的数据中提取程序单元并将其存储在存储器中。从接收的数据中提取指令数据，并且从存储器读取由指令数据指定的程序单元或其一部分，并执行。然后，显示比特流数据和执行结果。这确保了位流的再现与相关程序的执行和资源的有效利用的顺利同步。

8. 发明授权

US06473901B2 Method and apparatus of displaying bit stream data, method and apparatus for generating bit stream data, and storage medium 失效
标题翻译：显示比特流数据的方法和装置，用于产生比特流数据的方法和装置以及存储介质
公开(公告)号：US06473901B2
公开(公告)日：2002-10-29
申请号：US09096193
申请日：1998-06-12
申请人： Toru Kambayashi , Tatsunori Kanai , Takeshi Saito , Hiroshi Yao , Shigeyasu Natsubori , Osamu Hori , Toshimitsu Kaneko , Toshihiro Morohoshi , Takahiro Harashima , Yoshinori Suzuki , Shigeru Oyanagi , Takeshi Aikawa
发明人： Toru Kambayashi , Tatsunori Kanai , Takeshi Saito , Hiroshi Yao , Shigeyasu Natsubori , Osamu Hori , Toshimitsu Kaneko , Toshihiro Morohoshi , Takahiro Harashima , Yoshinori Suzuki , Shigeru Oyanagi , Takeshi Aikawa
IPC分类号： H04N720
CPC分类号： H04N21/262 , G06Q20/3678 , H04N5/4401 , H04N5/445 , H04N21/235 , H04N21/4305 , H04N21/4331 , H04N21/4334 , H04N21/4335 , H04N21/4348 , H04N21/435 , H04N21/4622 , H04N21/478 , H04N21/8166
摘要： According to a data display method, data having a program unit and instruction data for the program unit multiplexed on bit stream data is received. The program unit is extracted from the received data and is stored in a memory. The instruction data is extracted from the received data, and the program unit or part thereof specified by the instruction data is read from the memory and is executed. Then, the bit stream data and the execution result are displayed. This ensures smooth synchronization of reproduction of a bit stream with execution of an associated program and efficient use of resources.
摘要翻译：根据数据显示方法，接收具有程序单元的数据和用于在比特流数据上复用的程序单元的指令数据。从接收到的数据中提取程序单元并将其存储在存储器中。从接收的数据中提取指令数据，并且从存储器读取由指令数据指定的程序单元或其一部分，并执行。然后，显示比特流数据和执行结果。这确保了位流的再现与相关程序的执行和资源的有效利用的顺利同步。

9. 发明申请

US20150301892A1 MEMORY SYSTEM 有权
标题翻译：记忆系统
公开(公告)号：US20150301892A1
公开(公告)日：2015-10-22
申请号：US14789090
申请日：2015-07-01
申请人： Masaya Tarui , Tatsunori Kanai , Yutaka Yamada
发明人： Masaya Tarui , Tatsunori Kanai , Yutaka Yamada
IPC分类号： G06F11/10 , G06F3/06
CPC分类号： G06F11/1076 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/08 , G06F11/1012 , G06F11/1048 , G06F11/1666 , G11C29/42 , H03M13/19
摘要： A memory system comprises an encoding processing circuit 100 that performs redundant encoding process on target data Din to be written to thereby generate data RDin such that the number of bits having a predetermined value is half or less than the total number of bits, and a memory 120 to which the data RDin generated by the encoding processing circuit are written.
摘要翻译：存储器系统包括对要写入的目标数据Din进行冗余编码处理的编码处理电路100，从而生成数据RDin，使得具有预定值的位数是总位数的一半或更少，存储器写入由编码处理电路产生的数据RDin 120的数据。

10. 发明授权

US09110667B2 Control system, control method, and computer program product 有权
标题翻译：控制系统，控制方法和计算机程序产品
公开(公告)号：US09110667B2
公开(公告)日：2015-08-18
申请号：US13546246
申请日：2012-07-11
申请人： Yusuke Shirota , Tetsuro Kimura , Tatsunori Kanai , Haruhiko Toyama , Koichi Fujisaki , Junichi Segawa , Masaya Tarui , Satoshi Shirai , Hiroyoshi Haruki , Akihiro Shibata
发明人： Yusuke Shirota , Tetsuro Kimura , Tatsunori Kanai , Haruhiko Toyama , Koichi Fujisaki , Junichi Segawa , Masaya Tarui , Satoshi Shirai , Hiroyoshi Haruki , Akihiro Shibata
IPC分类号： G06F1/32 , G06F12/08
CPC分类号： G06F1/3275 , G06F12/0862 , G06F2212/1028 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： According to an embodiment, a control system includes a processing device; a main storage device to store the data; a cache memory to store part of the data stored; a prefetch unit to predict data highly likely to be accessed and execute prefetch, reading out data in advance onto the cache memory; and a power supply unit. The system further includes: a detecting unit to detect whether the processing device is in an idle state; a determining unit that determines whether to stop the supply of power to the cache memory in accordance with the state of the prefetch when determined as idle state; and a power supply control unit that controls the power supply unit so as to stop the supply of power, or controls the power supply unit so as to continue the supply of power.
摘要翻译：根据实施例，控制系统包括处理装置; 用于存储数据的主存储装置; 用于存储存储的部分数据的高速缓冲存储器; 用于预测非常可能被访问并执行预取的数据的预取单元，预先将数据读出到高速缓冲存储器上; 和电源单元。该系统还包括：检测单元，用于检测处理设备是否处于空闲状态; 确定单元，当确定为空闲状态时，根据预取的状态确定是否停止向高速缓冲存储器供电; 以及电源控制单元，其控制电源单元以停止电力供应，或者控制电源单元以继续供电。

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