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1. 发明授权

US08847812B2 Time-to-digital conversion stage and time-to-digital converter including the same 有权
标题翻译：时间到数字转换级和包括它的时间 - 数字转换器
公开(公告)号：US08847812B2
公开(公告)日：2014-09-30
申请号：US13589550
申请日：2012-08-20
申请人： Shiro Dosho , Takuji Miki
发明人： Shiro Dosho , Takuji Miki
IPC分类号： H03M1/50 , G04F10/00 , H03K5/151
CPC分类号： G04F10/005 , H03K5/1515 , H03M1/50
摘要： In a time-to-digital conversion stage, a time-to-digital conversion circuit outputs an n-bit digital signal, which represents an integer value ranging from −(2n-1−1) to +(2n-1−1), based on a phase difference between a first and a second signals input thereto; a time difference amplifier circuit amplifies the phase difference between the first and the second signals 2n-1 times, and outputs two signals having an amplified phase difference therebetween; a delay adjustment circuit adds a phase difference dependent on the digital signal to the two signals output from the time difference amplifier circuit, and outputs another two signals; an output detection circuit detects that the delay adjustment circuit has output the another two signals, and outputs a detection signal; and a storage circuit latches the digital signal in synchronism with the detection signal. Multi-stage coupling of the time-to-digital conversion stages forms a pipeline time-to-digital converter.
摘要翻译：在时间数字转换阶段，时间数字转换电路输出表示从 - （2n-1-1）到+（2n-1-1）的整数值的n位数字信号，基于输入到其的第一和第二信号之间的相位差; 时差放大器电路将第一和第二信号2n-1次之间的相位差放大倍数，并输出两个放大相位差的信号; 延迟调整电路将与数字信号相关的相位差与从时差放大器电路输出的两个信号相加，并输出另外两个信号; 输出检测电路检测出延迟调整电路输出了另外两个信号，并输出检测信号; 并且存储电路与检测信号同步地锁存数字信号。时间 - 数字转换级的多级耦合形成流水线时间 - 数字转换器。

2. 发明申请

US20120161990A1 INTEGRATOR AND OVERSAMPLING A/D CONVERTER HAVING THE SAME 有权
标题翻译：集成器和OVERSAMPING A / D转换器
公开(公告)号：US20120161990A1
公开(公告)日：2012-06-28
申请号：US13410964
申请日：2012-03-02
申请人： Shiro Dosho
发明人： Shiro Dosho
IPC分类号： H03M1/12 , G06G7/18
CPC分类号： G06G7/186 , H03H11/12 , H03M3/39 , H03M3/454
摘要： A high order integrator is configured using an operational amplifier, a first filter connected between an input terminal of the integrator and an inverted input terminal of the operational amplifier, and a second filter connected between the inverted input terminal and output terminal of the operational amplifier. The first filter includes n serially-connected first resistance elements, n-1 first capacitance elements each connected between each interconnecting node of the first resistance elements and the ground, and n-1 second resistance elements each connected between each interconnecting node of the first resistance elements and the ground. The second filter includes n serially-connected second capacitance elements, n-1 third resistance elements each connected between each interconnecting node of the second capacitance elements and the ground, and n-1 third capacitance elements each connected between each interconnecting node of the second capacitance elements and the ground.
摘要翻译：高阶积分器使用运算放大器配置，第一滤波器连接在积分器的输入端和运算放大器的反相输入端之间，第二滤波器连接在运算放大器的反相输入端和输出端之间。第一滤波器包括n个串联连接的第一电阻元件，每个连接在第一电阻元件的每个互连节点和地之间的n-1个第一电容元件，以及分别连接在第一电阻的每个互连节点之间的n-1个第二电阻元件元素和地面。第二滤波器包括n个串联连接的第二电容元件，n-1个第三电阻元件，每个连接在第二电容元件的每个互连节点和地之间; n-1个第三电容元件，每个连接在第二电容的每个互连节点之间元素和地面。

3. 发明授权

US07978013B2 Phase synchronizing circuit 有权
标题翻译：相位同步电路
公开(公告)号：US07978013B2
公开(公告)日：2011-07-12
申请号：US12096664
申请日：2006-10-25
申请人： Shiro Dosho , Kazuaki Sogawa , Yuji Yamada , Naoshi Yanagisawa
发明人： Shiro Dosho , Kazuaki Sogawa , Yuji Yamada , Naoshi Yanagisawa
IPC分类号： H03L7/00
CPC分类号： H03L7/0898 , H03L7/093 , H03L7/099 , H03L7/0995 , H03L7/107 , H03L7/183 , H03L2207/06
摘要： A constant determination unit (90) determines various constants, that are the magnitude of a charge current outputted from a charge pump circuit (30), the time constant of a loop filter (40), and the gain of a voltage controlled oscillator (50), so as to make the proportionality constant of a natural frequency of a phase locked loop circuit for the input frequency of the phase locked loop circuit and the damping factor to be predetermined values, and outputs various control signals based on the determined constants. The charge pump circuit (30), the loop filter (40), and the voltage controlled oscillator (50) modify the magnitude of the charge current, the time constant, and the gain, respectively, in accordance with control signals outputted from the constant determination unit (90).
摘要翻译：常数确定单元（90）确定各种常数，即从电荷泵电路（30）输出的充电电流的大小，环路滤波器（40）的时间常数和压控振荡器（50）的增益），以使锁相环电路的输入频率和阻尼因子的锁相环电路的固有频率的比例常数成为预定值，并根据确定的常数输出各种控制信号。电荷泵电路（30），环路滤波器（40）和压控振荡器（50）根据从常数输出的控制信号分别修正充电电流的大小，时间常数和增益确定单元（90）。

4. 发明申请

US20110050476A1 INTEGRATOR, RESONATOR, AND OVERSAMPLING A/D CONVERTER 有权
标题翻译：集成器，谐振器和超滤A / D转换器
公开(公告)号：US20110050476A1
公开(公告)日：2011-03-03
申请号：US12888126
申请日：2010-09-22
申请人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa , Yosuke Mitani , Masao Takayama
发明人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa , Yosuke Mitani , Masao Takayama
IPC分类号： H03M1/12 , G06G7/18
CPC分类号： H03M3/454 , H03M3/404 , H03M3/43
摘要： An integrator includes an operational amplifier, a first filter connected to an inverting input terminal of the operational amplifier, and a second filter connected between the inverting input terminal and an output terminal of the operational amplifier. The first filter includes n resistive elements connected in series, and (n−1) capacitive elements each having one end connected to an interconnecting node of the resistive elements and the other end connected to ground. The second filter includes n capacitive elements connected in series, and (n−1) resistive elements each having one end connected to an interconnecting node of the capacitive elements and the other end connected to ground.
摘要翻译：积分器包括运算放大器，连接到运算放大器的反相输入端的第一滤波器和连接在运算放大器的反相输入端和输出端之间的第二滤波器。第一滤波器包括串联连接的n个电阻元件和（n-1）个电容元件，每个电容元件的一端连接到电阻元件的互连节点，另一端连接到地。第二滤波器包括串联连接的n个电容元件和（n-1）个电阻元件，每个电阻元件的一端连接到电容元件的互连节点，另一端连接到地。

5. 发明授权

US07855670B2 A-to-D converter 有权
公开(公告)号：US07855670B2
公开(公告)日：2010-12-21
申请号：US12749277
申请日：2010-03-29
申请人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa
发明人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa
IPC分类号： H03M1/66
CPC分类号： H03M1/46 , H03M1/1215 , H03M1/14 , H03M1/667 , H03M1/682
摘要： A successive approximation type A-to-D converter includes a cyclic D-to-A converter (11), a comparator (12) for comparing an analog value with an output value of the D-to-A converter (11), and memory means (13) for sequentially storing an output value of the comparator (12) and supplying the stored value to the D-to-A converter (11) in a reverse order.

6. 发明授权

US07808295B2 Multiphase level shift system 有权
标题翻译：多相电平转换系统
公开(公告)号：US07808295B2
公开(公告)日：2010-10-05
申请号：US12296021
申请日：2007-06-15
申请人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Shiro Dosho , Yusuke Tokunaga
发明人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Shiro Dosho , Yusuke Tokunaga
IPC分类号： H03L5/00 , H03F3/66
CPC分类号： H03K19/01855 , H03K3/0315 , H03K3/354
摘要： Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°
摘要翻译： n个电平移位器（LS0〜LS7）中的每一个包括用于接收n个时钟信号（P0〜P7）中的任何一个的NMOS晶体管（Mn1）和用于接收来自另一个电平移位器的输出信号的PMOS晶体管（Mp1）。给予每个电平移位器（LS0至LS7）中的PMOS晶体管（Mp1）的输出信号是电平移位器的输出信号，其接收相对于给予NMOS的时钟信号的相位延迟量的时钟信号包括在该电平移位器中的晶体管（Mn1）是相位量X（0°

7. 发明申请

US20090134931A1 MULTIPHASE LEVEL SHIFT SYSTEM 有权
标题翻译：多级水平移位系统
公开(公告)号：US20090134931A1
公开(公告)日：2009-05-28
申请号：US12296021
申请日：2007-06-15
申请人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Shiro Dosho , Yusuke Tokunaga
发明人： Shiro Sakiyama , Akinori Matsumoto , Takashi Morie , Shiro Dosho , Yusuke Tokunaga
IPC分类号： H03L5/00
CPC分类号： H03K19/01855 , H03K3/0315 , H03K3/354
摘要： Each of n level shifters (LS0 to LS7) includes an NMOS transistor (Mn1) for receiving any one of n clock signals (P0 to P7) and a PMOS transistor (Mp1) for receiving an output signal from another level shifter. An output signal given to the PMOS transistor (Mp1) included in each of the level shifters (LS0 to LS7) is an output signal of the level shifter which receives the clock signal whose phase delay amount with respect to the clock signal given to the NMOS transistor (Mn1) included in that level shifter is a phase amount X (0°
摘要翻译： n个电平移位器（LS0〜LS7）中的每一个包括用于接收n个时钟信号（P0〜P7）中的任何一个的NMOS晶体管（Mn1）和用于接收来自另一个电平移位器的输出信号的PMOS晶体管（Mp1）。给予每个电平移位器（LS0至LS7）中的PMOS晶体管（Mp1）的输出信号是电平移位器的输出信号，其接收相对于给予NMOS的时钟信号的相位延迟量的时钟信号包括在该电平移位器中的晶体管（Mn1）是相位量X（0°

8. 发明申请

US20090040089A1 A-TO-D CONVERTER 有权
标题翻译： A转To转换器
公开(公告)号：US20090040089A1
公开(公告)日：2009-02-12
申请号：US12162930
申请日：2007-11-30
申请人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa
发明人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa
IPC分类号： H03M1/38
CPC分类号： H03M1/46 , H03M1/1215 , H03M1/14 , H03M1/667 , H03M1/682
摘要： A successive approximation type A-to-D converter includes a cyclic D-to-A converter (11), a comparator (12) for comparing an analog value with an output value of the D-to-A converter (11), and memory means (13) for sequentially storing an output value of the comparator (12) and supplying the stored value to the D-to-A converter (11) in a reverse order.
摘要翻译：逐次逼近型A到D转换器包括循环D转换器（A），用于将模拟值与D转换器（11）的输出值进行比较的比较器（12），以及存储装置（13），用于顺序地存储比较器（12）的输出值，并以相反的顺序将存储的值提供给D-A转换器（11）。

9. 发明授权

US07477099B2 Filter adjustment circuit 有权
标题翻译：滤波器调节电路
公开(公告)号：US07477099B2
公开(公告)日：2009-01-13
申请号：US11792081
申请日：2005-09-02
申请人： Kouji Okamoto , Takashi Morie , Shiro Dosho , Hirokuni Fujiyama
发明人： Kouji Okamoto , Takashi Morie , Shiro Dosho , Hirokuni Fujiyama
IPC分类号： H03B1/00
CPC分类号： H03G5/16 , H03H11/1291 , H03H11/20
摘要： In a filter adjustment circuit for an analog filter circuit such as a Gm-C filter, an input signal IS from a reference signal generation circuit 1 is inputted to a Gm-C filter 2 to be filtered and then converted by a conversion circuit 3 to a digital signal. A reference signal RS from the reference signal generation circuit 1 is converted by a conversion circuit 4 to a digital signal. The two converted signals are held in time series in a holding circuit 5. A timing generation circuit 6 generates an update timing signal en based on a reference time-series signal ref from the holding circuit 5. A control signal generation circuit 7 generates a control signal CS based on the reference time-series signal ref and a filter output time-series signal tgt, each from the holding circuit 5. The control signal CS is inputted to the Gm-C filter 2 in response to the update timing signal en to adjust the gain of the Gm-C filter 2. As a result, variations in the response characteristics of the Gm-C filter 2 are adjusted with high accuracy with a simple circuit structure.
摘要翻译：在用于诸如Gm-C滤波器的模拟滤波器电路的滤波器调节电路中，来自参考信号产生电路1的输入信号IS被输入到要过滤的Gm-C滤波器2，然后由转换电路3转换成数字信号。来自参考信号发生电路1的参考信号RS由转换电路4转换成数字信号。两个转换信号在保持电路5中保持时间序列。定时产生电路6基于来自保持电路5的基准时间序列信号ref产生更新定时信号en。控制信号产生电路7产生控制基于参考时间序列信号ref的信号CS和来自保持电路5的滤波器输出时间序列信号tgt。控制信号CS响应于更新定时信号en至...而被输入到Gm-C滤波器2 调整Gm-C滤波器2的增益。结果，以简单的电路结构，高精度地调整Gm-C滤波器2的响应特性的变化。

10. 发明授权

US07459964B2 Switched capacitor filter and feedback system 有权
标题翻译：开关电容滤波器和反馈系统
公开(公告)号：US07459964B2
公开(公告)日：2008-12-02
申请号：US10594398
申请日：2004-11-17
申请人： Shiro Dosho , Yusuke Tokunaga
发明人： Shiro Dosho , Yusuke Tokunaga
IPC分类号： H03K5/00 , H03L7/06
CPC分类号： H03L7/093 , H03H19/004 , H03L7/0891
摘要： A loop filter (30) includes a first capacitor (31) provided between an input terminal for a current signal and a reference voltage, a switched capacitor circuit (32) provided between the input terminal and the first capacitor (31) and a second capacitor (33) provided in parallel to the first capacitor (31) and the switched capacitor circuit (32). In the switched capacitor circuit (32), when a third capacitor (321) is connected to the first capacitor (31), a fourth capacitor (322) is connected to the second capacitor (33). In the loop filter (30) having the above-described configuration, a capacitance value of the second capacitor (33) is set to be larger than respective capacitance values of the third and fourth capacitors (321 and 322).
摘要翻译：环路滤波器（30）包括设置在电流信号的输入端和参考电压之间的第一电容器（31），设置在输入端子和第一电容器（31）之间的开关电容器电路（32）和第二电容器（33）与所述第一电容器（31）和所述开关电容器电路（32）并联设置。在开关电容电路（32）中，当第三电容器（321）连接到第一电容器（31）时，第四电容器（322）连接到第二电容器（33）。在具有上述结构的环路滤波器（30）中，第二电容器（33）的电容值被设定为大于第三和第四电容器（321和322）的各个电容值。

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