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1. 发明申请

US20130016820A1 ECHO CANCELLATION APPARATUS, CONFERENCING SYSTEM USING THE SAME, AND ECHO CANCELLATION METHOD 有权
标题翻译： ECHO取消设备，使用该设备的会议系统和ECHO取消方法
公开(公告)号：US20130016820A1
公开(公告)日：2013-01-17
申请号：US13544514
申请日：2012-07-09
申请人： Shinichi TAKAYAMA , Tsuyoki Nishikawa
发明人： Shinichi TAKAYAMA , Tsuyoki Nishikawa
IPC分类号： H04M3/42 , H04M9/08
CPC分类号： H04B3/23
摘要： An echo cancellation apparatus is connectable to a speaker configured to output speaker signals and a microphone configured to receive a sound from the speaker and including a plurality of microphone elements. The echo cancellation apparatus includes: a generating unit configured to generate a plurality of sensitivity signals having different sensitivity patterns which represent directionality of the microphone, based on a plurality of microphone signals obtained from the respective microphone signals; a delay estimating unit configured to determine a shortest delay time as an estimated delay time, the shortest delay time being a shortest one of delay times between the speaker signals and the microphone signals, the delay times being obtained from the respective sensitivity signals; and an echo suppressing unit configured to suppress echoes of the plurality of microphone signals using the estimated delay time.
摘要翻译：回声消除装置可连接到被配置为输出扬声器信号的扬声器和被配置为从扬声器接收声音并且包括多个麦克风元件的麦克风。回波消除装置包括：生成单元，被配置为基于从各个麦克风信号获得的多个麦克风信号，生成具有表示麦克风的方向性的不同灵敏度图案的多个灵敏度信号; 延迟估计单元，被配置为将最短延迟时间确定为估计延迟时间，所述最短延迟时间是所述扬声器信号和所述麦克风信号之间的延迟时间中最短的延迟时间，所述延迟时间是从各个灵敏度信号获得的; 以及回波抑制单元，被配置为使用所估计的延迟时间来抑制所述多个麦克风信号的回波。

2. 发明申请

US20120218845A1 SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREOF 失效
标题翻译：半导体器件及其控制方法
公开(公告)号：US20120218845A1
公开(公告)日：2012-08-30
申请号：US13404940
申请日：2012-02-24
申请人： Shinichi TAKAYAMA , Kazuhiko KAJIGAYA
发明人： Shinichi TAKAYAMA , Kazuhiko KAJIGAYA
IPC分类号： G11C7/12
CPC分类号： G11C7/12 , G11C7/18 , G11C11/401 , G11C11/4094 , G11C29/06 , G11C29/12005 , G11C2029/1204
摘要： Disclosed herein is a semiconductor device comprising an array having a hierarchical bit line structure, global bit lines adjacent to each other, local bit lines corresponding to the global bit lines, hierarchical switches, precharge circuits precharging the global bit lines, precharge circuits precharging the local bit lines, and a control circuit. When performing a test of the array, precharge voltages for the global bit lines are set to potentials different from each other, and the control circuit controls the potentials to be applied to the local bit lines through the global bit lines and the hierarchical switches.
摘要翻译：本文公开了一种半导体器件，其包括具有分级位线结构的阵列，彼此相邻的全局位线，对应于全局位线的局部位线，分层开关，预充电全局位线的预充电电路，预充电电路对本地位线和控制电路。当对阵列进行测试时，全局位线的预充电电压被设置为彼此不同的电位，并且控制电路通过全局位线和分层开关控制施加到局部位线的电位。

3. 发明申请

US20110292709A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20110292709A1
公开(公告)日：2011-12-01
申请号：US13117374
申请日：2011-05-27
申请人： Shinichi TAKAYAMA , Akira KOTABE , Kiyoo ITOH , Tomonori SEKIGUCHI
发明人： Shinichi TAKAYAMA , Akira KOTABE , Kiyoo ITOH , Tomonori SEKIGUCHI
IPC分类号： G11C5/06 , G11C7/06
CPC分类号： G11C7/08 , G11C11/4091 , G11C11/4094
摘要： A semiconductor device includes a sense amplifier circuit. The sense amplifier circuit includes a cross-coupled first transistor and second transistor that perform amplification. The sources of the cross-coupled transistors are respectively connected in series with a third transistor and a fourth transistor, and electrical current supply capability of the third and fourth transistors is controlled by a control voltage given to control electrodes of the third and fourth transistors. In a data retaining period, a minimum sub-threshold current necessary for retaining the data is flowed to the third and fourth transistors according to the control voltage, and bit line potential is maintained.
摘要翻译：半导体器件包括读出放大器电路。读出放大器电路包括执行放大的交叉耦合的第一晶体管和第二晶体管。交叉耦合晶体管的源极分别与第三晶体管和第四晶体管串联连接，并且通过施加到第三和第四晶体管的控制电极的控制电压来控制第三和第四晶体管的电流供应能力。在数据保持期间，保持数据所需的最小子阈值电流根据控制电压流向第三和第四晶体管，并保持位线电位。

4. 发明申请

US20110220968A1 DEVICE 有权
标题翻译：设备
公开(公告)号：US20110220968A1
公开(公告)日：2011-09-15
申请号：US13042108
申请日：2011-03-07
申请人： Shinichi TAKAYAMA , Yasutoshi YAMADA
发明人： Shinichi TAKAYAMA , Yasutoshi YAMADA
IPC分类号： H01L23/528
CPC分类号： H01L27/0207 , G11C11/4094 , G11C11/4096 , G11C11/4097 , H01L27/10811 , H01L27/10876 , H01L27/10885 , H01L27/10897
摘要： A device includes a semiconductor substrate, a first local bit line formed in the semiconductor substrate and elongated in a first direction, a first insulating layer on the semiconductor substrate, a first global bit line formed on the first insulating layer, a first path formed in the first insulating layer to couple a first end of the first local bit line with the first global bit line, and a second path formed in the first insulating layer to couple a second end of the first local bit line with the first global bit line.
摘要翻译：一种器件包括半导体衬底，形成在半导体衬底中并在第一方向上延伸的第一局部位线，在半导体衬底上的第一绝缘层，形成在第一绝缘层上的第一全局位线，形成在第一绝缘层上的第一通路所述第一绝缘层将所述第一局部位线的第一端与所述第一全局位线耦合，以及形成在所述第一绝缘层中以将所述第一局部位线的第二端与所述第一全局位线耦合的第二路径。

5. 发明申请

US20080273102A1 DETECTION DEVICE FOR DEFECTIVE PIXEL IN PHOTOGRAPHIC DEVICE 审中-公开
标题翻译：摄影装置中缺陷像素的检测装置
公开(公告)号：US20080273102A1
公开(公告)日：2008-11-06
申请号：US12112188
申请日：2008-04-30
申请人： Kaoru HYAKUTAKE , Takaaki SHOJI , Machiko AZUMA , Shinichi TAKAYAMA
发明人： Kaoru HYAKUTAKE , Takaaki SHOJI , Machiko AZUMA , Shinichi TAKAYAMA
IPC分类号： H04N9/64
CPC分类号： H04N5/367
摘要： The defeat determination unit determines whether a target pixel among the pixels of the image sensor is defective on the basis of a first defect map and at least one second defect map. The first defeat map shows a first relationship between a pixel value of the target pixel and pixel values of first neighboring same-color pixels with the target pixel that neighbor and surround the target pixel. The second defect map shows a second relationship between a pixel value of a heterochromatic adjacent pixel with the target pixel and pixel values of second neighboring same-color pixels with the heterochromatic adjacent pixel that neighbor and surround the heterochromatic adjacent pixel.
摘要翻译：失败确定单元基于第一缺陷图和至少一个第二缺陷图来确定图像传感器的像素中的目标像素是否有缺陷。第一失败映射显示目标像素的像素值与第一相邻相同像素的像素值与目标像素相邻并围绕目标像素的第一关系。第二缺陷图显示了异相邻近像素的像素值与目标像素之间的第二关系，以及与邻近和围绕异色相邻像素的异色相邻像素的第二相邻相同像素的像素值之间的第二关系。

6. 发明申请

US20100007724A1 ELECTRONIC ENDOSCOPE SIGNAL-PROCESSING DEVICE AND ELECTRONIC ENDOSCOPE SYSTEM 有权
标题翻译：电子内窥镜信号处理装置和电子内窥镜系统
公开(公告)号：US20100007724A1
公开(公告)日：2010-01-14
申请号：US12497871
申请日：2009-07-06
申请人： Shinichi TAKAYAMA
发明人： Shinichi TAKAYAMA
IPC分类号： H04N7/18
CPC分类号： H04N9/69 , A61B1/00009 , A61B1/042 , A61B1/05 , H04N1/6027 , H04N2005/2255
摘要： An electronic endoscope signal-processing device is provided that includes a gradation compensation processor. The gradation compensation processor compensates for R, G, and B gradations by controlling R, G, and B tone curves defining relationship between input values and output values of each of the R, G, and B signals. The R tone curve is shaped so as to squash the output values of the R Signal when the R signal input values are in a relatively low range and to expand the output values when the input values are in a relatively high range.
摘要翻译：提供一种包括灰度补偿处理器的电子内窥镜信号处理装置。灰度补偿处理器通过控制定义R，G和B信号中的每一个的输入值和输出值之间的关系的R，G和B色调曲线来补偿R，G和B等级。当R信号输入值处于相对低的范围内时，R色调曲线成形为压缩R信号的输出值，并且当输入值处于相对高的范围时扩大输出值。

7. 发明申请

US20090016635A1 EDGE-ENHANCEMENT DEVICE AND EDGE-ENHANCEMENT METHOD 有权
标题翻译：边缘增强装置和边缘增强方法
公开(公告)号：US20090016635A1
公开(公告)日：2009-01-15
申请号：US12170626
申请日：2008-07-10
申请人： Shinichi TAKAYAMA
发明人： Shinichi TAKAYAMA
IPC分类号： G06K9/40
CPC分类号： H04N9/646 , G06T5/004 , G06T2207/10016 , G06T2207/10068 , G06T2207/20192 , G06T2207/30004 , H04N5/208
摘要： An edge-enhancement device for subjecting input image data to edge enhancement so as to generate output image data has an edge-component generator, a weighting processor, and an addition processor. The input image data is obtained from a frame image having a plurality of pixels, and the input image data contains luminance data. The edge-component generator generates an edge component of the input image data. The weighting processor applies a weight according to the value of the luminance data of each pixel to a calculated edge component of each pixel so as to generate a weighted edge component for each pixel. The addition processor adds the weighted edge component of each pixel to the input image data of the pixel so as to generate the output image data.
摘要翻译：用于对输入图像数据进行边缘增强以产生输出图像数据的边缘增强装置具有边缘分量生成器，加权处理器和加法处理器。从具有多个像素的帧图像获得输入图像数据，并且输入图像数据包含亮度数据。边缘分量生成器生成输入图像数据的边缘分量。加权处理器根据每个像素的亮度数据的值对每个像素的计算的边缘分量应用权重，以便为每个像素产生加权的边缘分量。加法处理器将每个像素的加权边缘分量与像素的输入图像数据相加，以产生输出图像数据。

8. 发明申请

US20070232860A1 ENDOSCOPE 审中-公开
公开(公告)号：US20070232860A1
公开(公告)日：2007-10-04
申请号：US11691533
申请日：2007-03-27
申请人： Wataru KUBO , Masahiro OONO , Akira ARIMOTO , Shinichi ARAI , Koichi SATO , Koichi TSUTAMURA , Shinichi TAKAYAMA
发明人： Wataru KUBO , Masahiro OONO , Akira ARIMOTO , Shinichi ARAI , Koichi SATO , Koichi TSUTAMURA , Shinichi TAKAYAMA
IPC分类号： A61B1/06
CPC分类号： A61B5/0017 , A61B1/00006 , A61B1/00013 , A61B1/00096 , A61B1/045 , A61B1/051 , A61B1/07
摘要： An endoscope comprises an electric scope and a processor. The electric scope has a CMOS sensor and a video-signal emitting unit that outputs an image signal that is imaged by the CMOS sensor and that is converted to a light signal. The processor has a video-signal photo sensor unit that receives light regarding the image signal that is output from the video-signal emitting unit, and performs an image processing operation based on the light regarding the image signal.
摘要翻译：内窥镜包括电镜和处理器。电动镜具有CMOS传感器和视频信号发射单元，其输出由CMOS传感器成像并被转换为光信号的图像信号。处理器具有视频信号光传感器单元，其接收关于从视频信号发射单元输出的图像信号的光，并且基于关于图像信号的光执行图像处理操作。

9. 发明申请

US20120267792A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20120267792A1
公开(公告)日：2012-10-25
申请号：US13455171
申请日：2012-04-25
申请人： Shinichi TAKAYAMA , Kazuo ONO , Tomonori SEKIGUCHI , Akira KOTABE , Yoshimitsu YANAGAWA
发明人： Shinichi TAKAYAMA , Kazuo ONO , Tomonori SEKIGUCHI , Akira KOTABE , Yoshimitsu YANAGAWA
IPC分类号： H01L23/522
CPC分类号： H01L23/5286 , H01L23/481 , H01L25/0657 , H01L2224/16145 , H01L2225/06544
摘要： A stacked device includes a plurality of semiconductor chips connected to each other by through electrodes. The same number of through electrodes are included in each of paths extending from a first power source terminal through each of circuit elements formed for the semiconductor chips to a second power source terminal.
摘要翻译：堆叠式器件包括通过电极彼此连接的多个半导体芯片。在从第一电源端子通过形成为半导体芯片的电路元件的每一个延伸到第二电源端子的每个路径中包括相同数量的贯通电极。

10. 发明申请

US20110176379A1 SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CELL ARRAY OF OPEN BIT LINE TYPE AND CONTROL METHOD THEREOF 审中-公开
标题翻译：具有开放式线型存储器单元阵列的半导体存储器件及其控制方法
公开(公告)号：US20110176379A1
公开(公告)日：2011-07-21
申请号：US13008408
申请日：2011-01-18
申请人： Shinichi TAKAYAMA , Akira Kotabe , Kazuo Ono , Tomonori Sekiguchi , Yoshimitsu Yanagawa , Riichiro Takemura
发明人： Shinichi TAKAYAMA , Akira Kotabe , Kazuo Ono , Tomonori Sekiguchi , Yoshimitsu Yanagawa , Riichiro Takemura
IPC分类号： G11C7/06
CPC分类号： G11C11/4091 , G11C11/4094 , G11C11/4097 , G11C2207/002
摘要： A semiconductor memory device includes: first and second bit lines of an open bit-line system; a sense amplifier that amplifies a potential difference between the first and second bit lines; a pair of first and second local data lines corresponding to the first and second bit lines, respectively; and a write amplifier circuit. The write amplifier circuit changes a potential of the second local data line without changing a potential of the first local data line at a time of writing data for the first bit line, and changes a potential of the first local data line without changing a potential of the second local data line at a time of writing data for the second bit line.
摘要翻译：半导体存储器件包括：开放位线系统的第一和第二位线; 读出放大器，放大第一和第二位线之间的电位差; 对应于第一和第二位线的一对第一和第二本地数据线; 和写放大器电路。写入放大器电路在写入第一位线的数据时改变第二本地数据线的电位而不改变第一本地数据线的电位，并且在不改变第一本地数据线的电位的情况下改变第一本地数据线的电位在第二位线的数据写入时的第二本地数据线。

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