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1. 发明授权

US5875130A Method for programming flash electrically erasable programmable read-only memory 失效
标题翻译：闪存电可擦除可编程只读存储器的编程方法
公开(公告)号：US5875130A
公开(公告)日：1999-02-23
申请号：US085705
申请日：1998-05-27
申请人： Sameer S. Haddad , Wing H. Leung , John Chen , Ravi S. Sunkavalli , Ravi P. Gutala , Jonathan S. Su , Vei-Han Chan , Colin S. Bill
发明人： Sameer S. Haddad , Wing H. Leung , John Chen , Ravi S. Sunkavalli , Ravi P. Gutala , Jonathan S. Su , Vei-Han Chan , Colin S. Bill
IPC分类号： G11C16/10 , G11C16/34 , G11C13/00
CPC分类号： G11C16/3409 , G11C16/10 , G11C16/3404
摘要： A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a semiconductor substrate, and a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate formed on the substrate. A controller controls a power source to apply an operational pulse to the drain of a cell, and apply a source to substrate bias voltage to the cell while the operational pulse is being applied thereto, the bias voltage having a value selected to reduce or substantially eliminate leakage current in the cell. The operational pulse can be an overerase correction pulse. In this case, a voltage which is substantially equal to the bias voltage is applied to the control gate for the duration of the overerase correction pulse. The operational pulse can also be a programming pulse. In this case, a voltage which is higher than the bias voltage is applied to the control gate of the selected wordline for the duration of the programming pulse. The bias voltage is preferably applied during both the overerase correction and programming pulses, reducing the power requirements and reducing the background leakage of the cells to a level at which program, read and overerase correction operations can be operatively performed.
摘要翻译：闪存电可擦除可编程只读存储器（EEPROM）包括半导体衬底和多个场效应晶体管存储单元，每个具有形成在衬底上的源极，漏极，浮置栅极和控制栅极。控制器控制电源以将操作脉冲施加到单元的漏极，并且在施加操作脉冲时将源施加到单元的衬底偏置电压，所述偏置电压具有被选择为减少或基本上消除的值电池中的漏电流。操作脉冲可以是过高修正脉冲。在这种情况下，在过扫描校正脉冲的持续时间内，向控制栅极施加基本上等于偏置电压的电压。操作脉冲也可以是编程脉冲。在这种情况下，在编程脉冲的持续时间内，将高于偏置电压的电压施加到所选字线的控制栅极。偏置电压优选地在过电压过程校正和编程脉冲期间都被施加，从而降低功率需求并将电池的背景泄漏减小到能够可操作地执行程序，读取和过电压校正操作的电平。

2. 发明授权

US06275415B1 Multiple byte channel hot electron programming using ramped gate and source bias voltage 有权
标题翻译：使用斜坡栅极和源偏置电压的多字节通道热电子编程
公开(公告)号：US06275415B1
公开(公告)日：2001-08-14
申请号：US09416563
申请日：1999-10-12
申请人： Sameer S. Haddad , Ravi S. Sunkavalli , Wing Han Leung , John Chen , Ravi Prakash Gutala , Colin Bill , Vei-Han Chan
发明人： Sameer S. Haddad , Ravi S. Sunkavalli , Wing Han Leung , John Chen , Ravi Prakash Gutala , Colin Bill , Vei-Han Chan
IPC分类号： G11C1604
CPC分类号： G11C16/12
摘要： A memory device having multiple banks, each bank having multiple memory cells and a method of programming multiple memory cells in the device wherein a bias voltage is applied to a common source terminal of the multiple memory cells and a time varying voltage is applied to gates of the memory cells that are to be programmed. In one embodiment, the voltage applied to the gates of the memory cells to be programmed is a ramp voltage. In a second embodiment, the voltage applied to the gates of the memory cells to be programmed is an increasing step voltage. In another embodiment, the bias voltage applied to the common source terminal and the voltage applied to the control gates of the memory cells to be programmed are selected so that the current flowing through cells being programmed is reduced and that the leakage current from memory cells that are not to be programmed is substantially eliminated. In another embodiment, a bias voltage is applied to the common source terminal and a bias voltage is applied to the common well voltage. The combination of the voltages applied to the control gates and to the sources decreases loading on the bitlines to ensure that VDS does not fall below a required level necessary for the maintenance of the hot carrier effect during programming. A bias voltage can also be applied to the wells of the memory cells while the common source terminal is held at ground. Feedback control of the programming gate voltages can be used to control the power required for programming.
摘要翻译：一种具有多个存储单元的存储器件，每个存储体具有多个存储器单元，以及一种编程器件中的多个存储器单元的方法，其中偏置电压施加到多个存储器单元的公共源极端子，并且将时变电压施加到要编程的存储单元。在一个实施例中，施加到要编程的存储器单元的栅极的电压是斜坡电压。在第二实施例中，施加到待编程的存储器单元的栅极的电压是增加的阶梯电压。在另一个实施例中，选择施加到公共源极端子的偏置电压和施加到要编程的存储器单元的控制栅极的电压，使得流过被编程的单元的电流减小，并且来自存储器单元的泄漏电流不被编程的基本上被消除。在另一个实施例中，将偏置电压施加到公共源极端子，并将偏置电压施加到公共井电压。施加到控制栅极和源极的电压的组合减少了位线上的负载，以确保VDS不会降低到在编程期间维持热载流子效应所需的水平。偏置电压也可以施加到存储单元的阱，同时公共源极保持在地。编程栅极电压的反馈控制可用于控制编程所需的功率。

3. 发明授权

US6046932A Circuit implementation to quench bit line leakage current in programming and over-erase correction modes in flash EEPROM 有权
标题翻译：电路实现在闪存EEPROM中编程和过擦除校正模式中的位线漏电流
公开(公告)号：US6046932A
公开(公告)日：2000-04-04
申请号：US417273
申请日：1999-10-13
申请人： Colin Bill , Sameer S. Haddad , Jonathan Shi-Chang Su , Vei-Han Chan
发明人： Colin Bill , Sameer S. Haddad , Jonathan Shi-Chang Su , Vei-Han Chan
IPC分类号： G11C16/06 , G11C16/02 , G11C16/30 , G11C16/34 , H01L21/8247 , H01L27/115 , G11C16/12 , G11C16/16
CPC分类号： G11C16/3409 , G11C16/30 , G11C16/3404
摘要： A method of and a flash memory device for quenching bitline leakage current during programming and over-erase correction operations. The flash memory cells are organized in an array of I/O blocks with each block having columns and rows. An array of resistors is connected between the common array source connection and ground. The array of resistors is made up of sets of resistors, each set having a programming mode resistor and an APDE mode resistor. A data buffer switches either a programming mode resistor or APDE mode resistor into the circuit when a bitline is selected for either programming or APDE. The values of the resistors are selected to raise the voltage at the source above a selected threshold voltage of the memory cells so that over-erased cells will not provide leakage current to the bitline during either programming or APDE.
摘要翻译：一种用于在编程和过擦除校正操作期间淬灭位线泄漏电流的闪存器件的方法和闪存器件。闪存单元被组织成具有每个块具有列和行的I / O块的阵列。公共阵列源连接和地之间连接一组电阻。电阻器阵列由电阻器组成，每组具有编程模式电阻器和APDE模式电阻器。当选择编程或APDE的位线时，数据缓冲区将编程模式电阻器或APDE模式电阻器切换到电路中。选择电阻器的值以将源极处的电压提高到存储器单元的选定阈值电压以上，使得在编程或APDE期间，过擦除的单元将不会向位线提供泄漏电流。

4. 发明授权

US06236596B1 Biasing method and structure for reducing band-to-band and/or avalanche currents during the erase of flash memory devices 有权
标题翻译：在擦除闪速存储器件期间减少带 - 带和/或雪崩电流的偏置方法和结构
公开(公告)号：US06236596B1
公开(公告)日：2001-05-22
申请号：US09461376
申请日：1999-12-15
申请人： Daniel Sobek , Timothy James Thurgate , Scott D. Luning , Vei-Han Chan , Sameer S. Haddad
发明人： Daniel Sobek , Timothy James Thurgate , Scott D. Luning , Vei-Han Chan , Sameer S. Haddad
IPC分类号： G11C1134
CPC分类号： G11C16/14
摘要： A method and apparatus for reducing band-to-band currents during the erasure of a flash EEPROM memory cell is provided. The apparatus has a back biasing connection on the substrate at which a biasing voltage is applied during erasure of the flash EEPROM memory cell. The method of applying the biasing voltage to the back biasing connection during erasure of the flash EEPROM memory cell reduces band-to-band current between the source region and the substrate during erasure of the flash memory cell. This reduction provides for gate size reduction in flash memory cells without inducing detrimental short channel effects.
摘要翻译：提供了一种用于在快速EEPROM存储单元的擦除期间减小带 - 带电流的方法和装置。该装置在衬底上具有背偏压连接，在擦除EEPROM存储单元期间施加偏置电压。在闪存EEPROM存储单元擦除期间将偏置电压施加到反向偏置连接的方法在擦除闪速存储单元期间减少源区和衬底之间的带间电流。这种减少提供了闪存单元的栅极尺寸减小，而不会引起有害的短沟道效应。

5. 发明授权

US6005808A Biasing method and structure for reducing band-to-band and/or avalanche currents during the erase of flash memory devices 失效
公开(公告)号：US6005808A
公开(公告)日：1999-12-21
申请号：US993570
申请日：1997-12-18
申请人： Daniel Sobek , Timothy James Thurgate , Scott D. Luning , Vei-Han Chan , Sameer S. Haddad
发明人： Daniel Sobek , Timothy James Thurgate , Scott D. Luning , Vei-Han Chan , Sameer S. Haddad
摘要： A method and apparatus for reducing band-to-band currents during the erasure of a flash EEPROM memory cell is provided. The apparatus has a back biasing connection on the substrate at which a biasing voltage is applied during erasure of the flash EEPROM memory cell. The method of applying the biasing voltage to the back biasing connection during erasure of the flash EEPROM memory cell reduces band-to-band current between the source region and the substrate during erasure of the flash memory cell. This reduction provides for gate size reduction in flash memory cells without inducing detrimental short channel effects.

6. 发明授权

US07696018B2 Methods for fabricating multi-terminal phase change devices 有权
标题翻译：制造多端相变装置的方法
公开(公告)号：US07696018B2
公开(公告)日：2010-04-13
申请号：US12116911
申请日：2008-05-07
申请人： Antonietta Oliva , Louis Charles Kordus, II , Narbeh Derharcobian , Vei-Han Chan , Thomas E. Stewart, Jr.
发明人： Antonietta Oliva , Louis Charles Kordus, II , Narbeh Derharcobian , Vei-Han Chan , Thomas E. Stewart, Jr.
IPC分类号： H01L21/06 , H01L45/00
CPC分类号： H01L45/1683 , H01L45/06 , H01L45/1206 , H01L45/122 , H01L45/1226 , H01L45/126
摘要： Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. The programming control can be placed outside of the main signal path through the phase change device, reducing the impact of the associated capacitance and resistance of the device.
摘要翻译：相变装置，特别是多端子相变装置，包括通过相变材料桥接在一起的第一和第二有源端子，该相变材料的导电性可以根据施加到控制电极的控制信号进行修改。这种结构允许在两个有效端子之间可以产生电连接的应用，连接的控制使用单独的终端或终端实现。因此，可以独立于两个有源端子之间的路径的电阻来增加加热器元件的电阻。这允许使用较小的加热器元件，因此需要较少的电流以在每单位面积上产生相同量的焦耳加热。加热元件的电阻不影响相变装置的总电阻。编程控制可以通过相变装置放置在主信号路径之外，减少相关电容和器件电阻的影响。

7. 发明授权

US06674669B2 Nonvolatile memory structures and access methods 有权
标题翻译：非易失性存储器结构和访问方法
公开(公告)号：US06674669B2
公开(公告)日：2004-01-06
申请号：US10268863
申请日：2002-10-09
申请人： Hsing T. Tuan , Li-Chun Li , Vei-Han Chan
发明人： Hsing T. Tuan , Li-Chun Li , Vei-Han Chan
IPC分类号： G11C1134
CPC分类号： G11C16/08 , G11C8/08
摘要： In each row of a nonvolatile memory array, the select gates of all the memory cells are connected together and are used to select a row for memory access. The control gates of each row are also connected together, and the source regions of each row are connected together. Also, the control gates of plural rows are connected together, and the source regions of plural rows are connected together, but if the source regions of two rows are connected together, then their control gates are not connected together. If one of the two rows is being accessed but the other one of the two rows is not being accessed, their control gates are driven to different voltages, reducing the probability of a punch-through in the non-accessed row.
摘要翻译：在非易失性存储器阵列的每行中，所有存储器单元的选择栅极连接在一起，并用于选择用于存储器存取的行。每行的控制栅极也连接在一起，并且每行的源极区域连接在一起。此外，多行的控制栅极连接在一起，并且多行的源极区域连接在一起，但是如果两行的源极区域连接在一起，则它们的控制栅极不连接在一起。如果两行中的一个被访问，但是两行中的另一行未被访问，则它们的控制栅极被驱动到不同的电压，从而降低在未访问行中穿透的可能性。

8. 发明授权

US06660585B1 Stacked gate flash memory cell with reduced disturb conditions 有权
标题翻译：具有减少干扰条件的堆叠式门闪存单元
公开(公告)号：US06660585B1
公开(公告)日：2003-12-09
申请号：US09531787
申请日：2000-03-21
申请人： Peter W. Lee , Hsing-Ya Tsao , Vei-Han Chan , Hung-Sheng Chen , Fu-Chang Hsu
发明人： Peter W. Lee , Hsing-Ya Tsao , Vei-Han Chan , Hung-Sheng Chen , Fu-Chang Hsu
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , G11C16/0416 , H01L21/28273
摘要： In this invention a stacked gate flash memory cell is disclosed which has a lightly doped drain (LDD) on the drain side of the device and uses the source to both program using hot electron generation and erase the floating gate using Fowler-Nordheim-tunneling. Disturb conditions are reduced by taking advantage of the LDD and the biasing of the cell that uses the source for both programming and erasure. The electric field of the drain is greatly reduced as a result of the LDD which reduces hot electron generation. The LDD also helps reduce bit line disturb conditions during programming. A transient bit line disturb condition in a non-selected cell is minimized by preconditioning the bit line to the non-selected cell to Vcc.
摘要翻译：在本发明中，公开了一种堆叠栅极闪存单元，其在器件的漏极侧具有轻掺杂漏极（LDD），并且使用源使用热电子发生进行编程并使用Fowler-Nordheim隧道擦除浮动栅极。通过利用LDD和使用源进行编程和擦除的单元的偏置来减少干扰条件。作为减少热电子产生的LDD的结果，漏极的电场大大减小。 LDD还有助于在编程期间减少位线干扰条件。通过将未选择的单元的位线预处理为Vcc，使未选择的单元中的瞬态位线干扰条件最小化。

9. 发明授权

US6103602A Method and system for providing a drain side pocket implant 失效
标题翻译：用于提供排水侧口袋植入物的方法和系统
公开(公告)号：US6103602A
公开(公告)日：2000-08-15
申请号：US992618
申请日：1997-12-17
申请人： Timothy J. Thurgate , Vei-Han Chan
发明人： Timothy J. Thurgate , Vei-Han Chan
IPC分类号： H01L21/8238
CPC分类号： H01L29/7881 , H01L29/0847 , H01L29/66825 , H01L21/823412
摘要： A system and method for providing a memory cell on a semiconductor is disclosed. The memory cell has a source and a drain. The method and system include providing a source implant in the semiconductor, providing a pocket implant in the semiconductor, and providing a drain implant in the semiconductor after the pocket implant is provided. Thus, short channel effects are reduced.
摘要翻译：公开了一种在半导体上提供存储单元的系统和方法。存储单元具有源极和漏极。该方法和系统包括在半导体中提供源植入物，在半导体中提供凹穴注入，以及在提供口袋植入物之后在半导体中提供漏极注入。因此，短通道效应降低。

10. 发明授权

US5856946A Memory cell programming with controlled current injection 失效
标题翻译：采用可控电流注入的存储单元编程
公开(公告)号：US5856946A
公开(公告)日：1999-01-05
申请号：US831571
申请日：1997-04-09
申请人： Vei-Han Chan , Sameer Haddad , Chi Chang
发明人： Vei-Han Chan , Sameer Haddad , Chi Chang
IPC分类号： G11C16/12 , G11C16/04
CPC分类号： G11C16/12
摘要： A memory with controlled gate current injection during memory cell programming wherein programming circuitry applies a time-varying voltage to a control gate of the memory cell during a programming cycle. The time-varying voltage yields a substantially constant rate of electron flow from the channel region to the floating gate during the programming cycle.
摘要翻译：在存储器单元编程期间具有受控栅极电流注入的存储器，其中编程电路在编程周期期间将时变电压施加到存储器单元的控制栅极。在编程周期期间，随时间变化的电压产生从通道区域到浮动栅极的电子流量的基本恒定的速率。

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