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1. 发明申请

WO2015050787A1 THREE-DIMENSIONAL NAND MEMORY WITH ADAPTIVE ERASE 审中-公开
标题翻译：具有自适应擦除的三维NAND存储器
公开(公告)号：WO2015050787A1
公开(公告)日：2015-04-09
申请号：PCT/US2014/057697
申请日：2014-09-26
申请人： SANDISK TECHNOLOGIES INC.
发明人： RAGHU, Deepak , DUSIJA, Gautam Ashok , AVILA, Chris Nga Yee , DONG, Yingda , MUI, Man Lung , KOH, Pao-Ling
IPC分类号： G11C11/56 , G11C16/16 , G11C16/34 , G11C16/04
CPC分类号： G11C16/16 , G11C11/5635 , G11C16/0483 , G11C16/3445
摘要： Erasing memory cells in certain 3-D NAND charge-storage memory arrays is achieved by rapidly charging vertical conductors using Gate Induced Drain Leakage (GIDL) current generated in select transistors. When bit line voltage drops below its nominal value, select line voltage is controlled to maintain a constant voltage difference between bit line voltage and select line voltage thus maintaining a gate-drain voltage difference in select transistors that provides sufficient GIDL current for erase.
摘要翻译：通过在选择晶体管中产生的栅极引入漏极泄漏（GIDL）电流快速对垂直导体进行充电来实现对某些3-D NAND电荷存储器阵列的擦除存储单元。当位线电压降到其标称值以下时，选择线电压被控制，以保持位线电压和选择线电压之间的恒定电压差，从而保持提供足够的GIDL电流进行擦除的选择晶体管中的栅 - 漏电压差。

2. 发明申请

WO2015094707A1 ASYMMETRIC STATE DETECTION FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：非挥发性储存的非对称状态检测
公开(公告)号：WO2015094707A1
公开(公告)日：2015-06-25
申请号：PCT/US2014/068717
申请日：2014-12-05
申请人： SANDISK TECHNOLOGIES INC.
发明人： PATEL, Rohan , KOH, Pao-Ling , TAM, Eugene
IPC分类号： G11C11/56 , G11C16/34 , G11C29/02
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C16/26 , G11C16/3454 , G11C29/025 , G11C2029/1202 , G11C2211/5621
摘要： Techniques are disclosed herein for determining whether there is a defect that occurred as a result of programming non-volatile storage elements. Example defects include: broken word lines, control gate to substrate shorts, word line to word line shorts, double writes, etc. The memory cells may be programmed such that there will be a substantially even distribution of the memory cells in different data states. After programming, the memory cells are sensed at one or more reference levels. Two sub-groups of memory cells are strategically formed based on the sensing to enable detection of defects in a simple and efficient manner. The sub-groups may have a certain degree of separation of the data states to avoid missing a defect. The number of memory cells in one sub-group is compared with the other. If there is a significant imbalance between the two sub-groups, then a defect is detected.
摘要翻译：本文公开了用于确定是否存在作为编程非易失性存储元件的结果而发生的缺陷的技术。示例性缺陷包括：破碎的字线，控制栅极到衬底短路，字线到字线短路，双写等。存储器单元可以被编程，使得在不同数据状态下将存在基本均匀的存储器单元的分布。在编程之后，在一个或多个参考级别感测存储器单元。基于感测来战略地形成两个存储单元子组，以便以简单和有效的方式检测缺陷。子组可能具有一定程度的数据状态分离，以避免丢失缺陷。将一个子组中的存储单元的数量与另一个子组进行比较。如果两个子组之间存在显着的不平衡，则检测到缺陷。

3. 发明申请

WO2013130230A1 SAVING OF DATA IN CASES OF WORD-LINE TO WORD-LINE SHORT IN MEMORY ARRAYS 审中-公开
标题翻译：在存储器阵列中保存字线数据到字线短路的数据
公开(公告)号：WO2013130230A1
公开(公告)日：2013-09-06
申请号：PCT/US2013/024977
申请日：2013-02-06
申请人： SANDISK TECHNOLOGIES INC.
发明人： KOH, Pao-Ling , KUO, Tien-Chien
IPC分类号： G11C11/56 , G11C16/10 , G11C29/02
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5685 , G11C29/025 , G11C2029/1202
摘要： Techniques of operating a non-volatile memory are presented so that data that would otherwise be lost in the case of a word line to word line short are preserved. Before writing a word line, the data from a previously written adjacent word line are read back and stored in data latches that are associated with the corresponding bit lines but not being used for the data to be written. If a short occurs, as the data for both word lines are still in the latches, they can be written to a new location. This technique can also be incorporated into cache write operations and for a binary write operation performed while a multi-state write operation is suspended.
摘要翻译：呈现操作非易失性存储器的技术，使得在字线到字线短的情况下否则将丢失的数据被保留。在写入字线之前，来自先前写入的相邻字线的数据被读回并存储在与相应位线相关联但不用于要写入的数据的数据锁存器中。如果发生短路，因为两个字线的数据仍然在锁存器中，所以它们可以写入新的位置。这种技术也可以并入高速缓存写入操作以及在多状态写入操作被暂停时执行的二进制写入操作。

4. 发明申请

WO2015002897A1 WRITE OPERATIONS FOR DEFECT MANAGEMENT IN NONVOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器中的缺陷管理的写操作
公开(公告)号：WO2015002897A1
公开(公告)日：2015-01-08
申请号：PCT/US2014/044937
申请日：2014-06-30
申请人： SANDISK TECHNOLOGIES INC.
发明人： AVILA, Chris, Nga Yee , DUSIJA, Gautam, Ashok , CHEN, Jian , KOCHAR, Mrinal , MANOHAR, Abhijeet , MAK, Alexander, Kwok-Tung , LEE, Seungpil , KOH, Pao-Ling
IPC分类号： G11C11/56 , G11C16/34 , G11C16/10
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C2211/5621 , G11C2211/5641 , G11C2216/20
摘要： Data that is stored in a higher error rate format in a nonvolatile memory is backed up in a lower error rate format. Data to be stored may be transferred once to on-chip data latches where it is maintained while it is programmed in both the high error rate format and the low error rate format without being resent to the nonvolatile memory. Storage to a block in the high error rate format may be suspended to allow read out of a previously written high error rate block for error checking (post-write read).
摘要翻译：在非易失性存储器中以较高错误率格式存储的数据以较低的错误率格式进行备份。要被存储的数据可以被传送到片上数据锁存器，其中它被维护，同时以高错误率格式和低错误率格式被编程，而不重新发送到非易失性存储器。以高错误率格式存储到块可能被暂停，以允许读出先前写入的高错误率块用于错误检查（写入后读取）。

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