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1. 发明申请

US20140085959A1 3D MEMORY CONFIGURABLE FOR PERFORMANCE AND POWER 有权
标题翻译： 3D内存可配置性能和功耗
公开(公告)号：US20140085959A1
公开(公告)日：2014-03-27
申请号：US13626720
申请日：2012-09-25
申请人： Ruchir Saraswat , Matthias Gries
发明人： Ruchir Saraswat , Matthias Gries
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , G11C5/025 , G11C7/10 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C2207/2227 , H01L24/16 , H01L25/0657 , H01L27/0688 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541
摘要： A 3D memory that is configurable for performance and power. An embodiment of a memory device includes a dynamic random-access memory (DRAM) including multiple memory dies, each memory die including multiple memory arrays, each memory array including peripheral logic circuits and a configurable logic. The memory device further includes a system element coupled with the DRAM, the system element including a memory controller. The memory controller is to provide for control of the configurable logic to provide for separate or shared peripheral logic circuits for one or more memory arrays, the configurable logic being configurable to enable or disable one or more of the peripheral logic circuits and to enable or disable one or more I/O connections between the memory arrays.
摘要翻译：可配置性能和功耗的3D内存。存储器件的实施例包括包括多个存储器管芯的动态随机存取存储器（DRAM），每个存储器管芯包括多个存储器阵列，每个存储器阵列包括外围逻辑电路和可配置逻辑。存储器件还包括与DRAM耦合的系统元件，系统元件包括存储器控制器。存储器控制器旨在提供对可配置逻辑的控制以提供用于一个或多个存储器阵列的单独或共享的外围逻辑电路，所述可配置逻辑可配置为启用或禁用外围逻辑电路中的一个或多个并启用或禁用存储器阵列之间的一个或多个I / O连接。

2. 发明授权

US09513692B2 Heterogenous memory access 有权
标题翻译：异构内存访问
公开(公告)号：US09513692B2
公开(公告)日：2016-12-06
申请号：US14030515
申请日：2013-09-18
申请人： Ruchir Saraswat , Matthias Gries , Nicholas P. Cowley
发明人： Ruchir Saraswat , Matthias Gries , Nicholas P. Cowley
IPC分类号： G06F1/32 , G06F3/06 , G06F12/02
CPC分类号： G06F1/3275 , G06F1/3225 , G06F3/0625 , G06F3/0644 , G06F3/0685 , G06F12/02 , G06F12/0246 , G06F2212/7201 , G06F2212/7202 , G06F2212/7211 , G11C5/025 , G11C5/14 , Y02D10/13 , Y02D10/14
摘要： A memory controller operable for selective memory access to areas of memory exhibiting different attributes leverages different memory capabilities that vary access speed, retention time and power consumption, among others. Different areas of memory have different attributes while remaining available to applications as a single contiguous range of addressable memory. The memory controller employs an operating mode that identifies operational priorities for a computing device, such as speed, power conservation, or efficiency. The memory controller identifies an area of memory based on an expected usage of the data stored in the area, for example an access frequency indicating future retrieval. The memory controller therefore selects areas of memory based on the operating mode and the expected usage of data to be stored in the area according to a heuristic that favors areas of memory based on those exhibiting attributes having a high correspondence to the expected usage of the data.
摘要翻译：存储器控制器可操作用于对显示不同属性的存储器区域的选择性存储器访问，利用改变存取速度，保留时间和功耗的不同存储器能力等。存储器的不同区域具有不同的属性，而作为可寻址存储器的单个连续范围，可用于应用。存储器控制器采用识别计算设备的操作优先级的操作模式，例如速度，功率节省或效率。存储器控制器基于存储在该区域中的数据的预期使用情况来识别存储器区域，例如指示将来检索的访问频率。因此，存储器控制器基于操作模式和存储在该区域中的数据的预期使用量，根据启发式方式来选择存储器区域，该启发式方法基于那些呈现与数据的预期使用高度对应的属性的那些，。

3. 发明授权

US09195577B2 Dynamic operations for 3D stacked memory using thermal data 有权
标题翻译：使用热数据的3D堆叠内存的动态操作
公开(公告)号：US09195577B2
公开(公告)日：2015-11-24
申请号：US13995899
申请日：2011-09-30
申请人： Ruchir Saraswat , Matthias Gries
发明人： Ruchir Saraswat , Matthias Gries
IPC分类号： G06F12/00 , G11C7/04 , G11C11/406 , G11C5/02 , G06F1/20
CPC分类号： G06F12/00 , G06F1/206 , G11C5/025 , G11C7/04 , G11C11/40622 , G11C11/40626
摘要： Dynamic operations for operations for 3D stacked memory using thermal data. An embodiment of a memory device includes memory having multiple coupled memory elements and multiple thermal sensors, including a first thermal sensor in a first area of the memory stack and a second thermal sensor in a second area of the memory stack. A memory controller is to provide operations to modify thermal conditions of the memory elements based at least in part on thermal information generated by the thermal sensors.
摘要翻译：使用热量数据的3D堆叠存储器的操作的动态操作。存储器件的实施例包括具有多个耦合的存储器元件和多个热传感器的存储器，所述多个热传感器包括存储器堆叠的第一区域中的第一热传感器和存储器堆叠的第二区域中的第二热传感器。存储器控制器至少部分地基于由热传感器产生的热信息来提供操作来修改存储元件的热条件。

4. 发明授权

US08737108B2 3D memory configurable for performance and power 有权
标题翻译： 3D内存可配置为性能和功耗
公开(公告)号：US08737108B2
公开(公告)日：2014-05-27
申请号：US13626720
申请日：2012-09-25
申请人： Ruchir Saraswat , Matthias Gries
发明人： Ruchir Saraswat , Matthias Gries
IPC分类号： G11C5/02 , G11C5/04
CPC分类号： G11C5/063 , G11C5/025 , G11C7/10 , G11C11/4074 , G11C11/4076 , G11C11/4097 , G11C2207/2227 , H01L24/16 , H01L25/0657 , H01L27/0688 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541
摘要： A 3D memory that is configurable for performance and power. An embodiment of a memory device includes a dynamic random-access memory (DRAM) including multiple memory dies, each memory die including multiple memory arrays, each memory array including peripheral logic circuits and a configurable logic. The memory device further includes a system element coupled with the DRAM, the system element including a memory controller. The memory controller is to provide for control of the configurable logic to provide for separate or shared peripheral logic circuits for one or more memory arrays, the configurable logic being configurable to enable or disable one or more of the peripheral logic circuits and to enable or disable one or more I/O connections between the memory arrays.
摘要翻译：可配置性能和功耗的3D内存。存储器件的实施例包括包括多个存储器管芯的动态随机存取存储器（DRAM），每个存储器管芯包括多个存储器阵列，每个存储器阵列包括外围逻辑电路和可配置逻辑。存储器件还包括与DRAM耦合的系统元件，系统元件包括存储器控制器。存储器控制器旨在提供对可配置逻辑的控制以提供用于一个或多个存储器阵列的单独或共享的外围逻辑电路，所述可配置逻辑可配置为启用或禁用外围逻辑电路中的一个或多个并启用或禁用存储器阵列之间的一个或多个I / O连接。

5. 发明申请

US20150082062A1 HETEROGENOUS MEMORY ACCESS 有权
标题翻译：异构存储器访问
公开(公告)号：US20150082062A1
公开(公告)日：2015-03-19
申请号：US14030515
申请日：2013-09-18
申请人： Ruchir Saraswat , Matthias Gries , Nicholas P. Cowley
发明人： Ruchir Saraswat , Matthias Gries , Nicholas P. Cowley
IPC分类号： G06F1/32 , G06F3/06
CPC分类号： G06F1/3275 , G06F1/3225 , G06F3/0625 , G06F3/0644 , G06F3/0685 , G06F12/02 , G06F12/0246 , G06F2212/7201 , G06F2212/7202 , G06F2212/7211 , G11C5/025 , G11C5/14 , Y02D10/13 , Y02D10/14
摘要： A memory controller operable for selective memory access to areas of memory exhibiting different attributes leverages different memory capabilities that vary access speed, retention time and power consumption, among others. Different areas of memory have different attributes while remaining available to applications as a single contiguous range of addressable memory. The memory controller employs an operating mode that identifies operational priorities for a computing device, such as speed, power conservation, or efficiency. The memory controller identifies an area of memory based on an expected usage of the data stored in the area, for example an access frequency indicating future retrieval. The memory controller therefore selects areas of memory based on the operating mode and the expected usage of data to be stored in the area according to a heuristic that favors areas of memory based on those exhibiting attributes having a high correspondence to the expected usage of the data.
摘要翻译：存储器控制器可操作用于对显示不同属性的存储器区域的选择性存储器访问，利用改变存取速度，保留时间和功耗的不同存储器能力等。存储器的不同区域具有不同的属性，而作为可寻址存储器的单个连续范围，可用于应用。存储器控制器采用识别计算设备的操作优先级的操作模式，例如速度，功率节省或效率。存储器控制器基于存储在该区域中的数据的预期使用情况来识别存储器区域，例如指示将来检索的访问频率。因此，存储器控制器基于操作模式和存储在该区域中的数据的预期使用量，根据启发式方式来选择存储器区域，该启发式方法基于那些呈现与数据的预期使用高度对应的属性的那些，。

6. 发明申请

US20130275665A1 DYNAMIC OPERATIONS FOR 3D STACKED MEMORY USING THERMAL DATA 有权
标题翻译：使用热数据的三维堆叠存储器的动态操作
公开(公告)号：US20130275665A1
公开(公告)日：2013-10-17
申请号：US13995899
申请日：2011-09-30
申请人： Ruchir Saraswat , Matthias Gries
发明人： Ruchir Saraswat , Matthias Gries
IPC分类号： G06F12/00
CPC分类号： G06F12/00 , G06F1/206 , G11C5/025 , G11C7/04 , G11C11/40622 , G11C11/40626
摘要： Dynamic operations for operations for 3D stacked memory using thermal data. An embodiment of a memory device includes memory having multiple coupled memory elements and multiple thermal sensors, including a first thermal sensor in a first area of the memory stack and a second thermal sensor in a second area of the memory stack. A memory controller is to provide operations to modify thermal conditions of the memory elements based at least in part on thermal information generated by the thermal sensors.
摘要翻译：使用热量数据的3D堆叠存储器的操作的动态操作。存储器件的实施例包括具有多个耦合的存储器元件和多个热传感器的存储器，所述多个热传感器包括存储器堆叠的第一区域中的第一热传感器和存储器堆叠的第二区域中的第二热传感器。存储器控制器至少部分地基于由热传感器产生的热信息来提供操作来修改存储元件的热条件。

7. 发明申请

US20050174102A1 On-chip analysis & computation of transition behaviour of embedded nets in integrated circuits 有权
标题翻译：集成电路中嵌入式网络的过渡行为的片上分析与计算
公开(公告)号：US20050174102A1
公开(公告)日：2005-08-11
申请号：US11025854
申请日：2004-12-29
申请人： Ruchir Saraswat , Balwant Singh , Prashant Dubey
发明人： Ruchir Saraswat , Balwant Singh , Prashant Dubey
IPC分类号： G01R19/00 , G01R31/28 , G01R31/30
CPC分类号： G01R31/2884 , G01R31/3004
摘要： An apparatus for enabling the on-chip analysis of the voltage and/or current transition behaviour of one or more embedded nets of an integrated circuit independently of the fabrication process. The said apparatus comprises a Reference Step Generator (RSG) for providing programmable reference voltages or currents, a Step Delay Generator (SDG) for providing programmable delays, a Comparator (C) that receives the output of the reference step generator on one input, the output from the node under test at the second input, and a latch enable signal from the step delay generator, and provides a latched digital output in response to the comparison, and a controller that co-ordinates the operation of the reference step generator, Step Delay Generator and Latching Comparator to provide a transient response measurement.
摘要翻译：一种用于独立于制造过程实现片上分析集成电路的一个或多个嵌入网络的电压和/或电流转换特性的装置。所述装置包括用于提供可编程参考电压或电流的参考步长发生器（RSG），用于提供可编程延迟的步进延迟发生器（SDG）;在一个输入端接收参考步进发生器的输出的比较器（C）在来自第二输入的被测节点的输出以及来自阶梯延迟发生器的锁存使能信号，并且响应于该比较而提供锁存的数字输出;以及控制器，其对参考步长发生器的操作进行调节，步骤延迟发生器和锁存比较器提供瞬态响应测量。

8. 发明申请

US20180004284A1 TECHNIQUES FOR OCULAR CONTROL 审中-公开
公开(公告)号：US20180004284A1
公开(公告)日：2018-01-04
申请号：US15201364
申请日：2016-07-01
申请人： Ruchir Saraswat , Nicholas Cowley , Richard Goldman , Patrick Gerard McGlew
发明人： Ruchir Saraswat , Nicholas Cowley , Richard Goldman , Patrick Gerard McGlew
IPC分类号： G06F3/01
CPC分类号： G06F3/013 , G06F3/015 , G06F3/048 , G06F3/0481
摘要： An ocular control system arranged to determine electric potentials associated with a set of sensor. The ocular control system may determine direction of gaze or motion based on the determined electric potentials. The determined direction of gaze or motion may be used to provide data input for a computing device.

9. 发明申请

US20110135027A1 CHAOTIC WIDE BAND FREQUENCY MODULATOR FOR NOISE REDUCTION 有权
标题翻译：用于噪声减少的气溶胶带频调制器
公开(公告)号：US20110135027A1
公开(公告)日：2011-06-09
申请号：US12631281
申请日：2009-12-04
申请人： Ruchir Saraswat , Andriy Gelman , Ulrich Bretthauer , Sunil Parmar , Rajashekar Manche , Chodimella Venkata Ramana , Shivraj G. Dharne
发明人： Ruchir Saraswat , Andriy Gelman , Ulrich Bretthauer , Sunil Parmar , Rajashekar Manche , Chodimella Venkata Ramana , Shivraj G. Dharne
IPC分类号： H04B15/00
CPC分类号： H03K3/84
摘要： The embodiments of the invention relate to apparatus and method for reducing electromagnetic interference (EMI) and radio frequency interference (RFI) in computer systems via a chaotic wide band frequency modulation. The chaotic noise modulator, in one embodiment, comprises: a master cell to generate a control voltage corresponding to an un-modulated reference signal; and a slave cell having a chaotic signal generator to generate a random noise signal, the slave cell coupled with the master cell and operable to generate a modulated output signal in response to the control voltage.
摘要翻译：本发明的实施例涉及通过混沌宽带频率调制来减少计算机系统中的电磁干扰（EMI）和射频干扰（RFI）的装置和方法。在一个实施例中，混沌噪声调制器包括：主单元，用于产生对应于未调制参考信号的控制电压; 以及具有混沌信号发生器以产生随机噪声信号的从单元，所述从单元与主单元耦合并且可操作以响应于控制电压产生调制的输出信号。

10. 发明授权

US07242179B2 Digital circuit for frequency and timing characterization 有权
标题翻译：用于频率和时序表征的数字电路
公开(公告)号：US07242179B2
公开(公告)日：2007-07-10
申请号：US11023054
申请日：2004-12-27
申请人： Ruchir Saraswat , Balwant Singh , Hina Mushir
发明人： Ruchir Saraswat , Balwant Singh , Hina Mushir
IPC分类号： G01R31/28
CPC分类号： G01R31/31727 , G01R31/31922
摘要： A digital circuit operating frequency characterizer provides a combination of frequency and duty cycle characterization. The digital circuit operating frequency characterizer includes a programmable frequency generator, a programmable edge variator, a test engine, and a control circuit. The programmable frequency generator provides one or more output signals, and the programmable edge variator is coupled to one or more outputs of the programmable frequency generator for adjusting duty cycle. The test engine uses the outputs from the programmable edge variator and/or programmable frequency generator to apply a defined test signal sequence to a circuit under test and produce a status output after evaluating the outputs received from the circuit under test. The control circuit is connected to the control inputs of the programmable frequency generator, programmable edge variator, and the status output of the test engine. The control circuit synchronizes their operations and performs the combination of frequency and duty cycle characterization.
摘要翻译：数字电路工作频率表征器提供频率和占空比表征的组合。数字电路工作频率表征器包括可编程频率发生器，可编程边缘变换器，测试引擎和控制电路。可编程频率发生器提供一个或多个输出信号，并且可编程边缘变换器耦合到可编程频率发生器的一个或多个输出端，用于调整占空比。测试引擎使用可编程边沿变换器和/或可编程频率发生器的输出，将定义的测试信号序列应用于被测电路，并在评估从被测电路接收的输出后产生状态输出。控制电路连接到可编程频率发生器，可编程边沿变换器和测试引擎的状态输出的控制输入。控制电路使其操作同步并执行频率和占空比表征的组合。

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