专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050136605A1 MOS transistor gates with thin lower metal silicide and methods for making the same 有权
标题翻译：具有薄的下金属硅化物的MOS晶体管栅极及其制造方法
公开(公告)号：US20050136605A1
公开(公告)日：2005-06-23
申请号：US10745454
申请日：2003-12-22
申请人： Robert Murto , Luigi Colombo , Mark Visokay
发明人： Robert Murto , Luigi Colombo , Mark Visokay
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L21/3205 , H01L21/44
CPC分类号： H01L29/4975 , H01L21/28097 , H01L21/823835 , H01L29/665 , H01L29/6659
摘要： Methods are presented for fabricating transistor gate structures, wherein upper and lower metal suicides are formed above a gate dielectric. In one example, the lower silicide is formed by depositing a thin first silicon-containing material over the gate dielectric, which is implanted and then reacted with a first metal by annealing to form the lower silicide. A capping layer can be formed over the first metal prior to annealing, to prevent oxidation of the metal prior to silicidation, and a barrier layer can be formed over the lower silicide to prevent reaction with subsequently formed silicon material. In another example, the lower silicide is a multilayer silicide structure including a plurality of metal silicide sublayers.
摘要翻译：呈现用于制造晶体管栅极结构的方法，其中上和下金属硅化物形成在栅极电介质上方。在一个示例中，下硅化物通过在栅极电介质上沉积薄的第一含硅材料而形成，其被注入，然后通过退火与第一金属反应以形成下硅化物。在退火之前可以在第一金属上形成覆盖层，以防止在硅化物之前金属的氧化，并且可以在下硅化物上形成阻挡层以防止随后形成的硅材料的反应。在另一个实例中，下硅化物是包括多个金属硅化物层的多层硅化物结构。

2. 发明申请

US20060019437A1 Dual work function gate electrodes obtained through local thickness-limited silicidation 有权
标题翻译：通过局部厚度限制硅化获得的双功能功能栅电极
公开(公告)号：US20060019437A1
公开(公告)日：2006-01-26
申请号：US10897846
申请日：2004-07-23
申请人： Robert Murto , Luigi Colombo , Mark Visokay
发明人： Robert Murto , Luigi Colombo , Mark Visokay
IPC分类号： H01L21/8238
CPC分类号： H01L21/823835 , H01L21/823842
摘要： The present invention provides a method of manufacturing a semiconductor device. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first transistor (120) has a gate electrode (135) that includes a metal silicide layer 135a over which is located a silicon gate layer (135b) together which have a work function associated therewith, and a second transistor (125) located over the semiconductor substrate (110) and proximate the first transistor (120), wherein the second transistor (125) also includes a gate electrode (160) that includes a metal silicide layer (160a) over which is located a silicon gate layer (160b) together which have a different work function from that of the first gate electrode (135) associated therewith.
摘要翻译：本发明提供一种制造半导体器件的方法。除了其它可能的元件之外，半导体器件（100）包括位于半导体衬底（110）上方的第一晶体管（120），其中第一晶体管（120）具有包括金属硅化物层135a的栅电极（135）位于硅栅极层（135b）上，其具有与其相关联的功函数;以及第二晶体管（125），位于半导体衬底（110）之上且靠近第一晶体管（120），其中第二晶体管 125）还包括栅电极（160），其包括金属硅化物层（160a），栅极电极（160a）位于硅栅极层（160b）上，其具有与第一栅电极（135）的功函数不同的功函随之而来。

3. 发明申请

US20080044957A1 WORK FUNCTION CONTROL OF METALS 有权
标题翻译：金属的工作功能控制
公开(公告)号：US20080044957A1
公开(公告)日：2008-02-21
申请号：US11870631
申请日：2007-10-11
申请人： James Chambers , Mark Visokay , Luigi Colombo , Antonio Rotondaro
发明人： James Chambers , Mark Visokay , Luigi Colombo , Antonio Rotondaro
IPC分类号： H01L21/84
CPC分类号： H01L21/823842
摘要： Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.
摘要翻译：公开了具有不同功函数的金属栅极晶体管。在一个示例中，第一金属是“中间间隙”金属，分别在第一和第二区域中被第二和第三金属操纵，以在不同区域中沿相反方向移动第一金属的功函数。在不同区域中产生的功函数对应于将要形成的不同类型的晶体管。

4. 发明申请

US20070122962A1 Semiconductor CMOS Devices and Methods with NMOS High-K Dielectric Present in Core Region that Mitigate Damage to Dielectric Materials 有权
标题翻译：半导体CMOS器件和方法与NMOS High-K介质存在于核心区域，减轻对介质材料的损害
公开(公告)号：US20070122962A1
公开(公告)日：2007-05-31
申请号：US11620447
申请日：2007-01-05
申请人： James Chambers , Mark Visokay , Luigi Colombo
发明人： James Chambers , Mark Visokay , Luigi Colombo
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842 , Y10S438/981
摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device. A core dielectric layer is formed in the core region (510). A barrier layer is deposited and patterned to expose the NMOS devices of the core region (512). The core dielectric layer is removed from the core NMOS devices (514). A high-k dielectric layer is formed (514) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions/devices of the core region and the NMOS and PMOS regions/devices of the I/O region.
摘要翻译：本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。在半导体器件（506）的芯和I / O区域中形成I / O电介质层。从器件的芯区域去除（508）I / O电介质层。在芯区域（510）中形成芯介质层。屏蔽层被沉积并图案化以暴露核心区域（512）的NMOS器件。从核心NMOS器件（514）去除芯介质层。在核心和I / O区域上形成高k电介质层（514）。然后，从核心区域的PMOS区域/器件和I / O区域的NMOS和PMOS区域/器件去除高k电介质层（512）。

5. 发明申请

US20070037343A1 Process for manufacturing dual work function metal gates in a microelectronics device 有权
公开(公告)号：US20070037343A1
公开(公告)日：2007-02-15
申请号：US11200741
申请日：2005-08-10
申请人： Luigi Colombo , James Chambers , Mark Visokay
发明人： Luigi Colombo , James Chambers , Mark Visokay
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L29/66545
摘要： The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315a and 315b. The nMOS and pMOS stacked gate structures 315a and 315b each comprise a gate dielectric 205, a first metal layer, 305 located over the gate dielectric 205 and a sacrificial gate layer 310 located over the first metal layer 305. The method further includes removing the sacrificial gate layer 310 in at least one of the nMOS or pMOS stacked gate structures, thereby forming a gate opening 825 and modifying the first metal layer 305 within the gate opening 825 to form a gate electrode with a desired work function.

6. 发明申请

US20050136589A1 Method for integrating high-k dielectrics in transistor devices 有权
标题翻译：在晶体管器件中集成高k电介质的方法
公开(公告)号：US20050136589A1
公开(公告)日：2005-06-23
申请号：US10738958
申请日：2003-12-17
申请人： Antonio Rotondaro , Douglas Mercer , Luigi Colombo , Mark Visokay , Haowen Bu , Malcolm Bevan
发明人： Antonio Rotondaro , Douglas Mercer , Luigi Colombo , Mark Visokay , Haowen Bu , Malcolm Bevan
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8242 , H01L29/51
CPC分类号： H01L21/28176 , H01L21/28194 , H01L29/517 , H01L29/518 , H01L29/6656 , H01L29/6659
摘要： Methods are disclosed that fabricating semiconductor devices with high-k dielectric layers. The invention removes portions of deposited high-k dielectric layers not below gates and covers exposed portions (e.g., sidewalls) of high-k dielectric layers during fabrication with an encapsulation layer, which mitigates defects in the high-k dielectric layers and contamination of process tools. The encapsulation layer can also be employed as an etch stop layer and, at least partially, in comprising sidewall spacers. As a result, a semiconductor device can be fabricated with a substantially uniform equivalent oxide thickness.
摘要翻译：公开了制造具有高k电介质层的半导体器件的方法。本发明除了不在门下方的沉积的高k电介质层的部分，并且在用封装层制造期间覆盖高k电介质层的暴露部分（例如，侧壁），这减轻了高k电介质层中的缺陷和工艺污染工具封装层也可以用作蚀刻停止层，并且至少部分地包括侧壁间隔物。结果，可以制造具有基本均匀的等效氧化物厚度的半导体器件。

7. 发明申请

US20050124121A1 Anneal of high-k dielectric using NH3 and an oxidizer 审中-公开
标题翻译：使用NH3和氧化剂的高k电介质的退火
公开(公告)号：US20050124121A1
公开(公告)日：2005-06-09
申请号：US10731647
申请日：2003-12-09
申请人： Antonio Rotondaro , James Chambers , Mark Visokay , Luigi Colombo
发明人： Antonio Rotondaro , James Chambers , Mark Visokay , Luigi Colombo
IPC分类号： C23C16/56 , H01L21/28 , H01L21/31 , H01L21/314 , H01L21/316 , H01L21/336 , H01L21/4763 , H01L21/8242 , H01L29/51
CPC分类号： H01L21/02318 , C23C16/56 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/3143 , H01L21/31641 , H01L21/31645 , H01L29/513 , H01L29/517 , H01L29/518
摘要： The present invention pertains to annealing a high dielectric constant (high-k) material in a manner that substantially reduces or eliminates disadvantages and problems heretofore associated with the same. In particular, the high-k material is annealed in an ambient having a single chemistry of nitrogen and hydrogen, such as ammonia (NH3), to nitride and react unwanted impurities, and an oxidizer to oxidize and densify the high-k material, while mitigating growth of a lower-k material at an interface of the high-k material and an underlying substrate. Additionally, particular temperatures and pressures are utilized within the process so that the risk of an undesired exothermic reaction is mitigated. Annealing the high-k material in accordance with manners disclosed herein has application to semiconductor fabrication processes and, as such, is discussed herein within the context of the same.
摘要翻译：本发明涉及以大大减少或消除与之相关的缺点和问题的方式退火高介电常数（高k）材料。特别地，高k材料在具有氮和氢的单一化学性质（例如氨（NH 3））的环境中退火至氮化物并反应不需要的杂质，以及氧化剂氧化和致密化高k材料，同时减轻在高k材料和下层衬底的界面处的较低k材料的生长。此外，在该方法中利用特定的温度和压力，以便减轻不期望的放热反应的风险。根据本文公开的方式对高k材料进行退火，已经应用于半导体制造工艺，并且因此本文在其上下文中讨论。

8. 发明申请

US20050101145A1 Semiconductor structure and method of fabrication 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20050101145A1
公开(公告)日：2005-05-12
申请号：US10703388
申请日：2003-11-06
申请人： Mark Visokay , Luigi Colombo
发明人： Mark Visokay , Luigi Colombo
IPC分类号： H01L21/302 , H01L21/461 , H01L21/8238
CPC分类号： H01L21/823842
摘要： Fabricating a semiconductor includes depositing a metal layer outwardly from a dielectric layer and forming a mask layer outwardly from a first portion of the metal layer. Atoms are incorporated into an exposed second portion of the metal layer to form a composition-altered portion of the metal layer. The mask layer is removed from the first portion of the metal layer and a barrier layer is deposited outwardly from the metal layer. A poly-Si layer is deposited outwardly from the barrier layer to form a semiconductor layer, where the barrier layer substantially prevents reaction of the metal layer with the poly-Si layer. The semiconductor layer is etched to form gate stacks, where each gate stack operates according to one of a plurality of work functions.
摘要翻译：制造半导体包括从电介质层向外沉积金属层并从金属层的第一部分向外形成掩模层。将原子并入金属层的暴露的第二部分中以形成金属层的组合物改变部分。掩模层从金属层的第一部分去除，并且阻挡层从金属层向外沉积。多晶硅层从阻挡层向外沉积形成半导体层，其中阻挡层基本上防止了金属层与多晶硅层的反应。蚀刻半导体层以形成栅极堆叠，其中每个栅极堆叠根据多个功函数中的一个工作。

9. 发明申请

US20070037335A1 Dual work function CMOS devices utilizing carbide based electrodes 有权
标题翻译：利用碳化物电极的双功能CMOS器件
公开(公告)号：US20070037335A1
公开(公告)日：2007-02-15
申请号：US11204235
申请日：2005-08-15
申请人： James Chambers , Luigi Colombo , Mark Visokay
发明人： James Chambers , Luigi Colombo , Mark Visokay
IPC分类号： H01L21/8234
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/4966
摘要： Concurrently forming different metal gate transistors having respective work functions is disclosed. In one example, a metal carbide, which has a relatively low work function, is formed over a semiconductor substrate. Oxygen and/or nitrogen are then added to the metal carbide in a second region to establish a second work function in the second region, where the metal carbide itself establishes a first work function in a first region. One or more first metal gate transistor types are then formed in the first region and one or more second metal gate transistor types are formed in the second region.
摘要翻译：同时形成具有各自功函数的不同金属栅极晶体管。在一个实例中，在半导体衬底上形成具有较低功函数的金属碳化物。然后在第二区域中将氧和/或氮添加到金属碳化物中以在第二区域中建立第二功函数，其中金属碳化物本身在第一区域中建立第一功函数。然后在第一区域中形成一个或多个第一金属栅极晶体管类型，并且在第二区域中形成一个或多个第二金属栅极晶体管类型。

10. 发明申请

US20060267119A1 REFRACTORY METAL-BASED ELECTRODES FOR WORK FUNCTION SETTING IN SEMICONDUCTOR DEVICES 有权
标题翻译：用于半导体器件中工作功能的基于金属的金属电极
公开(公告)号：US20060267119A1
公开(公告)日：2006-11-30
申请号：US11462573
申请日：2006-08-04
申请人： Luigi Colombo , James Chambers , Mark Visokay
发明人： Luigi Colombo , James Chambers , Mark Visokay
IPC分类号： H01L29/94
CPC分类号： H01L21/823842 , H01L29/4958
摘要： The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).
摘要翻译：本发明在一个实施例中提供一种栅极结构（100）。栅极结构包括栅极电介质（105）和栅极（110）。栅极电介质包括难熔金属并且位于半导体衬底（115）之上。半导体衬底具有导带和价带。栅极位于栅极电介质上方并且包括难熔金属。栅极具有与导带或价带对准的功函数。其他实施例包括替代栅极结构（200），形成用于半导体器件（301）的栅极结构（300）和双栅极集成电路（400）的方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式