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1. 发明授权

US07886244B2 Driving values to DC adjusted/untimed nets to identify timing problems 有权
标题翻译：将值驱动到DC调整/未定义的网络以识别时序问题
公开(公告)号：US07886244B2
公开(公告)日：2011-02-08
申请号：US12271588
申请日：2008-11-14
申请人： Robert B. Gass , Yee Ja , Christoph Jaeschke
发明人： Robert B. Gass , Yee Ja , Christoph Jaeschke
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5031
摘要： An apparatus and computer program product for driving values to “don't care” (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The apparatus and computer program product may be utilized, for example, with logical built-in self test (LBIST) testing of an integrated circuit in which the DC adjusted (dcadj) nets for normal functional mode of the integrated circuit may not be DC adjusted for LBIST mode. By using the apparatus and computer program product, timing related problems associated with DC adjusted/untimed nets can be made apparent either by using simulation or semi-formal/formal analysis. For example, with regard to DC adjusted/untimed nets, the apparatus and computer program product may identify any violations of these nets with regard to maintaining their DC adjusted values. Such identification of violations of DC adjusted/untimed nets may be made without interfering with the static timing analysis of timed nets.
摘要翻译：提供了一种用于驱动集成电路设计的“无关心”（DC）调整/未定型网络的值的装置和计算机程序产品，从而识别定时问题。该装置和计算机程序产品可以用于例如集成电路的逻辑内置自检（LBIST）测试，其中用于集成电路的正常功能模式的DC调节（dcadj）网络可能不被直流调整用于LBIST模式。通过使用设备和计算机程序产品，可以通过使用模拟或半正式/形式分析，使与DC调整/未定义网相关的定时相关问题变得明显。例如，关于DC调整/未定义的网络，设备和计算机程序产品可以识别关于维持其DC调整值的任何这些网络的违规。可以在不干扰定时网络的静态时序分析的情况下进行对DC调整/未定义网的违规的识别。

2. 发明申请

US20080016480A1 System and Method for Driving Values to DC Adjusted/Untimed Nets to Identify Timing Problems 失效
标题翻译：用于向直流调整/无源网络驱动价值以识别时序问题的系统和方法
公开(公告)号：US20080016480A1
公开(公告)日：2008-01-17
申请号：US11457865
申请日：2006-07-17
申请人： Robert B. Gass , Yee Ja , Christoph Jaeschke
发明人： Robert B. Gass , Yee Ja , Christoph Jaeschke
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A system and method for driving values to “don't care” (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The system and method may be utilized, for example, with logical built-in self test (LBIST) testing of an integrated circuit in which the DC adjusted (dcadj) nets for normal functional mode of the integrated circuit may not be DC adjusted for LBIST mode. By using the system and method, timing related problems associated with DC adjusted/untimed nets can be made apparent either by using simulation or semi-formal/formal analysis. For example, with regard to DC adjusted/untimed nets, the system and method may identify any violations of these nets with regard to maintaining their DC adjusted values. Such identification of violations of DC adjusted/untimed nets may be made without interfering with the static timing analysis of timed nets.
摘要翻译：提供了一种用于驱动集成电路设计的“无关心”（DC）调整/未定型网络的值以便识别定时问题的系统和方法。该系统和方法可以用于例如集成电路的逻辑内置自检（LBIST）测试，其中用于集成电路的正常功能模式的DC调节（dcadj）网络可以不被LB调整为LBIST 模式。通过使用系统和方法，通过使用模拟或半正规/形式分析，可以使与DC调整/未定义网相关的定时相关问题变得明显。例如，关于DC调整/未定义的网络，系统和方法可以识别关于维持其DC调整值的任何这些网络的违规。可以在不干扰定时网络的静态时序分析的情况下进行对DC调整/未定义网的违规的识别。

3. 发明申请

US20090132983A1 Driving Values to DC Adjusted/Untimed Nets to Identify Timing Problems 有权
标题翻译：向直流调整/未绑定网络驱动价值，以确定时序问题
公开(公告)号：US20090132983A1
公开(公告)日：2009-05-21
申请号：US12271588
申请日：2008-11-14
申请人： Robert B. Gass , Yee Ja , Christoph Jaeschke
发明人： Robert B. Gass , Yee Ja , Christoph Jaeschke
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An apparatus and computer program product for driving values to “don't care” (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The apparatus and computer program product may be utilized, for example, with logical built-in self test (LBIST) testing of an integrated circuit in which the DC adjusted (dcadj) nets for normal functional mode of the integrated circuit may not be DC adjusted for LBIST mode. By using the apparatus and computer program product, timing related problems associated with DC adjusted/untimed nets can be made apparent either by using simulation or semi-formal/formal analysis. For example, with regard to DC adjusted/untimed nets, the apparatus and computer program product may identify any violations of these nets with regard to maintaining their DC adjusted values. Such identification of violations of DC adjusted/untimed nets may be made without interfering with the static timing analysis of timed nets.
摘要翻译：提供了一种用于驱动集成电路设计的“无关心”（DC）调整/未定型网络的值的装置和计算机程序产品，从而识别定时问题。该装置和计算机程序产品可以用于例如集成电路的逻辑内置自检（LBIST）测试，其中用于集成电路的正常功能模式的DC调节（dcadj）网络可能不被直流调整用于LBIST模式。通过使用设备和计算机程序产品，可以通过使用模拟或半正式/形式分析，使与DC调整/未定义网相关的定时相关问题变得明显。例如，关于DC调整/未定义的网络，设备和计算机程序产品可以识别关于维持其DC调整值的任何这些网络的违规。可以在不干扰定时网络的静态时序分析的情况下进行对DC调整/未定义网的违规的识别。

4. 发明授权

US07490305B2 Method for driving values to DC adjusted/untimed nets to identify timing problems 失效
标题翻译：将值驱动到DC调整/未定义网络以识别时序问题的方法
公开(公告)号：US07490305B2
公开(公告)日：2009-02-10
申请号：US11457865
申请日：2006-07-17
申请人： Robert B. Gass , Yee Ja , Christoph Jaeschke
发明人： Robert B. Gass , Yee Ja , Christoph Jaeschke
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A method for driving values to “don't care” (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The system and method may be utilized, for example, with logical built-in self test (LBIST) testing of an integrated circuit in which the DC adjusted (dcadj) nets for normal functional mode of the integrated circuit may not be DC adjusted for LBIST mode. By using the system and method, timing related problems associated with DC adjusted/untimed nets can be made apparent either by using simulation or semi-formal/formal analysis. For example, with regard to DC adjusted/untimed nets, the system and method may identify any violations of these nets with regard to maintaining their DC adjusted values. Such identification of violations of DC adjusted/untimed nets may be made without interfering with the static timing analysis of timed nets.
摘要翻译：提供了一种用于驱动集成电路设计的“不关心”（DC）调整/未定网的值从而识别定时问题的方法。该系统和方法可以用于例如集成电路的逻辑内置自检（LBIST）测试，其中用于集成电路的正常功能模式的DC调节（dcadj）网络可以不被LB调整为LBIST 模式。通过使用系统和方法，通过使用模拟或半正规/形式分析，可以使与DC调整/未定义网相关的定时相关问题变得明显。例如，关于DC调整/未定义的网络，系统和方法可以识别关于维持其DC调整值的任何这些网络的违规。可以在不干扰定时网络的静态时序分析的情况下进行对DC调整/未定义网的违规的识别。

5. 发明申请

US20090138837A1 System and Method for Sequential Equivalence Checking for Asynchronous Verification 有权
标题翻译：用于异步验证的顺序等价检查的系统和方法
公开(公告)号：US20090138837A1
公开(公告)日：2009-05-28
申请号：US11945465
申请日：2007-11-27
申请人： Jason R. Baumgartner , Yee Ja , Hari Mony , Viresh Paruthi , Barinjato Ramanandray
发明人： Jason R. Baumgartner , Yee Ja , Hari Mony , Viresh Paruthi , Barinjato Ramanandray
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A system and method for performing sequential equivalence checking for asynchronous verification are provided. A first model of the integrated circuit design is provided that has additional logic in it to reflect the possible variance in behavior of the asynchronous crossings. A second model of the integrated circuit design is provided that does not have this asynchronous behavior logic but instead correlates to the simplest synchronous model that is usually used for non-asynchronous functional verification tasks. Sequential equivalence checking is performed to verify that the two models are input/output equivalent. In order to address non-uniform arrival times of bus strands, logic is provided for identifying bus strands that have transitioning bits, determining a representative delay for these strands, comparing the representative delays for all of the bus strands to determine the maximum delay for the entire bus, and applying this maximum delay to one of the models.
摘要翻译：提供了用于执行用于异步验证的顺序等同性检查的系统和方法。提供了集成电路设计的第一个模型，其具有额外的逻辑，以反映异步交叉的行为的可能方差。提供了集成电路设计的第二个模型，其不具有该异步行为逻辑，而是与通常用于非异步功能验证任务的最简单的同步模型相关联。执行顺序等价检查以验证两个模型是输入/输出等效的。为了解决总线链路的不均匀到达时间，提供了用于识别具有转换位的总线串的逻辑，确定这些线的代表性延迟，比较所有总线线的代表性延迟，以确定整个总线，并将这个最大延迟应用于其中一个模型。

6. 发明授权

US07453759B2 Clock-gated model transformation for asynchronous testing of logic targeted for free-running, data-gated logic 失效
标题翻译：用于针对自由运行，数据门控逻辑的逻辑的异步测试的时钟门控模型转换
公开(公告)号：US07453759B2
公开(公告)日：2008-11-18
申请号：US11380257
申请日：2006-04-26
申请人： Yee Ja , Bradley S. Nelson , Wolfgang Roesner
发明人： Yee Ja , Bradley S. Nelson , Wolfgang Roesner
IPC分类号： G11C8/00
CPC分类号： G06F17/504 , G06F17/5022 , G06F2217/62
摘要： Asynchronous behavior of a circuit is modeled by modifying latches in a netlist to add an extra port to the latches, e.g., a single-port latch is transformed into a dual-port latch. Each input port has an enable line and a data input. The data input in the added port is a feedback line from the latch output, and the enable line in the added port is the logical NOR of all of the original enable lines. By adding this extra latch port in the higher-level model, it becomes possible to introduce assertion logic to ensure that one and only one latch port for a given latch is ever active during the same simulation cycle. The model can then be tested earlier in the design methodology prior to the availability of the post-synthesis netlist. The model can also be used in both simulation and formal or semi-formal verification.
摘要翻译：电路的异步行为是通过修改网表中的锁存器来增加锁存器的额外端口来建模的，例如，单端口锁存器被转换成双端口锁存器。每个输入端口都有一个使能线和数据输入。添加端口中输入的数据是来自锁存器输出的反馈线，加入端口中的使能线为所有原始使能线的逻辑或。通过在更高级别的模型中添加这个额外的锁存端口，可以引入断言逻辑，以确保给定锁存器中的一个和唯一一个锁存端口在同一仿真周期内始终处于活动状态。然后可以在设计方法之前对该模型进行测试，然后才能获得后合成网表。该模型也可用于模拟和正式或半正式验证。

7. 发明申请

US20080072188A1 System and Method for Modeling Metastability Decay Through Latches in an Integrated Circuit Model 失效
标题翻译：用于通过集成电路模型中的锁存器来计算可逆性衰减的系统和方法
公开(公告)号：US20080072188A1
公开(公告)日：2008-03-20
申请号：US11532575
申请日：2006-09-18
申请人： Yee Ja , Bradley S. Nelson
发明人： Yee Ja , Bradley S. Nelson
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A system and method for modeling metastability decay through latches in an integrated circuit model are provided. With the system and method, asynchronous clock boundaries are identified in the integrated circuit model and latches in a receive clock domain are enumerated. Latches within a range of the asynchronous clock boundary are selected for transformation. These latches are transformed into metastability decay latches using new latch primitive logic that models the decay of an indeterminate value. The metastability decay latches maintains an indeterminate value during a metastability time period and achieve a randomly selected logic value at the end of the metastability time period. The transformed integrated circuit model may then be simulated and the results analyzed to generate reports of the integrated circuit model's operation. The transformed integrate circuit model more accurately represents the actual operation of the hardware implementation of the integrated circuit model.
摘要翻译：提供了一种通过集成电路模型中的锁存器建模亚稳态衰减的系统和方法。利用系统和方法，在集成电路模型中识别异步时钟边界，并枚举接收时钟域中的锁存器。选择异步时钟边界范围内的锁存器进行转换。这些锁存器使用新的锁存原语逻辑转换成亚稳态衰减锁存器，其对不确定值的衰减进行建模。亚稳态衰减锁存器在亚稳态时间段期间保持不确定的值，并在亚稳态时间段结束时实现随机选择的逻辑值。然后可以模拟转换的集成电路模型，并分析结果以生成集成电路模型的操作的报告。转换后的集成电路模型更准确地表示了集成电路模型硬件实现的实际运行。

8. 发明申请

US20080040695A1 System and Method for Accurately Modeling an Asynchronous Interface using Expanded Logic Elements 有权
标题翻译：使用扩展逻辑元件精确建模异步接口的系统和方法
公开(公告)号：US20080040695A1
公开(公告)日：2008-02-14
申请号：US11874620
申请日：2007-10-18
申请人： Bing-Lun Chu , Yee Ja , Bradley Nelson , Wolfgang Roesner
发明人： Bing-Lun Chu , Yee Ja , Bradley Nelson , Wolfgang Roesner
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5031
摘要： A system and method for accurately modeling an asynchronous interface using expanded logic elements are provided. With the apparatus and method, the logic of an asynchronous interface is reduced to primitive logic elements. These primitive logic elements are expanded by the mechanisms of the present invention to take into consideration whether or not the primitive logic elements themselves may be experiencing a switching or glitch hazard and whether or not the inputs to the primitive logic elements may be based on a switching or glitch hazard from another primitive logic element in the asynchronous interface logic. These expanded logic elements are used in an integrated circuit design to replace the original primitive logic elements in the design. The asynchronous interface may then be simulated with the expanded logic elements providing outputs indicative of whether the actual data output of the expanded logic elements is deterministic or not.
摘要翻译：提供了一种使用扩展逻辑元件对异步接口进行精确建模的系统和方法。利用该装置和方法，将异步接口的逻辑简化为原始逻辑元件。这些原始逻辑元件通过本发明的机制来扩展，以考虑原语逻辑元件本身是否可能经历切换或故障危险以及基本逻辑元件的输入是否可以基于切换或异步接口逻辑中另一原始逻辑元件的故障危险。这些扩展的逻辑元件用于集成电路设计中以替代设计中的原始原始逻辑元件。然后可以用扩展的逻辑元件来模拟异步接口，该逻辑元件提供指示扩展的逻辑元件的实际数据输出是否是确定性的输出。

9. 发明申请

US20060190883A1 System and method for unfolding/replicating logic paths to facilitate propagation delay modeling 失效
标题翻译：用于展开/复制逻辑路径以促进传播延迟建模的系统和方法
公开(公告)号：US20060190883A1
公开(公告)日：2006-08-24
申请号：US11054903
申请日：2005-02-10
申请人： Yee Ja , Bradley Nelson
发明人： Yee Ja , Bradley Nelson
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A system and method for unfolding/replicating logic paths to facilitate propagation delay modeling are provided. With the system and method, nets of an integrated circuit design are unfolded and logic of these nets is replicated such that each leg of a fanout can be driven independently from the signal source. In order to unfold the nets, the nets and logic are replicated in the netlist and connected to replicated source and endpoints. These new nets in the netlist may then be driven separately such that a different propagation delay along different nets from the same source may be simulated. In this way, a level of propagation delay may be abstracted into the modeling by driving or delaying each path separately. The transitioning value will then appear to have differing arrival times from the perspective of the sinks.
摘要翻译：提供了用于展开/复制逻辑路径以促进传播延迟建模的系统和方法。利用系统和方法，集成电路设计的网络被展开，并且复制这些网络的逻辑，使得扇出的每个支路可以独立于信号源被驱动。为了展开网络，网络和逻辑在网表中被复制，并连接到复制的源和端点。网表中的这些新网可以单独驱动，从而可以模拟来自相同源的不同网络的不同传播延迟。以这种方式，可以通过单独驱动或延迟每个路径将传播延迟的级别提取到建模中。从汇的角度来看，过渡值似乎有不同的到达时间。

10. 发明授权

US07885801B2 Modeling asynchronous behavior from primary inputs and latches 失效
标题翻译：从主要输入和锁存器建模异步行为
公开(公告)号：US07885801B2
公开(公告)日：2011-02-08
申请号：US12168888
申请日：2008-07-07
申请人： Zoltan T. Hidvegi , Yee Ja , Bradley S. Nelson
发明人： Zoltan T. Hidvegi , Yee Ja , Bradley S. Nelson
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Asynchronous behavior of a circuit is emulated by modifying a netlist to insert additional logic at a driving element such as a latch. The additional logic outputs one of (i) a present output from the driving element, (ii) a delayed output from the driving element, or (iii) a random value, which drives downstream logic. The output of the additional logic is selectively responsive to a user-controlled skew enable input. The invention allows for simpler data skew logic transformations which are applicable to both latches and primary inputs, with no dependencies on any clock net.
摘要翻译：通过修改网表以在诸如锁存器的驱动元件处插入附加逻辑来仿真电路的异步行为。附加逻辑输出（i）来自驱动元件的当前输出，（ii）来自驱动元件的延迟输出，或（iii）驱动下游逻辑的随机值中的一个。附加逻辑的输出选择性地响应于用户控制的偏移使能输入。本发明允许更简单的数据偏移逻辑变换，其可应用于锁存器和主输入，而不依赖于任何时钟网。

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